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@ -517,12 +517,23 @@ static void cpu_execute(rv32_cpu_t* cpu, instruction_t* instruction) |
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cpu->sim_ticks_left = 1; |
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cpu->pc -= 4; |
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break; |
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default: |
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switch(instruction->func7) |
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{ |
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case FUNC7_SFENCEVMA: |
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fprintf(stderr, "SFENCE.VMA: Guest kernel must think we have an MMU. We have none.\n"); |
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break; |
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case FUNC7_WFI: |
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fprintf(stderr, "WFI: Guest kernel must think we have interrupts. We have none.\n"); |
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break; |
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default: |
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fprintf(stderr, "FATAL: Unknown IMM for ECALL/EBREAK instruction while executing (IMM=0x%x)\n", instruction->immediate); |
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exit(EXIT_FAILURE); |
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break; |
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} |
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break; |
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} |
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break; |
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case FUNC3_CSRRW: |
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fprintf(stderr, "CSRRW\n"); |
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break; |
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@ -1052,11 +1063,39 @@ static void cpu_print_instruction(instruction_t* instruction) |
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case IMM_EBREAK: |
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printf("ebreak\n"); |
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break; |
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default: |
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switch(instruction->func7) |
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{ |
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case FUNC7_WFI: |
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printf("wfi\n"); |
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break; |
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case FUNC7_SFENCEVMA: |
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printf("sfence.vma\n"); |
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break; |
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case FUNC7_SINVALVMA: |
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printf("sinval.vma\n"); |
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break; |
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case FUNC7_SFENCEWINVAL_SFENCEINVALIR: |
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switch(instruction->immediate & 0x1F) |
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{ |
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case IMM5_SFENCEWINVAL: |
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printf("sfence.w.inval\n"); |
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break; |
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case IMM5_SFENCEINVALIR: |
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printf("sfence.inval.ir\n"); |
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break; |
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default: |
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fprintf(stderr, "Warning: Unknown IMM for SFENCEWINVAL/SFENCEINVALIR instruction (IMM=0x%x)\n", instruction->immediate); |
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break; |
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} |
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break; |
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default: |
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fprintf(stderr, "Warning: Unknown IMM for ECALL/EBREAK instruction (IMM=0x%x)\n", instruction->immediate); |
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break; |
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} |
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break; |
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} |
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break; |
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case FUNC3_CSRRW: |
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printf("csrrw csr[0x%x], x%u, x%u\n", instruction->immediate, instruction->rd, instruction->rs1); |
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break; |
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