|
|
@ -7,7 +7,8 @@ uint32_t csr_read(struct RV32_CPU* cpu, uint32_t csr) |
|
|
|
{ |
|
|
|
{ |
|
|
|
case CSR_CYCLE: |
|
|
|
case CSR_CYCLE: |
|
|
|
return cpu->sim_ticks_done; |
|
|
|
return cpu->sim_ticks_done; |
|
|
|
break; |
|
|
|
case CSR_SSTATUS: |
|
|
|
|
|
|
|
return csr_read(cpu, CSR_MSTATUS); |
|
|
|
default: |
|
|
|
default: |
|
|
|
break; |
|
|
|
break; |
|
|
|
} |
|
|
|
} |
|
|
@ -17,5 +18,13 @@ uint32_t csr_read(struct RV32_CPU* cpu, uint32_t csr) |
|
|
|
|
|
|
|
|
|
|
|
void csr_write(struct RV32_CPU* cpu, uint32_t csr, uint32_t value) |
|
|
|
void csr_write(struct RV32_CPU* cpu, uint32_t csr, uint32_t value) |
|
|
|
{ |
|
|
|
{ |
|
|
|
|
|
|
|
switch(csr) |
|
|
|
|
|
|
|
{ |
|
|
|
|
|
|
|
case CSR_SSTATUS: |
|
|
|
|
|
|
|
csr_write(cpu, CSR_MSTATUS, value); |
|
|
|
|
|
|
|
return; |
|
|
|
|
|
|
|
default: |
|
|
|
|
|
|
|
break; |
|
|
|
|
|
|
|
} |
|
|
|
cpu->csr[csr] = value; |
|
|
|
cpu->csr[csr] = value; |
|
|
|
} |
|
|
|
} |
|
|
|