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9da9b5045f
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#include "exception.h" |
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#include <stdio.h> |
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void exception_trigger(rv32_cpu_t* cpu, uint32_t scause) |
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{ |
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// An exception can only be triggered by the CPU itself,
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// so we know we already own the mutex
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// We are in the CPU thread itself, but we need
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// the return of this function to be the beginning of
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// the cpu loop
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// To achieve that, we can just call cpu_loop (noreturn)
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// at the end of this function
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// Save execution context, so that 'mret/sret/..' can restore it
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// TODO
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// Set PC to STVEC, and set SCAUSE
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// TODO: If PC cannot be mmu_resolved, throw a 'double fault' ?
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cpu->pc = cpu->csr[CSR_STVEC]; |
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cpu->csr[CSR_SCAUSE] = scause; |
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pthread_mutex_unlock(&cpu0_mutex); |
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cpu_loop(cpu); |
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} |
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#ifndef EXCEPTION_H |
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#define EXCEPTION_H |
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#include "rv32cpu.h" |
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void exception_trigger(rv32_cpu_t* cpu, uint32_t scause); |
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#define SCAUSE_INSTRUCTION_MISSALIGNED 0x0 |
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#define SCAUSE_INSTRUCTION_ACCESS_FAULT 0x1 |
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#define SCAUSE_ILLEGAL_INSTRUCTION 0x2 |
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#define SCAUSE_BREAKPOINT 0x3 |
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#define SCAUSE_LOAD_ACCESS_FAULT 0x5 |
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#define SCAUSE_AMO_ADDRESS_MISALIGNED 0x6 |
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#define SCAUSE_ENVIRONMENT_CALL 0x8 |
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#define SCAUSE_INSTRUCTION_PAGE_FAULT 0xC |
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#define SCAUSE_LOAD_PAGE_FAULT 0xD |
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#define SCAUSE_STORE_AMO_PAGE_FAULT 0xF |
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#endif |
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#include "mmu.h" |
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#include "cpu/exception.h" |
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#include <stdio.h> |
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#include <stdlib.h> |
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extern uint8_t* memory; |
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// Memory Managment Unit implementation
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// We only support Sv32
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#define PAGE_SIZE (4 * 1024) // 4KiB, 2^12B
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#define LEVELS 2 |
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#define PTE_SIZE 4 // sizeof(uint32_t)
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// SATP CSR Register: [MODE(1bit) ASID(9bits) PPN(22bits)]
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#define SATP_MODE (1 << 31) |
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#define SATP_MODE_BARE (0) |
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#define SATP_MODE_SV32 (1 << 31) |
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#define SATP_ASID (0x1FF << 22) |
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#define SATP_PPN (0x3FFFFF) |
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// Page Table entry: [PPN[1](12bits) PPN[0](10bits) RSW(2bits) D A G U X W R V]
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#define PTE_PPN_1(pte) ((pte & 0xFFF00000) >> 20) |
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#define PTE_PPN_0(pte) ((pte & 0x000FFC00) >> 10) |
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#define PTE_PPN(pte) ((pte & 0xFFFFFC00) >> 10) |
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#define PTE_RSW (0b11 << 8) |
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#define PTE_D (1 << 7) |
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#define PTE_A (1 << 6) |
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#define PTE_G (1 << 5) |
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#define PTE_U (1 << 4) |
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#define PTE_X (1 << 3) |
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#define PTE_W (1 << 2) |
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#define PTE_R (1 << 1) |
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#define PTE_V (1 << 0) |
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// Physical address: 34 bits [PPN[1](12bits, ) PPN[0](10bits) Offset(12bits)]
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// We only use 32-bits addresses, so the top 2 are always 0
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#define PADDR_PAGE_OFFSET (0x00000FFF) |
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// Virtual address: [VPN[1](10bits) VPN[0](10bits) Offset(12bits)]
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#define VADDR_VPN_1 (0xFFC00000) |
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#define VADDR_VPN_0 (0x003FF000) |
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#define VADDR_PAGE_OFFSET (0x00000FFF) |
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uint32_t mmu_resolve(rv32_cpu_t* cpu, uint32_t vaddr) |
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{ |
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// TODO: Make sure we are in S-mode or U-mode
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// Check if MODE field is 'bare', meaning no mmu
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if((cpu->csr[CSR_SATP] & SATP_MODE) == SATP_MODE_BARE) |
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return vaddr; |
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// fprintf(stderr, "MMU enabled on (virtual) address 0x%x resolution\n", vaddr);
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uint32_t page_table = (cpu->csr[CSR_SATP] & SATP_PPN) * PAGE_SIZE; |
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// Resolve first-level page table entry
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uint32_t vpn_1 = (vaddr & VADDR_VPN_1) >> 22; |
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uint32_t pte_address = page_table + vpn_1 * PTE_SIZE; |
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uint32_t pte = *((uint32_t*) (&memory[pte_address])); |
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if(!(pte & PTE_V)) |
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{ |
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// Invalid PTE
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// TODO : Add a MEMORY_ACCESS_TYPE
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exception_trigger(cpu, SCAUSE_INSTRUCTION_PAGE_FAULT); |
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} |
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if((pte & PTE_R) || (pte & PTE_W) || (pte & PTE_X)) |
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{ |
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// Leaf PTE, we are ready to resolve the mapping
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// This is a 4 MiB megapage
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// Physical Address: [PPN[1] = pte.PPN[1], PPN[0] = vaddr.VPN[0], offset]
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uint32_t paddr = 0; |
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paddr |= (PTE_PPN_1(pte) << 22); |
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paddr |= (vaddr & VADDR_VPN_0); |
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paddr |= vaddr & VADDR_PAGE_OFFSET; |
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return paddr; |
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} |
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// PTE is a pointer to next level of page table
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page_table = PTE_PPN(pte) * PAGE_SIZE; |
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// Resolve second-level page table entry
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uint32_t vpn_0 = (vaddr & VADDR_VPN_0) >> 12; |
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pte_address = page_table + vpn_0 * PTE_SIZE; |
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pte = *((uint32_t*) (&memory[pte_address])); |
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if(!(pte & PTE_V)) |
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{ |
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// Invalid PTE
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exception_trigger(cpu, SCAUSE_INSTRUCTION_PAGE_FAULT); |
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} |
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// This must be a leaf PTE, as Sv32 only supports 2-level mappings
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// This is a 4 KiB page
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if(!((pte & PTE_R) || (pte & PTE_W) || (pte & PTE_X))) |
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{ |
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fprintf(stderr, "Error: Pointer second-level Page Table Entry 0x%x at 0x%x while resolving virtual address 0x%x\n", pte, pte_address, vaddr); |
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exit(EXIT_FAILURE); |
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} |
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// Physical Address: [PPN[1] = pte.PPN[1], PPN[0] = pte.PPN[0], offset]
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uint32_t paddr = 0; |
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paddr |= (PTE_PPN_1(pte) << 22); |
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paddr |= (PTE_PPN_0(pte) << 12); |
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paddr |= vaddr & VADDR_PAGE_OFFSET; |
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return paddr; |
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} |
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@ -0,0 +1,9 @@ |
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#ifndef MMU_H |
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#define MMU_H |
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#include <stdint.h> |
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#include "cpu/rv32cpu.h" |
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uint32_t mmu_resolve(rv32_cpu_t* cpu, uint32_t vaddr); |
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#endif |
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