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@ -93,6 +93,7 @@ static void cpu_decode(raw_instruction_t raw_instruction, instruction_t* output) |
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break; |
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break; |
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// R-type instructions
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// R-type instructions
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case OPCODE_ARITHLOG: |
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case OPCODE_ARITHLOG: |
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case OPCODE_ATOMIC: |
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break; |
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break; |
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// S-type instructions
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// S-type instructions
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case OPCODE_STORE: |
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case OPCODE_STORE: |
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@ -118,22 +119,19 @@ static void cpu_execute(rv32_cpu_t* cpu, instruction_t* instruction) |
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case OPCODE_LUI: |
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case OPCODE_LUI: |
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{ |
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{ |
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// Load Upper Immediate (load immediate(31:12 bits) in rd)
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// Load Upper Immediate (load immediate(31:12 bits) in rd)
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if(instruction->rd) |
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cpu->regs.x[instruction->rd] = instruction->immediate; |
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cpu->regs.x[instruction->rd] = instruction->immediate; |
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break; |
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break; |
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} |
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} |
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case OPCODE_AUIPC: |
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case OPCODE_AUIPC: |
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{ |
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{ |
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// Add Upper Immediate to PC
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// Add Upper Immediate to PC
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if(instruction->rd) |
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cpu->regs.x[instruction->rd] = instruction->immediate + cpu->pc; |
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cpu->regs.x[instruction->rd] = instruction->immediate + cpu->pc; |
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break; |
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break; |
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} |
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} |
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case OPCODE_JAL: |
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case OPCODE_JAL: |
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{ |
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{ |
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// Jump And Link
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// Jump And Link
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if(instruction->rd) |
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cpu->regs.x[instruction->rd] = cpu->pc + 4; |
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cpu->regs.x[instruction->rd] = cpu->pc + 4; |
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// Sign extend immediate from 21 bits to 32 bits
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// Sign extend immediate from 21 bits to 32 bits
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uint32_t immediate = (instruction->immediate & 0x1FFFFF) | (instruction->immediate & 0x100000 ? 0xFFE00000 : 0); |
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uint32_t immediate = (instruction->immediate & 0x1FFFFF) | (instruction->immediate & 0x100000 ? 0xFFE00000 : 0); |
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cpu->pc += immediate - 4; |
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cpu->pc += immediate - 4; |
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@ -142,8 +140,7 @@ static void cpu_execute(rv32_cpu_t* cpu, instruction_t* instruction) |
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case OPCODE_JALR: |
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case OPCODE_JALR: |
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{ |
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{ |
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// Jump And Link Register
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// Jump And Link Register
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if(instruction->rd) |
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cpu->regs.x[instruction->rd] = cpu->pc + 4; |
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cpu->regs.x[instruction->rd] = cpu->pc + 4; |
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// Sign extend immediate from 12 bits to 32 bits
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// Sign extend immediate from 12 bits to 32 bits
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uint32_t immediate = (instruction->immediate & 0xFFF) | (instruction->immediate & 0x800 ? 0xFFFFF000 : 0); |
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uint32_t immediate = (instruction->immediate & 0xFFF) | (instruction->immediate & 0x800 ? 0xFFFFF000 : 0); |
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cpu->pc = ((cpu->regs.x[instruction->rs1] + immediate) & 0xFFFFFFFE) - 4; |
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cpu->pc = ((cpu->regs.x[instruction->rs1] + immediate) & 0xFFFFFFFE) - 4; |
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@ -460,6 +457,97 @@ static void cpu_execute(rv32_cpu_t* cpu, instruction_t* instruction) |
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break; |
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break; |
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} |
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} |
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case OPCODE_ATOMIC: |
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{ |
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// Atomic instructions (A extension)
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// To find out which operation, we must analyse func7 (func3 == 0x2)
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if(instruction->func3 != FUNC3_ATOMIC) |
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{ |
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fprintf(stderr, "FATAL: Unknown func3 0x%x for ATOMIC instruction, could not execute\n", instruction->func3); |
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exit(EXIT_FAILURE); |
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} |
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// FUNC7 contains 2 flag bits in lower part ; ignore them, we look for func7_5
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uint32_t address = cpu->regs.x[instruction->rs1]; |
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uint32_t* ptr = ((uint32_t*) &memory[mmu_translate(address)]); |
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switch(instruction->func7 >> 2) |
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{ |
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case FUNC75_LRW: |
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// Load-Reserved Word
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cpu->regs.x[instruction->rd] = *ptr; |
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// TODO register reservation set that subsumes the bytes in word
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fprintf(stderr, "LR.W\n"); |
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break; |
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case FUNC75_SCW: |
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// Store-Conditional Word
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// TODO succeed only if the reservation is still valid and the reservation set contains the bytes written
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*ptr = cpu->regs.x[instruction->rs2]; |
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cpu->regs.x[instruction->rd] = 0; // TODO write 1 in rd on failure
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fprintf(stderr, "SC.W\n"); |
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break; |
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case FUNC75_AMOSWAPW: |
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// Atomic Memory Operation SWAP Word
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cpu->regs.x[instruction->rd] = *ptr; |
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// Put in RS1 addr the value of RS2
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*ptr = cpu->regs.x[instruction->rs2]; |
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// Put in RS2 the value of RS1 addr (which is in RD)
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cpu->regs.x[instruction->rs2] = cpu->regs.x[instruction->rd]; |
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break; |
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case FUNC75_AMOADDW: |
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// Atomic Memory Operation ADD Word
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cpu->regs.x[instruction->rd] = *ptr; |
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// Add rs1 addr and value of rs2
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*ptr = cpu->regs.x[instruction->rd] + cpu->regs.x[instruction->rs2]; |
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break; |
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case FUNC75_AMOXORW: |
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// Atomic Memory Operation XOR Word
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cpu->regs.x[instruction->rd] = *ptr; |
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// Xor rs1 addr and value of rs2
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*ptr = cpu->regs.x[instruction->rd] ^ cpu->regs.x[instruction->rs2]; |
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break; |
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case FUNC75_AMOANDW: |
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// Atomic Memory Operation AND Word
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cpu->regs.x[instruction->rd] = *ptr; |
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// AND rs1 addr and value of rs2
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*ptr = cpu->regs.x[instruction->rd] & cpu->regs.x[instruction->rs2]; |
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break; |
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case FUNC75_AMOORW: |
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// Atomic Memory Operation OR Word
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cpu->regs.x[instruction->rd] = *ptr; |
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// Or rs1 addr and value of rs2
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*ptr = cpu->regs.x[instruction->rd] | cpu->regs.x[instruction->rs2]; |
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break; |
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case FUNC75_AMOMINW: |
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// Atomic Memory Operation MIN Word
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cpu->regs.x[instruction->rd] = *ptr; |
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// Min rs1 addr and value of rs2
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*ptr = ((int32_t) cpu->regs.x[instruction->rd]) < ((int32_t) cpu->regs.x[instruction->rs2]) ? cpu->regs.x[instruction->rd] : cpu->regs.x[instruction->rs2]; |
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break; |
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case FUNC75_AMOMAXW: |
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// Atomic Memory Operation MAX Word
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cpu->regs.x[instruction->rd] = *ptr; |
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// Max rs1 addr and value of rs2
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*ptr = ((int32_t) cpu->regs.x[instruction->rd]) > ((int32_t) cpu->regs.x[instruction->rs2]) ? cpu->regs.x[instruction->rd] : cpu->regs.x[instruction->rs2]; |
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break; |
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case FUNC75_AMOMINUW: |
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// Atomic Memory Operation MIN Unsigned Word
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cpu->regs.x[instruction->rd] = *ptr; |
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// Min rs1 addr and value of rs2
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*ptr = cpu->regs.x[instruction->rd] < cpu->regs.x[instruction->rs2] ? cpu->regs.x[instruction->rd] : cpu->regs.x[instruction->rs2]; |
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break; |
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case FUNC75_AMOMAXUW: |
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// Atomic Memory Operation MAX Unsigned Word
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cpu->regs.x[instruction->rd] = *ptr; |
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// Max rs1 addr and value of rs2
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*ptr = cpu->regs.x[instruction->rd] > cpu->regs.x[instruction->rs2] ? cpu->regs.x[instruction->rd] : cpu->regs.x[instruction->rs2]; |
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break; |
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default: |
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fprintf(stderr, "FATAL: Unknown func7 0x%x for ATOMIC/0x2 instruction, could not execute\n", instruction->func7); |
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exit(EXIT_FAILURE); |
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break; |
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} |
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break; |
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} |
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default: |
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default: |
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fprintf(stderr, "FATAL: Unknown instruction opcode 0x%x while executing; how could this decode ?\n", instruction->opcode); |
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fprintf(stderr, "FATAL: Unknown instruction opcode 0x%x while executing; how could this decode ?\n", instruction->opcode); |
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exit(EXIT_FAILURE); |
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exit(EXIT_FAILURE); |
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@ -490,6 +578,9 @@ void cpu_loop(rv32_cpu_t* cpu) |
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// Execute
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// Execute
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cpu_execute(cpu, &instruction); |
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cpu_execute(cpu, &instruction); |
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// Reset value of zero, in case instruction tried to modify
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cpu->regs.zero = 0; |
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cpu->pc += 4; |
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cpu->pc += 4; |
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} |
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} |
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} |
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} |
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@ -799,6 +890,70 @@ static void cpu_print_instruction(instruction_t* instruction) |
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} |
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} |
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break; |
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break; |
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} |
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} |
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case OPCODE_ATOMIC: |
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{ |
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// Atomic instructions (A extension)
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// To find out which operation, we must analyse func7 (func3 == 0x2)
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if(instruction->func3 != FUNC3_ATOMIC) |
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{ |
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fprintf(stderr, "Warning: Unknown func3 0x%x for ATOMIC instruction\n", instruction->func3); |
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break; |
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} |
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// FUNC7 contains 2 flag bits in lower part ; ignore them, we look for func7_5
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switch(instruction->func7 >> 2) |
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{ |
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case FUNC75_LRW: |
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// Load-Reserved Word
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printf("lr.w x%u, x%u\n", instruction->rd, instruction->rs1); |
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break; |
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case FUNC75_SCW: |
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// Store-Conditional Word
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printf("sc.w x%u, x%u, x%u\n", instruction->rd, instruction->rs1, instruction->rs2); |
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break; |
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case FUNC75_AMOSWAPW: |
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// Atomic Memory Operation SWAP Word
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printf("amoswap.w x%u, x%u, x%u\n", instruction->rd, instruction->rs1, instruction->rs2); |
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break; |
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case FUNC75_AMOADDW: |
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// Atomic Memory Operation ADD Word
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printf("amoadd.w x%u, x%u, x%u\n", instruction->rd, instruction->rs1, instruction->rs2); |
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break; |
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case FUNC75_AMOXORW: |
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// Atomic Memory Operation XOR Word
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printf("amoxor.w x%u, x%u, x%u\n", instruction->rd, instruction->rs1, instruction->rs2); |
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break; |
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case FUNC75_AMOANDW: |
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// Atomic Memory Operation AND Word
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printf("amoand.w x%u, x%u, x%u\n", instruction->rd, instruction->rs1, instruction->rs2); |
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break; |
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case FUNC75_AMOORW: |
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// Atomic Memory Operation OR Word
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printf("amoor.w x%u, x%u, x%u\n", instruction->rd, instruction->rs1, instruction->rs2); |
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break; |
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case FUNC75_AMOMINW: |
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// Atomic Memory Operation MIN Word
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printf("amomin.w x%u, x%u, x%u\n", instruction->rd, instruction->rs1, instruction->rs2); |
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break; |
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case FUNC75_AMOMAXW: |
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// Atomic Memory Operation MAX Word
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printf("amomax.w x%u, x%u, x%u\n", instruction->rd, instruction->rs1, instruction->rs2); |
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break; |
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case FUNC75_AMOMINUW: |
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// Atomic Memory Operation MIN Unsigned Word
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printf("amominu.w x%u, x%u, x%u\n", instruction->rd, instruction->rs1, instruction->rs2); |
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break; |
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case FUNC75_AMOMAXUW: |
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// Atomic Memory Operation MAX Unsigned Word
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printf("amomaxu.w x%u, x%u, x%u\n", instruction->rd, instruction->rs1, instruction->rs2); |
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break; |
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default: |
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fprintf(stderr, "FATAL: Unknown func7 0x%x for ATOMIC/0x2 instruction, could not execute\n", instruction->func7); |
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exit(EXIT_FAILURE); |
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break; |
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} |
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break; |
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} |
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default: |
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default: |
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fprintf(stderr, "Warning: Unknown instruction opcode 0x%x while printing\n", instruction->opcode); |
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fprintf(stderr, "Warning: Unknown instruction opcode 0x%x while printing\n", instruction->opcode); |
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break; |
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|
break; |
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|