2023-10-04 21:28:18 +02:00
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# vriscv - a risc-v simulator
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2023-11-03 16:36:21 +01:00
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Linux and the BBL bootloader can be downloaded, built, and ran on the simulator using:
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```
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make run
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```
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2023-10-08 21:50:06 +02:00
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## Unit tests
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Unit tests can be compiled and run using :
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```
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make tests
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```
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2023-10-04 21:28:18 +02:00
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## Resources used
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2023-10-09 19:48:12 +02:00
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RISC-V Specifications:
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- https://five-embeddev.com/riscv-isa-manual/latest/instr-table.html (instruction table)
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- https://five-embeddev.com/riscv-isa-manual/latest/priv-instr-table.html (privileged instructions)
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2023-10-17 13:25:31 +02:00
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Device Tree Source :
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- https://elinux.org/Device_Tree_Usage
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2023-10-04 21:28:18 +02:00
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Juraj's Blog, mostly:
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- https://jborza.com/post/2021-04-04-riscv-supervisor-mode/
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- https://jborza.com/emulation/2021/04/22/ecalls-and-syscalls.html
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2023-10-05 11:16:06 +02:00
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RISC-V SBI Specifications:
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- https://github.com/riscv-non-isa/riscv-sbi-doc/releases
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