Ilias ApalodimasandTom Rini
1174c99ab4
Currently, the bi_dram[] information is stored in the board info structure (bd). Because bd is only valid after reserve_board(), dram_init_banksize() must be called late in the initialization process. This limitation is problematic, as it forces us to rely on a variety of bespoke functions to determine board RAM, bank memory sizes, and other early setup requirements. By moving bi_dram[] into the global data (gd), we can run it earlier. This is particularly convenient since boards define their own dram_init_banksize() routines, which do not always rely on parsing Device Tree (DT) memory nodes. Additionally, U-Boot defaults to relocating to the top of the first memory bank. While boards currently use custom functions to override this behavior, having the DRAM bank information available earlier in gd makes relocating to a different bank trivial and standardizes the process. Reviewed-by: Anshul Dalal <anshuld@ti.com> Tested-by: Michal Simek <michal.simek@amd.com> # Versal Gen 2 Vek385 Tested-by: Anshul Dalal <anshuld@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Tested-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
127 lines
2.9 KiB
C
127 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* (C) Copyright 2016 - 2018 Xilinx, Inc.
|
|
* Michal Simek <michal.simek@amd.com>
|
|
*/
|
|
|
|
#include <init.h>
|
|
#include <asm/armv8/mmu.h>
|
|
#include <asm/cache.h>
|
|
#include <asm/global_data.h>
|
|
#include <asm/io.h>
|
|
#include <asm/arch/hardware.h>
|
|
#include <asm/arch/sys_proto.h>
|
|
#include <asm/cache.h>
|
|
#include <dm/platdata.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
#define VERSAL_MEM_MAP_USED 5
|
|
|
|
#define DRAM_BANKS CONFIG_NR_DRAM_BANKS
|
|
|
|
#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
|
|
#define TCM_MAP 1
|
|
#else
|
|
#define TCM_MAP 0
|
|
#endif
|
|
|
|
/* +1 is end of list which needs to be empty */
|
|
#define VERSAL_MEM_MAP_MAX (VERSAL_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
|
|
|
|
static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = {
|
|
{
|
|
.virt = 0x80000000UL,
|
|
.phys = 0x80000000UL,
|
|
.size = 0x70000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE |
|
|
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
}, {
|
|
.virt = 0xf0000000UL,
|
|
.phys = 0xf0000000UL,
|
|
.size = 0x0fe00000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE |
|
|
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
}, {
|
|
.virt = 0x400000000UL,
|
|
.phys = 0x400000000UL,
|
|
.size = 0x200000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE |
|
|
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
}, {
|
|
.virt = 0x600000000UL,
|
|
.phys = 0x600000000UL,
|
|
.size = 0x800000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
.virt = 0xe00000000UL,
|
|
.phys = 0xe00000000UL,
|
|
.size = 0xf200000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE |
|
|
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
}
|
|
};
|
|
|
|
void mem_map_fill(void)
|
|
{
|
|
int banks = VERSAL_MEM_MAP_USED;
|
|
|
|
#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
|
|
versal_mem_map[banks].virt = 0xffe00000UL;
|
|
versal_mem_map[banks].phys = 0xffe00000UL;
|
|
versal_mem_map[banks].size = 0x00200000UL;
|
|
versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE;
|
|
banks = banks + 1;
|
|
#endif
|
|
|
|
for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
|
|
/* Zero size means no more DDR that's this is end */
|
|
if (!gd->dram[i].size)
|
|
break;
|
|
|
|
#if defined(CONFIG_VERSAL_NO_DDR)
|
|
if (gd->dram[i].start < 0x80000000UL ||
|
|
gd->dram[i].start > 0x100000000UL) {
|
|
printf("Ignore caches over %llx/%llx\n",
|
|
gd->dram[i].start,
|
|
gd->dram[i].size);
|
|
continue;
|
|
}
|
|
#endif
|
|
versal_mem_map[banks].virt = gd->dram[i].start;
|
|
versal_mem_map[banks].phys = gd->dram[i].start;
|
|
versal_mem_map[banks].size = gd->dram[i].size;
|
|
versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE;
|
|
banks = banks + 1;
|
|
}
|
|
}
|
|
|
|
struct mm_region *mem_map = versal_mem_map;
|
|
|
|
u64 get_page_table_size(void)
|
|
{
|
|
return 0x14000;
|
|
}
|
|
|
|
#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU)
|
|
int arm_reserve_mmu(void)
|
|
{
|
|
tcm_init(TCM_LOCK);
|
|
gd->arch.tlb_size = PGTABLE_SIZE;
|
|
gd->arch.tlb_addr = VERSAL_TCM_BASE_ADDR;
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
U_BOOT_DRVINFO(soc_xilinx_versal) = {
|
|
.name = "soc_xilinx_versal",
|
|
};
|