Currently we don't properly map between the regulator mode ID enum and
the appropriate register values in the mode map, as a result we always
unintentionally vote for retention mode if we actually attempt to set
it. In the set_mode path we did find the appropriate entry in the mode
map but we wrote the id instead of the register values. Clean this up
and properly map id -> mode and vice versa.
Link: https://patch.msgid.link/20260108-rpmh-regulator-fixes-v1-6-d1b5b300b665@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Make use of the new RPMh read support to fetch regulator values that may
have been voted on by a previous bootloader stage. This allows commands
like "regulator status" to report the actual votes programmed into
hardware (though not necessarily the actual states of the regulators
once the votes have been aggregated).
Link: https://patch.msgid.link/20260108-rpmh-regulator-fixes-v1-5-d1b5b300b665@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Several bugs were discovered in the rpmh-rsc driver which collectively
meant we were never actually waiting for the TCS to flush, these were
likely missed because U-Boot runs single threaded and the RPMh had
typically processed the single command we sent by the time we went
to send the next one. However a future patch will implement rpmh read
support which requires us to properly wait for the RPMh command response
so we can return the value.
Fix these issues so we correctly ensure the TCS is done before
returning.
Link: https://patch.msgid.link/20260108-rpmh-regulator-fixes-v1-3-d1b5b300b665@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
If we don't reclaim and clear the IRQ bits, we might get a spurious
interrupt from this TCS in Linux:
WARNING: CPU: 0 PID: 0 at drivers/soc/qcom/rpmh-rsc.c:451 tcs_tx_done+0x98/0x270
...
Call trace:
tcs_tx_done+0x98/0x270 (P)
__handle_irq_event_percpu+0x60/0x220
handle_irq_event+0x54/0xc0
handle_fasteoi_irq+0xa8/0x1c0
handle_irq_desc+0x3c/0x68
generic_handle_domain_irq+0x24/0x40
gic_handle_irq+0x5c/0xd0
...
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260108-rpmh-regulator-fixes-v1-1-d1b5b300b665@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
PMIC Arbiter may expose multiple owned and non-owned APIDs per SID/PID.
- Keep current mapping if it is OWNED and a NON-OWNED appears.
- Always update when a NEW OWNED APID appears (make writable).
- If current is NON-OWNED and a new NON-OWNED appears, update to it
(remain read-only).
This avoids write-access violations when not using the newly discovered
owned channels.
Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Link: https://patch.msgid.link/20260107153504.550450-1-aswin.murugan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
When 'max-clk' is not specified, the SDHCI core retrieves the base clock
from the SDHCI_CAPABILITIES register (bits [15:8]). However, this field
is unreliable on MSM SDHCI controllers, as noted by the Linux driver
using the SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN flag. In addition, the field
is only 8 bits wide and cannot represent base clocks above 255 MHz.
On platforms like Agatti/QCM2290, the firmware sets the SDHCI clock to
384 MHz, but the capabilities register reports 200 MHz. As a result,
the core calculates a divider of 4, producing a 96 MHz SDCLK instead of
the intended ~52 MHz. This overclocking can cause sporadic CRC errors
with certain eMMC.
To fix this, use the actual clock rate reported by the SDHCI core clock
instead of relying on the capabilities register for divider calculation.
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://patch.msgid.link/20251210155454.1561611-1-loic.poulain@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
The SMEM driver was failing to resolve memory regions on some boards
because `dev_of_offset()` + `fdtdec_lookup_phandle()` did not yield a
valid DT node. Modernize the code to use driver-model/ofnode accessors
and make the probe robust for both DT styles (direct `reg` vs
`memory-region` phandle).
- qcom_smem_map_memory():
* Drop fdtdec path; use dev_read_phandle_with_args() +
ofnode_read_resource().
* Use dev_read_phandle_with_args() +
fnode_read_resource().
- qcom_smem_probe():
* Try dev_read_addr_size() first (map via <reg>), else fall back to
qcom_smem_map_memory() with "memory-region".
* Check "qcom,rpm-msg-ram" presence to add second region.
- Additionally, SMEM_HOST_COUNT is increased to support newer SMEM
versions that include more remote processors. This avoids failures
during processor ID checks.
Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Reviewed-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Link: https://patch.msgid.link/20251112165851.1561418-1-aswin.murugan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Currently (since 2026.01-rc) on all SDM630/660 based devices this is
printed, after observing long boot delay (several seconds) before
executing preboot commands:
QCOM-FMP: Failed to find boot partition
find_target_partition() function incorrectly assumes that eMMC is always
at number 0. In general you can't rely on device numbering to determine if
particular block device is eMMC or SD-card, because it depends on how
aliases are defined in device tree "chosen" node. Some SoCs have MMC
numbers starting at 1, not 0; so mmc1 is eMMC, mmc2 is SD-card.
Make eMMC detection reliable by using IS_SD() macro from mmc.h header.
Using this method target boot partition can be found successfully.
With debug prints enabled, this is printed:
QCOM-FMP: skipped SD-Card (devnum 2)
QCOM-FMP: Capsule update target: boot (disk 1:60)
QCOM-FMP: DFU string: 'mmc 0=u-boot.bin part 1 60'
Without debug prints nothing is printed, no error about failure to find
boot partition.
Fixes: fe80a5f800 ("mach-snapdragon: CapsuleUpdate: support all boot methods")
Signed-off-by: Alexey Minnekhanov <alexeymin@minlexx.ru>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20251107232935.283843-1-alexeymin@minlexx.ru
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Added a check to ensure the requested timeout does not exceed the
hardware's maximum supported value. This prevents register overflow
and ensures watchdog reliability.
So, added a check in qcom_wdt_start() to ensure the requested timeout
does not exceed the hardware-supported maximum value. If the requested
value exceeds the maximum value, then the timeout is clamped
at maximum value.
The timeout is first converted to watchdog ticks and then compared
against QCOM_WDT_MAX_TIMEOUT. This helps prevent misconfiguration
and potential watchdog misbehavior due to overflow.
QCOM_WDT_MAX_TIMEOUT is set to 0xFFFFF, as Qualcomm SoCs typically
use 20 bits to store bark/bite timeout values.
This work builds upon the previous submission:
https://lore.kernel.org/u-boot/20250527124926.128413-1-balaji.selvanathan@oss.qualcomm.com/
Signed-off-by: Gopinath Sekar <gopinath.sekar@oss.qualcomm.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Link: https://patch.msgid.link/20250625094607.1348494-1-gopinath.sekar@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
This patch is not as E Shattow authored it, but contains non-trivial
changes from Heinrich Schuchardt as well. The original author has
requested that this commit be reverted until the changes can be
committed showing which parts were authored by E Shattow and which by
Heinrich Schuchardt.
This reverts commit 4c105d2ae7.
Signed-off-by: Tom Rini <trini@konsulko.com>
Make crypt_compare() accessible from board-specific code
by removing its dependency on the autoboot feature.
Signed-off-by: Tomas Paukrt <tomaspaukrt@email.cz>
Reviewed-by: Tom Rini <trini@konsulko.com>
The "fixed-layout" nvmem controller subnode used to be optional wrapper
around nvmem controller cells subnodes. The "fixed-layout" node is now
mandatory in most cases, but in order to support both recent and legacy
DTs, both variants have to be supported.
Implement support for the "fixed-layout" node in the most trivial manner,
check whether the nvmem cell supernode is compatible with "fixed-layout"
and if it is, proceed one level above it to find the nvmem controller.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Peripheral registers on MPC83xx-series chips are declared in
immap_83xx.h as a set of structs that ultimately fill the entire MMIO
space of 1 MiB. This patch introduces a compile-time check of the size
of each peripheral struct. The purpose of these checks is two-fold:
1. To quickly tell readers of the code the total size of each struct
2. To verify that the size does not change when a struct is edited
If the size of a peripheral struct were to change by a few bytes due
to an editing error, the result would be mayhem for all following
peripherals, because all offsets would shift by the amount of the error.
All new checks have been compile-tested.
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
This platform is unfortunately frequently very close to the binary
size limit. Currently it is so close that generic bug fixes can trigger
build failure. Remove the license command from the image as that frees
up nearly 7KiB of space.
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
The AM571x SoC has 1 GB DDR space. As part of normal re-location process
U-Boot copies itself to the top of DDR bank. However, on HS devices, the
top 37 MB is used by PPA and is firewalled. This results in an exception
and the boot fails. Set CONFIG_SYS_MEM_TOP_HIDE to reserve the top 38 MB
memory (aligned to 2MB as per page size for ARM32) to fix the boot.
Note: This limitation does not exist for other AM57x devices, but this
config is applied in the common defconfig since adding a separate
defconfig only for AM571x is not justified. Losing 38MB of memory at the
bootloader stage on other devices is acceptable.
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Add a requirements.txt file to the pylibfdt script directory to specify
setuptools as a dependency. This follows the pattern of each tool in
U-Boot having its own requirements.txt file. The version is set to
78.1.1 to avoid conflict with the same in tools/patman/requirements.txt.
Reviewed-by: Simon Glass <simon.glass@canonical.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> # sandbox
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Add a paragraph explaining that in addition to the requirements.txt
for test/py/test.py itself, users may need to install additional python
packages depending on the U-Boot configuration being built.
Reviewed-by: Simon Glass <simon.glass@canonical.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> # sandbox
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Set ubconfig to None and add a check in the show_timings() function of
test/py/test.py to ensure that the global ubconfig variable was actually
initialized before access attributes.
If tests fail early, e.g. because --build failed, ubconfig may not have
been initialized yet and results in an exception in an atexit handler.
Adding this check avoids unnecessary noise in the output.
Exception ignored in atexit callback: <function cleanup at 0x7de475ea6b60>
Traceback (most recent call last):
File "u-boot/test/py/conftest.py", line 669, in cleanup
show_timings()
File "u-boot/test/py/conftest.py", line 616, in show_timings
if ubconfig.timing:
^^^^^^^^
NameError: name 'ubconfig' is not defined
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> # sandbox
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner <dlechner@baylibre.com> says:
MT8365 has different pinctrl register layout compared to other SoCs in
the family, so needs its own driver.
This is also the first SoC in this family supported in U-Boot using an
upstream devicetree that has the mediatek,pctl-regmap property, so we
need to add support for that to the common mediatek pinctrl code first.
Link: https://lore.kernel.org/r/20260106-pinctl-mtk-mt8365-v1-0-0ca3eb382468@baylibre.com
Add support for the mediatek,pctl-regmap devicetree property to the
common MediaTek pinctrl driver.
In upstream devicetrees from Linux, the pinctrl nodes may be on the
interrupt controller register address space rather than the pinctrl
register address space. In this case, there is a syscon node linking to
the actual pinctrl registers. This uses a common property name of
mediatek,pctl-regmap for the phandle to the syscon node.
The logic here is that if this property is present, we look up the
syscon node and use it's address as the base address of the pinctrl
registers and ignore the pinctrl node's own reg property. (Support
for interrupts could be added later if needed.)
There is also at least one SoC in Linux that has two syscon phandles
in this property. This implementation support parsing this, but doesn't
do anything with the second syscon yet (the 2nd syscon is for interrupts
which we are saving for later).
Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner <dlechner@baylibre.com> says:
There were a number of bugs in the clock definitions for the mt8365
clock drivers. This series aims to fix the obvious issues.
This builds on [1] that implements the clk dump command to inspect the
clock trees at runtime. Using that revealed quite a few mistakes in
the clock definitions.
Additionally, the topckgen-cg hack is removed for mt8365 since it would
require an extra devicetree node using the same address space as the
topckgen node. This would not be accepted upstream in Linux, so we
shouldn't do it in U-Boot either. mt85{12,16,18} also have this hack.
I didn't attempt to remove it from those platforms since I don't have
hardware to test on.
Patches have been runtime tested on mt8365_evk hardware and compile-
tested on other platforms using:
./tools/buildman/buildman --boards=mt7986a_bpir3_sd,mt7620_rfb,mt7986_rfb,mt7987_emmc_rfb,mt7987_rfb,mt7622_rfb,mt7987_sd_rfb,mt7623a_unielec_u7623_02,mt7988_rfb,mt7623n_bpir2,mt7988_sd_rfb,mt7628_rfb,mt8183_pumpkin,mt7629_rfb,mt8365_evk,mt7981_emmc_rfb,mt8512_bm1_emmc,mt7981_rfb,mt8516_pumpkin,mt7981_sd_rfb,mt8518_ap1_emmc -b HEAD -c 9
[1]: https://lore.kernel.org/u-boot/20251218-clk-mtk-improvements-v1-0-72db131ba148@baylibre.com/
Link: https://lore.kernel.org/r/20260107-clk-mtk-mt8365-fixes-v2-0-3294a5d2f239@baylibre.com
Use a ID map to add clocks for the missing CLK_TOP_CLK32K and
CLK_TOP_CLK26M that were not included in the devicetree definitions.
This fixes getting the rate of any clock that had one of these as a
parent.
CLK_TOP_UNIVPLL does not appear to be a real clock, so it is omitted
now since we can do that with the ID map as well.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Remove the separate topckgen-cg driver for handling clock gates in the
topckgen address space. The devicetree bindings for this were not
acceptable upstream because it was creating a separate clock controller
using the same address space as the main topckgen clock controller. The
gates are moved to the topckgen tree instead.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Add handling for gates in the topckgen clk drivers. This avoids the need
to have separate topckgen-cg drivers and devicetree nodes for the same
address space and clock ID range.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Split the struct mtk_clk_tree for MT8365 into separate structures for
the apmixedsys, topckgen and infracfg clock controllers. This is needed
to support moving the topckgen gates into the struct mtk_clk_tree. Since
apmixedsys can also have gates, we need separate structures.
Signed-off-by: David Lechner <dlechner@baylibre.com>
