Add the driver for the Airoha EN8811H 2.5 Gigabit PHY. The PHY supports
100/1000/2500 Mbps with auto negotiation only.
The driver uses two firmware files, for which updated versions are added to
linux-firmware already.
Based on the Linux upstream 8811 driver code(air_en8811h.c),
I have modified the relevant process to align with the U-Boot boot sequence.
and have validated this on Banana Pi BPI-R3 Mini.
The MD32 FW is currently stored in eMMC partition 1 on Banana Pi BPI-R3 Mini,
and it is loaded from there.
Signed-off-by: Lucien.Jheng <lucienzx159@gmail.com>
As the code is today, we get a warning about "select" statements on
"choice" options not doing anything. However, it also works as intended
because SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is the default option
within that choice statement. To guard against future regressions, make
the choice statement in common/spl/Kconfig have an explicit default if
MVEBU_SPL_BOOT_DEVICE_MMC.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This device uses the SCSI subsystem to interface with SATA devices.
Trying to use the sata command results in an unhandled exception.
This has the side effect of also causing bootflow scan to raise
an unhandled exception when it attempts to probe the SATA
subsystem. Disabling the sata command fixes this issue and does
not remove support for any boot devices.
Signed-off-by: Benjamin Schneider <ben@bens.haus>
Reviewed-by: Stefan Roese <sr@denx.de>
This file was using IS_ENABLED() to test for CONFIG flags but omitted
the CONFIG_ prefix and so did not work as expected.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Testing has shown that loading large initramfs causes data corruption
where the kernel image had been loaded to.
Debian 12 installation using a 17M initramfs boots fine, but the final
system with an initramfs of 27M obscurely fails to boot with bootz
reporting "Bad magic!".
Inspecting kernel_addr_r after this failed boot attempt does show
garbage in place of the expected zimage header.
The problem seems to occur on armada 388 only when sdhci sdma is enabled
in defconfig. Other armada boards such as turris omnia did not enable
the option.
Remove sdhci sdma from defconfig for now as a workaround.
Signed-off-by: Josua Mayer <josua@solid-run.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Enabling ODT is required to suppress reflection of the data signal on
DDR write operation. SolidRun Armada 388 SoM only connects M_ODT[0] even
when both chip-select are used.
Enable ODT[0] for both chip-select during write only.
See also commit d09f199097 ("board: solidrun: clearfog: enable ddr odt0
on write for both chip-select") where this was added to SolidRun
Clearfog board which is using the same System on Module but unlike
Helios-4 without ECC memory.
Signed-off-by: Josua Mayer <josua@solid-run.com>
J722S has hw rng, which can be used by OPTEE.
So remove option to use SW TRNG by OPTEE.
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
With the switch to using GCC 14.2.0 in commit 001bac5f16 ("Dockerfile:
Update to gcc-14.2.0 and clang-18") in CI, we should make buildman match
this.
Signed-off-by: Tom Rini <trini@konsulko.com>
Currently, phytec_get_product_name() function only takes care of PCM
SoM type, however in case of PCL, KSM or KSP SoM type it will return
error:
phytec_get_product_name: Invalid SOM type
Add support for other SoM types as defined in phytec_som_type_str enum
(see phytec_som_detection.h) to get rid of the error.
While at it, also simplify switch case statements by grouping them
together. This makes it more concise and readable.
Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
Reviewed-by: Daniel Schultz <d.schultz@phytec.de>
Add a check for CONFIG_SKIP_RELOCATE in reserve_uboot to skip the
relocation of the U-Boot image.
CONFIG_SKIP_RELOCATE skips relocation of U-Boot to the end of RAM
allowing for systems that have extremely limited RAM to run U-Boot.
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Much like what was fixed on the AM62x and AM62Px platforms[0]. The
CU_CLKOUT0 has two (25mhz and 50mhz) mux options however the clock
structure incorrectly duplicated the first 50mhz option twice. Fix this
for the AM62A platforms so the 25mhz option is selectable.
[0] https://lore.kernel.org/all/20250408161211.3165588-1-parth105105@gmail.com/
Reported-by: Parth Pancholi <parth.pancholi@toradex.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
On the AM3359 ICE we have two modes of operation CPSW mode or PRU-ICSS
mode.
For PRU-ICSS mode, connect Pin2 and Pin3 of J18 and J19 and for CPSW mode,
connect Pin1 and Pin2 of J18 and J19.
This patch adds support for PRUSS mode boot strapping from uboot.
Co-developed-by: Basharath Hussain Khaja <basharath@couthit.com>
Signed-off-by: Basharath Hussain Khaja <basharath@couthit.com>
Signed-off-by: Parvathi Pudi <parvathi@couthit.com>
A small fix for the cr50 which is a TPM but doesn't support all
the TPM functionality. Since it deviates from our normal TIS compliant
TPMs it can't be started twice since running the selftests twice hangs.
When FIT image with multiple dtbs are involved for R5 boot process,
R5 SPL starts off with the first instance of dtb to probe the
eeprom, then once we have identified the type of board, invocation
of setup_multi_dtb_fit will replace the gd->fdt_blob with the proper
board dtb match. However, when we do this, two things happen:
a) Prior to the invocation of setup_multi_dtb_fit, as part of the eeprom
discovery process, i2c controller device is already probed and marked
as exclusive with the match of the very first tisci match (from the
original boot dtb). This list is stored in the info->dev_list of the
first probe.
b) When the second dtb is loaded, tisci is probed again (since this is a
new node) and the new info->dev_list is empty.
At this stage, the exclusive devices such as i2c instances used to
probe the board information is left in the old info->dev_list that is
no longer used actively by the system using the replaced dtb.
As a result of this, the cleanup we intend to do with
ti_sci_cmd_release_exclusive_devices is no longer complete and
leaves the instances such as i2c for eeprom marked used as we scan just
the new info->dev_list.
This creates a problem when Device Manager(DM) firmware starts up later
on in the boot process and identifies that this instance of i2c is
already marked active, so it assumes this can no longer be controlled
by software and is marked internally as reserved and HLOS can no
longer control these instances. This defeated the purpose of
ti_sci_cmd_release_exclusive_devices.
NOTE: This scheme works just fine if the FIT has just a single dtb as
the info->dev_list is upto date.
To fix this, let us make ti_sci_cmd_release_exclusive_devices scan the
all registrations of tisci instances and cleanup all exclusive devices
that have ever been registered.
As part of this, change the prototype of release_exclusive_devices to
drop the handle since that has no further meaning now.
Though this issue was identified on AM64-sk, this can be present in
other builds which use multi-fit-dtb for R5 SPL startup.
Fixes: 9566b777ae ("firmware: ti_sci: Add a command for releasing all exclusive devices")
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
iomux_match_device() returns -ENOENT instead of the end index, which means
console_stop() is never called at the moment for unused consoles.
This prevents e.g. f_acm from releasing the USB gadget interface when
removing it from stdio/stderr/stdin.
Fixes: b672c1619b ("IOMUX: Split out iomux_match_device() helper")
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
The tpm_auto_start() function is used in tests and assumes that it can
open the TPM even if it is already open and a locality claimed. The cr50
driver does not use the common TPM2 TIS code so lacks a check for the
is_open field of struct tpm_chip and in fact it doesn't use that struct.
Add an equivalent check to cr50_i2c_open().
This fixes all init sequences on that TPM -- e.g 'tpm init && tpm init'
or 'tpm autostart && tpm init' used to hang
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Jerome Forissier <jerome.forissier@linaro.org> says:
This series replaces the dynamic initcalls (with function pointers) with
static calls, and gets rid of initcall_run_list(), init_sequence_f,
init_sequence_f_r and init_sequence_r. This makes the code simpler and the
binary slighlty smaller: -2281 bytes/-0.21 % with LTO enabled and -510
bytes/-0.05 % with LTO disabled (xilinx_zynqmp_kria_defconfig).
Execution time doesn't seem to change noticeably. There is no impact on
the SPL.
The inline assembly fixes, although they look unrelated, are triggered
on some platforms with LTO enabled. For example: kirkwood_defconfig.
CI: https://source.denx.de/u-boot/custodians/u-boot-net/-/pipelines/25514
Link: https://lore.kernel.org/r/20250404135038.2134570-1-jerome.forissier@linaro.org
Change board_init_f(), board_init_f_r() and board_init_r() to make
static calls instead of iterating over the init_sequence_f,
init_sequence_f_r and init_sequence_r arrays, respectively. This makes
the code a simpler (and even more so when initcall_run_list() is
later removed) and it reduces the binary size as well. Tested with
xilinx_zynqmp_kria_defconfig; bloat-o-meter results:
- With LTO
add/remove: 106/196 grow/shrink: 10/28 up/down: 31548/-33829 (-2281)
Total: Before=1070471, After=1068190, chg -0.21%
- Without LTO
add/remove: 0/54 grow/shrink: 3/0 up/down: 2322/-2832 (-510)
Total: Before=1121723, After=1121213, chg -0.05%
Execution time does not change in a noticeable way.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
The mcr and msr instructions are available in Thumb mode only if
Thumb2 is supported. Therefore, if __thumb2__ is not set, make
sure we switch to ARM mode by inserting a .arm directive in the
inline assembly.
Fixes LTO link errors with kirkwood platforms, triggered by a later
commit:
tools/buildman/buildman -o /tmp/build -eP sheevaplug
[...]
{standard input}:24085: Error: selected processor does not support `mrc p15,0,r3,c1,c0,0' in Thumb mode
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tom reports that generating the ESL file we need for authenticated
capsule updates fails to work on azure which expects a RO git tree.
Move it to $(objtree)
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
UART-A can be exposed through uSD, this was tested on Transformer T20
but should work on all Ventana-based boards.
TX is exported on SDD pingroup corresponding to uSD CLK pin
RX is exported on SDB which is CMD pin in uSD slot
Signed-off-by: Artur Kowalski <arturkow2000@gmail.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The Tegra Note 7 is a mini tablet computer and the second Tegra 4
based mobile device designed by Nvidia that runs the Android operating
system. The Tegra Note has a 7" IPS display with 1280 x 800 (217 ppi)
resolution. The 1 GB of RAM and 16 GB of internal memory can be
supplemented with a microSDXC card giving up to 64 GB of additional
storage.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The ASUS Transformer Pad TF701T is an Android tablet computer made by
ASUS, successor to the ASUS Transformer Pad Infinity. The tablet includes
a Tegra 4 T114 processor clocked at 1.9 GHz, and an upgraded 2560×1600
pixel resolution screen, increasing the pixel density to 300 PPI and
a mobile dock. Transformers (t114) board derives from Nvidia Macallan
development board.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The clock initialization routine sets the DISP* clock parent to PLLC,
resulting in DC failure in the case when PLLD was previously configured.
This issue disrupts chainloading and to prevent failures caused by DISP*
clock parent conflicts, clock initialization should not modify DISP*. The
DC driver handles DISP* configuration.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Most device headers contain SoC specific part and common Tegra post part.
Add a generic header which can be used by any Tegra device of one of the
supported SoC generations (T20, T30, T114, T124 or T210) without need in
device specific configuration.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Link CFG_SYS_NS16550_COM1 value to chosen CONFIG_TEGRA_ENABLE_UART Tegra
wide. Remove all CFG_SYS_NS16550_COM1 from device headers.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Applies same logic to general Tegra pincontrol driver as is done to Tegra20
by commit:
a35bf832d7 ("pinctrl: tegra20: detect unknown/invalid pin/func
configurations")
Suggested-by: Artur Kowalski <arturkow2000@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Tegra20 driver doesn't know about some pin configurations and even about
some pins. In case when pin configuration is unknown the pin would be
muxed to whatever is under function 0, in case when pin itself is
unknown, it could cause out-of-bounds array access in pinmux_set_func
and pinmux_set_pullupdown.
Signed-off-by: Artur Kowalski <arturkow2000@gmail.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The Motorola Atrix 4G (MB860) and Droid X2 (MB870) both featured a
dual-core NVIDIA Tegra 2 AP20H processor clocked at 1GHz, coupled with 1GB
of DDR2 RAM. Storage consisted of 16GB of internal flash memory, expandable
via microSD. The display was a 4.0-inch TFT LCD with a resolution of
960x540 pixels (qHD). The devices originally ran on Android up to 2.3
(Gingerbread).
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The LM3532 is a 500-kHz fixed frequency asynchronous boost converter which
provides the power for 3 high-voltage, low-side current sinks. The device
is programmable over an I2C-compatible interface and has independent
current control for all three channels.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Add support for the LCD panel module used in Motorola Atrix 4G or Droid X2.
Exact panel vendor and model are unknown. The panel has a 540x960 (qHD)
resolution and uses 24 bit RGB per pixel.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
CPCAP has a dedicated interrupt for power button. Implement this to have
more input control over the devices.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The CPCAP is a Motorola/ST-Ericsson creation, a multifunctional IC whose
main purpose was power control. It was used in a wide variety of Motorola
products, both Tegra and OMAP based. The most notable devices using this
PMIC are the Motorola Droid 4, Atrix 4G, and Droid X2.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Place Tegra124 SOR and eDP implenetation into common Tegra driver folder
until it is integrated into existing setup.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Since this set of drivers suports four Tegra SoC generations, lets name it
just 'tegra'.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
GPIO reset and power-off functionality depends on device tree data, which
is often absent in SPL or TPL. To address this, incorporate PHASE_ into the
config option and add Kconfig option or each phase.
Adjust SYSRESET_GPIO and POWEROFF_GPIO uses to address possible
regressions.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Historically, PLLD2 mirrored PLLD's layout on Tegra30 and 114. However,
with the introduction of Tegra124, this changed. This layout alteration was
not considered, and it now requires a corrective action to prevent future
complications.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
PLLD and PLLD2 clocks possess a unique enable bit within their
miscellaneous register. Take this into account when using clock_set_rate
function.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Add missing configuration of chip select polarity. Default polarity is LOW,
which satisfies most cases but some devices require HIGH polarity and will
not work.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Lucien.JhengandTom Rini
Benjamin SchneiderandStefan Roese
Chris PackhamandStefan Roese
Josua MayerandStefan Roese
Casey ConnollyandTom Rini
yan wangandTom Rini
Udit KumarandTom Rini
Primoz FiserandTom Rini
Jesse TaubeandTom Rini
Bryan BrattlofandTom Rini
Parvathi PudiandTom Rini
Nishanth MenonandTom Rini
Stephan GerholdandTom Rini
Simon GlassandIlias Apalodimas
Jerome ForissierandTom Rini
Artur KowalskiandSvyatoslav Ryhel