The PBUF_POOL_BUFSIZE ends up being only 592 bytes, instead of 1514,
when PROT_TCP_LWIP Kconfig option is disabled. This results in a full
Ethernet frame requiring three PBUFs instead of just one.
This happens because the PBUF_POOL_BUFSIZE constant depends on the value
of a TCP_MSS constant, something that defaults to 536 when PROT_TCP_LWIP
is disabled.
PBUF_POOL_BUFSIZE = LWIP_MEM_ALIGN_SIZE(TCP_MSS + 40 + PBUF_LINK_HLEN)
Ensure that a full Ethernet frame fits inside a single PBUF by moving
the define of TCP_MSS outside the PROT_TCP_LWIP ifdef block.
Fixes: 1c41a7afaa ("net: lwip: build lwIP")
Acked-by: Jerome Forissier <jerome.forissier@arm.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
For enabling the clock driver we use symbol CONFIG_CLK.
Select this symbol for the HiSilicon Fast Ethernet Controller driver.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
If we are using the legacy or the LWIP network stack,
should not influence our decision to provide command `mii`.
Let BOOT_DEFAULTS_CMDS imply MII if either of the network
stacks is available.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Current code just bind mt7531 mdio with it's driver, so mdio device may
not be probed and hense not usable.
This patch:
* Forces probing of mt7531 mdio for GDM1 port
* Renames the mt7531 mdio bus interface to 'mt7531-mdio'. We may have
multiple available MDIO, so the name 'mdio' isn't descriptive enough.
* Sets mdio bus for the GDM port device
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
It's not possible to disable PCS support just now, an7581 u-boot will not
compile. This patch fixes an issue.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Add required changes to call PCS function to configure the Serdes Port.
The Ethernet driver is adapted following Upstream Kernel node structure.
Function calling order is the same of Phylink upstream kernel.
With the PCS support, also add support for attaching PHY. With
"in-band-status" set in DT for the managed property, a rudimental
support for SFP module is present.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
pcs-airoha-common.o should not build unconditionally,
also make building rules looks better.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Add support for Airoha PCS driver present on AN7581 SoC.
This is needed to configure the Serdes port for the different PHY mode.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Call airoha_switch_init() before creating GDM instances, so if
allocation of GDM port fails, early created GDM instances will work
normally.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
We should not call airoha_fe_init() from GDM port independent code,
because it do a GDM specific things.
Makes airoha_fe_maccr_init() and airoha_fe_init() port dependent
and call them from airoha_eth_port_probe()
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Declare airoha_eth_port as U_BOOT_DRIVER(), fix airoha_alloc_gdm_port()
to lookup a driver instead of direct airoha_eth_port usage.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
In the case of an7581 possible GDM port id are: 1, 2 and 4.
Initialization of port GDM4 will lead to out of boundary writing
to gdm_port_str[] array.
Let's increase the array size by 1 to avoid it.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Rework the driver to support multiple GDM port. The driver is split to
main driver as a MISC driver with forced probe (by using the
DM_FLAG_PROBE_AFTER_BIND) and each GDM port register a ETH driver.
This permit a 1:1 implementation with the linux kernel driver and permit
to use the same exact DT nodes.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Instead of having duplicate priv struct for mdio-mt7531-mmio driver in
both driver and header, use the one exposed by the header directly.
This make sure we have consistent priv struct if the driver will be
updated in the future.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The hashed-nodes property in a FIT signature node lists which FDT paths
are included in the signature hash. It is intended as a hint so should
not be used for verification.
Add a function to build the node list from scratch by iterating the
configuration's image references. Skip properties known not to be image
references. For each image, collect the path plus all hash and cipher
subnodes.
Use the new function in fit_config_check_sig() instead of reading
'hashed-nodes'.
Update the test_vboot kernel@ test case: fit_check_sign now catches the
attack at signature-verification time (the @-suffixed node is hashed
instead of the real one, causing a mismatch) rather than at
fit_check_format() time.
Update the docs to cover this. The FIT spec can be updated separately.
Signed-off-by: Simon Glass <simon.glass@canonical.com>
Closes: https://lore.kernel.org/u-boot/20260302220937.3682128-1-trini@konsulko.com/
Reported-by: Apple Security Engineering and Architecture (SEAR)
Tested-by: Tom Rini <trini@konsulko.com>
The PCIe0 instance of PCIe on the J722S SoC uses the 4 GB Address Window
starting from 0x6_0000_0000 to map System Addresses to PCIe Bus Addresses.
Hence, enable CONFIG_SYS_PCI_64BIT.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Fixes: 79f3e77133 ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")
The PCIe1 instance of PCIe on the J7200 SoC uses the 4 GB Address Window
starting from 0x41_0000_0000 to map System Addresses to PCIe Bus Addresses.
Hence, enable CONFIG_SYS_PCI_64BIT.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Fixes: 79f3e77133 ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")
The PCIe0 instance of PCIe on the AM64x SoC uses the 4 GB Address Window
starting from 0x6_0000_0000 to map System Addresses to PCIe Bus Addresses.
Hence, enable CONFIG_SYS_PCI_64BIT.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Fixes: 79f3e77133 ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")
The PCIe Controllers on the J784S4 and AM69 SoCs support Root-Complex
mode of operation. PCIe0 instance of PCIe on both of the SoCs is brought
out on the Starter-Kit (AM69) and EVM (J784S4) boards. Hence, enable
the configs required for Root-Complex mode of operation.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Fixes: 79f3e77133 ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")
The PCIe Controllers on the J784S4 SoC support Root-Complex mode of
operation. Hence, enable it.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Fixes: 79f3e77133 ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")
The PCIe Controllers in the K3 SoCs have 4 GB Address Windows in the
64-bit address space to map System (CPU) Addresses to PCIe Bus Addresses.
The physical addresses for these Address Windows across PCIe instances
across SoCs is as follows:
+--------+----------------+----------------+----------------+----------------+
| SoC | PCIe0 | PCIe1 | PCIe2 | PCIe3 |
+--------+----------------+----------------+----------------+----------------+
| AM64 | 0x6_0000_0000 | NA | NA | NA |
| J722S | 0x6_0000_0000 | NA | NA | NA |
| AM68 | NA | 0x41_0000_0000 | NA | NA |
| J7200 | NA | 0x41_0000_0000 | NA | NA |
| J721S2 | NA | 0x41_0000_0000 | NA | NA |
| J742S2 | 0x40_0000_0000 | 0x41_0000_0000 | NA | NA |
| AM69 | 0x40_0000_0000 | 0x41_0000_0000 | 0x42_0000_0000 | 0x43_0000_0000 |
| J721E | 0x40_0000_0000 | 0x41_0000_0000 | 0x42_0000_0000 | 0x43_0000_0000 |
| J784S4 | 0x40_0000_0000 | 0x41_0000_0000 | 0x42_0000_0000 | 0x43_0000_0000 |
+--------+----------------+----------------+----------------+----------------+
Two regions for a 1:1 mapping from virtual addresses to physical addresses
catering to all of the above will be required, which are:
1. For AM64 and J722S SoCs
=> Start: 0x6_0000_0000 Size: 0x1_0000_0000
2. For AM68, AM69, J7200, J721E, J721S2, J742S2 and J784S4 SoCs
=> Start: 0x40_0000_0000 Size: 0x4_0000_0000
Since the 'Flash Peripherals' region from 0x5_0000_0000 to 0x8_7FFF_FFFF
includes the mapping for AM64 and J722S SoCs, only the second region
mentioned above needs to be added.
Hence, add the region to support 64-bit address space for PCIe.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Fixes: 79f3e77133 ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")
Drivers should extract device-tree data before probing via the
.of_to_plat hook.
Implement it for stm32_dsi driver. By doing so, it also solve a
variable shadowing in stm32_dsi_probe() where &clk was used as
peripheral clock and ref clock.
For readability some struct have been renamed such as:
* struct stm32_dsi_priv *dsi -> struct stm32_dsi_priv *priv
* struct clk clk -> struct clk pclk
Signed-off-by: Raphael Gallais-Pou <rgallaispou@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Philip Molloy <philip@philipmolloy.com> says:
This series updates the maintainers for the ADI ADSP platform. It
follows Greg's series adding support for ADI ADSP SoCs.
Timesys spent years developing and maintaining Linux support for ADI
ADSP SoCs. The maintenance contract has ended and ADI has brought that
effort in-house. Additionally, Timesys was acquired by another company.
Thanks to everyone at Timesys for all of their hard work over the years!
Link: https://lore.kernel.org/r/20260226111136.354009-1-philip@philipmolloy.com
After years of developing the ADI ADSP platform, Timesys was purchased
by another company and is no longer contracted to maintain the platform.
Signed-off-by: Philip Molloy <philip.molloy@analog.com>
Reviewed-by: Greg Malysa <malysagreg@gmail.com>
After years of developing the ADI ADSP platform, Timesys was purchased
by another company and is no longer contracted to maintain the platform.
Utsav is leaving ADI after contributing to ADSP SoCs for the last 3
years. He is a founding member of the in-house team supporting the
chips.
Linux support at ADI has been consolidated. Use the company-wide mailing
list and git repository.
Signed-off-by: Philip Molloy <philip.molloy@analog.com>
Reviewed-by: Greg Malysa <malysagreg@gmail.com>
More strict checks in GCC 15 expose a new warning:
tools/atmelimage.c: In function ‘atmel_find_pmecc_parameter_in_token’:
tools/atmelimage.c:64:31: error: assignment discards ‘const’ qualifier from pointer target type [-Werror=discarded-qualifiers]
64 | param = strstr(token, "=");
| ^
cc1: all warnings being treated as errors
Add 'const' qualifier to variable 'param' to prevent build failing
due to -Werror.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
A few fixes/missing changes for UFS:
- remove unused ufs_post_bind() declaration
- Disable UTP command timeout in slow mode
- Missing MediaTek UFS PHY Driver to be used with the UFS driver
Remove the "phandle = <0x..>;" properties from the DT diff between
unpatched base DT and U-Boot augmented DT if DEVICE_TREE_DEBUG=1.
The phandle numbers are only generated by DTC, but not referenced
anywhere in the DT, because the original references are specifically
not replaced by phandle numbers when recent DTC is invoked with the
-I dts -O dts flags . The phandle number are therefore only a noise
in the diff, filter them out.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tested-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
The exported sub_make_done variable leaks into the environment of all
child processes. When make targets like tcheck spawn independent make
invocations with O=, those child makes inherit sub_make_done=1, skip
the KBUILD_OUTPUT setup and try to build in the source tree.
There is a workaround that resets sub_make_done to 0 for specific test
targets, but this isn't great since it has tolist every target that
spawns independent make invocations.
Instead, unexport sub_make_done once we are in the final make
invocation. The direct sub-make already has the value in its
environment from the export, and no further propagation is needed.
This also allows the per-target workaround to be removed.
Fixes: 27529f1cb0 ("kbuild: skip parsing pre sub-make code for recursion")
Signed-off-by: Simon Glass <simon.glass@canonical.com>
The bootmenu_conv_key() function is shared with expo subsystem for key
input. Adding alphanumeric-to-BKEY_SHORTCUT conversion there causes expo
to swallow typed characters instead of inserting them as text, since
BKEY_SHORTCUT falls in the range that expo treats as a command key
rather than passing through.
Move the shortcut-key detection into bootmenu_loop() where it is
only used in the bootmenu context.
Fixes: 8c986521c3 ("cmd: bootmenu: permit to select bootmenu entry with a shortcut")
Signed-off-by: Simon Glass <simon.glass@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The ofnode_to_fdt() function may return a NULL pointer in multiple cases.
Or, this function's return value is often passed directly to functions such
as fdt_getprop() which end up dereferencing it, thus causing a NULL pointer
exception.
Don't allow ofnode_to_fdt() to return NULL, to avoid a NULL pointer
dereference.
Reviewed-by: Raphaël Gallais-Pou <raphael.gallais-pou@foss.st.com>
Signed-off-by: Romain Gantois <romain.gantois@bootlin.com>
Reviewed-by: Simon Glass <simon.glass@canonical.com>
The get_ram_size() function fails to restore the original RAM data when
the data cache is enabled. This issue was observed on an AM625 R5 SPL
with 512MB of RAM and is a regression that became visible with
commit bc07851897 ("board: ti: Pull redundant DDR functions to a common
location and Fixup DDR size when ECC is enabled").
Observed boot failure messages:
Warning: Did not detect image signing certificate. Skipping authentication to prevent boot failure. This will fail on Security Enforcing(HS-SE) devices
Authentication passed
Starting ATF on ARM64 core...
The system then hangs. This indicates that without a data cache flush,
data in the cache is not coherent with RAM, preventing the system from
booting. This was verified by printing the content of this address when
the issue occurs.
Add a data cache flush after each restore operation to resolve this
issue.
Fixes: bc07851897 ("board: ti: Pull redundant DDR functions to a common location and Fixup DDR size when ECC is enabled")
Fixes: 1c64b98c1e ("common/memsize.c: Fix get_ram_size() when cache is enabled")
Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
Reviewed-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Tested-by: Francesco Dolcini <francesco.dolcini@toradex.com> # Toradex Verdin AM62
Commit 067c1b0332 ("ufs: Call ufs_scsi_bind() from uclass .post_bind")
inlined ufs_scsi_bind() into ufs_post_bind() as trivial
device_bind_driver() call.
ufs_scsi_bind() is no longer referenced anywhere in the codebase, so
drop its declaration from include/ufs.h.
Drivers used to include <ufs.h> to include prototype of ufs_scsi_bind()
function, so we can now safely remove such includes.
Fixes: 067c1b0332 ("ufs: Call ufs_scsi_bind() from uclass .post_bind")
Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260203-cleanup-ufs-header-v1-1-4c10424485f0@baylibre.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Add a test calling the LoadImage() UEFI function with both its SourceBuffer
and DevicePath input arguments equal to NULL.
This test can be run on the sandbox with the following command:
./u-boot -T -c "setenv efi_selftest load image from file; \
bootefi selftest"
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
With the change to regularize the usage of TEST_PY_TEST_SPEC in the
sjg-lab stanza with commit c7f360f20d ("Gitlab: Rework sjg-lab calling
test.py to be closer to test.py stage") the leading "and " part of the
usage under qemu-x86_64 wasn't removed when it should have been. Do so
now.
Fixes: c7f360f20d ("Gitlab: Rework sjg-lab calling test.py to be closer to test.py stage")
Reviewed-by: Simon Glass <simon.glass@canonical.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
