Change optee probe function to only warn when service enumeration
sequence fails instead of reporting an optee driver probe failure.
Indeed U-Boot can still use OP-TEE even if some OP-TEE services are
not discovered.
Fixes: 94ccfb78a4 ("drivers: tee: optee: discover OP-TEE services")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
DSP core is going into abnormal state when load callback is called
after starting of DSP core.
Reload of firmware needs core to be stopped first, followed by
load.
So avoid loading of firmware, when core is started.
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
The AEM and Juno FVPs (Fixed Virtual Platforms) support a VirtIO
disc interface. Adding VIRTIO to the list of boot devices allows
these FastModel platforms to boot from 'disc' in the same way
the hardware counterpart can boot from SATA or USB.
This is a NOP if CONFIG_CMD_VIRTIO is not enabled, so no impact
on Juno hardware (which is built with vexpress_aemv8a_juno_defconfig)
Signed-off-by: Robert Catherall <robert.catherall@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Migrate to the new environment format and drop most of the config.h.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add timer driver in Starfive SoC. It is an timer that outside
of CPU core and inside Starfive SoC.
Signed-off-by: Kuan Lim Lee <kuanlim.lee@starfivetech.com>
Signed-off-by: Wei Liang Lim <weiliang.lim@starfivetech.com>
Changes for v2:
- correct driver name, comment, variable
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
It is hardware compatible with classic MicroBlaze processor.
The patch contains initial wiring and configuration for initial HW design
with memory, cpu, interrupt controller, timers and uartlite console
(interrupt controller is listed but U-Boot is not using it).
Provided DT is just describing one configuration and should be taken only
as example.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Add gpio-restart node to do reset.
Before applied this patch, System Reset Extension doesn't appear with
sbi command.
OpenSBI 1.3
Machine:
Vendor ID 489
Architecture ID 8000000000000007
Implementation ID 4210427
Extensions:
sbi_set_timer
sbi_console_putchar
...[snip]...
IPI Extension
RFENCE Extension
Hart State Management Extension
Performance Monitoring Unit Extension
After applied this patch, System Reset Extension is supported from SBI.
OpenSBI 1.3
Machine:
Vendor ID 489
Architecture ID 8000000000000007
Implementation ID 4210427
Extensions:
sbi_set_timer
sbi_console_putchar
...[snip]...
IPI Extension
RFENCE Extension
Hart State Management Extension
System Reset Extension
Performance Monitoring Unit Extension
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Pull request for efi-next-20231217
Documentation:
* replace MD5 and SHA1 by SHA256 in examples
UEFI:
* Refactor boot manager and bootefi command to let the EFI boot method work
without shell.
Both SHA1 and (especially) MD5 are no longer as safe as they once were for
cryptographic use. Replaces examples which use them with examples using
SHA256 instead. This will provide more-secure defaults for users who use
documentation examples as a base for their own use. This is not too
necessary for non-verified-boot scenarios (since someone could just replace
the checksum), but I wanted to be complete.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Now that efi_loader subsystem provides interfaces that are equivalent
with bootefi command, we can replace command invocations with APIs.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Now it is clear that the command actually depends on interfaces,
not "bootefi bootmgr" command.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
In the prior commits, interfaces for executing EFI binary and boot manager
were carved out. Move them under efi_loader directory so that they can
be called from other places without depending on bootefi command.
Only efi_selftest-related code will be left in bootefi.c.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Device paths allocated in bootefi_test_prepare() will be immediately
consumed by do_efi_selftest() and there is no need to keep them for later
use. Introduce test-specific varialbles to make it easier to move other
bootmgr functions into library directory in the next commit.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Carve binary execution code out of do_bootefi_image() in order to move
binary-execution specific code into library directory in the later
commit.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Carve EFI boot manager related code out of do_bootefi_image() in order
to move boot manager specific code into library directory in the later
commit.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Replicate some code and re-organize do_bootefi() into three cases, which
will be carved out as independent functions in the next two commits.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Unfold do_bootefi_image() into do_bootefi() in order to make it easier
to re-organize do_bootefi() in the next commit.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
After talking with the author off-list I was reminded that this part of
the series was not supposed to be merged, only parts 1-3 upon further
review.
This reverts commit 58a277c207.
Signed-off-by: Tom Rini <trini@konsulko.com>
clock patches for u-boot/next
The main thing in here is Igor's conversion of soc_clk_dump to a clk_ops
member. There's also a write-protect feature for nuvoton clocks.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
clock changes for u-boot/master
This has some clock fixes which should go in before the release. It's a bit
late in the cycle, but most of these have tests to go along with them.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
The base address of extended DDR does not change across the K3 family.
Setting this per SoC is not needed. Remove this definition to help
remove the last bits from K3 include/configs/*.h files.
Signed-off-by: Andrew Davis <afd@ti.com>
Updates as a result of TIFS core now reserving a virtual interrupt
for enabling interrupts between DM to TIFS core. Because of this
change other virtual interrupt counts decrease by one.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Share the MCU GPIO interrupts between A53 core and DM R5 core. Allocating
2 instances each to A53 and DM R5.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Update am62ax rm-cfg with allocation entries for C7x core. Following
updates are added for C7x:
- Share split BCDMA tx and rx channels between DM R5 and C7x
- Share rings for split BCDMA tx and rx channels between DM R5 and C7x
- Add Global events and Virtual interrupts for C7x
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
The Device vs Normal memory map is the same for all K3 SoCs. Merge
the SoC specific maps into one.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
All normal memory areas should be mapped as such.
We added these un-cached holes in our memory map to hack around the
remoteproc driver missing the proper cache maintenance operations.
The problem is having these non-cached memory map areas causes stability
issues later in system operation due to the nature of the K3 coherency
architecture. Plus these are board specific carveouts and instead
should have been added at the board level, not here in the SoC common
code area.
Remove these non-cached memory map areas.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
ATF and OPTEE regions may be firewalled from non-secure entities. To
prevent access to this area we leave a hole there in the MMU map. This
is the same idea as [0] but we complete that patch by adding the same
for AM65, J721e, J7200, and J721s2 here.
[0] commit 0688ff3ae2 ("arm: mach-k3: arm64-mmu: do not map ATF and OPTEE regions in A53 MMU")
Signed-off-by: Andrew Davis <afd@ti.com>
NR_MMU_REGIONS is a copy/paste from another platform that extends
this list later. We do not do that, so let the list be the size
of the initializer list.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
This file is common for all K3, move it out of board/ directory and
into mach-k3. As we need to change the path in k3-binman.dtsi let's
take this opportunity to switch to absolute paths which makes adding
non-TI boards (like Toradex Verdin) not need to override these paths.
Signed-off-by: Andrew Davis <afd@ti.com>
It's possible for composite clocks to have a divider that does not
implement set_rate() operation. For example, sandbox_clk_composite()
registers composite clock with a divider that only has get_rate().
Currently clk_composite_set_rate() only checks thate rate_ops are
present, so for sandbox it will cause NULL dereference during
clk_set_rate().
This patch adds rate_ops->set_rate check tp clk_composite_set_rate().
Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231205232334.2931-2-ivprusov@salutedevices.com
