When applying the patch that became commit a2d881f5bcd3 ("doc: memory:
Add documentation for system RAM") one of the diagrams was missed.
Re-add this missing file.
Reported-by: Adriano Carvalho <adrianocarvalho.pt@gmail.com>
Fixes: a2d881f5bcd3 doc: memory: Add documentation for system RAM
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
[trini: Take Neha's original svg and re-apply it]
Signed-off-by: Tom Rini <trini@konsulko.com>
Initialize mtd->writesize in nand_init() as otherwise
nand_page_size() returns 0 and this affects NAND read
operations.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
- Update MMC entry to match 'mmc' using 'N'
- Add myself as POWER maintainer for regulator and pmic patches. I have
started to handle relevant patches.
- Update QORIQ maintainer. Priyanka has moved to work on other stuff, I
have been handling this for quite some time.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add myself as a maintainer of the NETWORK subsystem since:
- I have effectively been handling net patches in my patchwork queue and
sending pull requests to Tom,
- I do have push access to the u-boot-net custodian tree.
Also, add u-boot-net as the SCM tree for NETWORK (LWIP) since it is where
lwIP-related patches end up too.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
CC: Ramon Fried <rfried.dev@gmail.com>
CC: Joe Hershberger <joe.hershberger@ni.com>
CC: Tom Rini <trini@konsulko.com>
R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 page 585
Figure 9.3.2 Software Reset flow (B) indicates that for peripherals in HSC
domain, after reset has been asserted by writing a matching reset bit into
register SRCR, it is mandatory to wait 1ms.
Because it is the controller driver which can determine whether or not the
controller is in HSC domain based on its compatible string, add the missing
delay into the controller driver.
This 1ms delay is documented on R-Car V4H and V4M, it is currently unclear
whether S4 is affected as well. This patch does apply the extra delay on
R-Car S4 as well.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Assure the reset is latched and the core is ready for DBI access.
On R-Car V4H, the PCIe reset is asynchronized and does not take
effect immediately, but needs a short time to complete. In case
DBI access happens in that short time, that access generates an
SError. Make sure that condition can never happen, read back the
state of the reset which should turn the asynchronized reset into
synchronized one, and wait a little over 1ms to add additional
safety margin.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 page 4581
Figure 104.3b Initial Setting of PCIEC(example), third quarter of the figure
indicates that register 0xf8 should be polled until bit 18 becomes set to 1.
Register 0xf8 bit 18 is 0 immediately after write to PCIERSTCTRL1 and is set
to 1 in less than 1 ms afterward. The current readl_poll_timeout() break
condition is inverted and returns when register 0xf8 bit 18 is set to 0,
which in most cases means immediately. In case CONFIG_DEBUG_LOCK_ALLOC=y ,
the timing changes just enough for the first readl_poll_timeout() poll to
already read register 0xf8 bit 18 as 1 and afterward never read register
0xf8 bit 18 as 0, which leads to timeout and failure to start the PCIe
controller.
Fix this by inverting the poll condition to match the reference manual
initialization sequence.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
On the RZG2L platform, the advised
TF-A (https://github.com/renesas-rz/rzg_trusted-firmware-a/tree/v2.5/rzg2l)
does not pass any DTB blob to U-Boot.
On the other hand, the RZG2L part of U-Boot expects a DTB to be passed. It
means that if one flashes the latest TF-A as well as the mainline U-Boot,
it will crash trying to dereference the NULL DTB pointer before outputing
anything.
Check if the DTB pointer is NULL before trying to use it.
Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The error message in phytec_get_product_name() was missing a newline,
causing log output to be concatenated with subsequent messages. Add
the newline to improve readability.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
After switching our boards to standard boot, we observed that the
kernel hangs when booting with the "script" boot method over the
network.
The original scriptaddr value was copied from ti_common.env and
remained unused for some time. On phycore-am62x and phycore-am62ax,
however, this address conflicts with the current location where
ATF is loaded (CONFIG_K3_ATF_LOAD_ADDR).
Move scriptaddr to 0x89100000, directly after fdtoverlay_addr_r.
The phycore-am64x is not affected by this issue, but we update it
as well to keep all phycore-am6xx boards consistent.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Anshul Dalal <anshuld@ti.com>
Per a private email, drop Luka Perkov from MAINTAINERS entries.
Reviewed-by: Tony Dinh <mibodhi@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Fix support for i.MX93 voltage modes on phyCORE-i.MX93 SoM boards.
First of all, Kconfig option CONFIG_IMX9_LOW_DRIVE_MODE is gone since
commit c9efcad237 ("imx93_evk: Remove CONFIG_IMX9_LOW_DRIVE_MODE and
ld defconfig") and was replaced by runtime detection mechanism. Thus
lets use is_voltage_mode() instead of Kconfig to detect CPU type and
select proper voltage mode.
Secondly, 1400MHz ND mode (Nominal Drive) requiring 0.85V BUCK voltage
was not supported with current power_init_board() PMIC settings. Add
check also for this CPU type and set BUCK voltage accordingly.
Last but not least, add printf() printouts about PMIC voltage mode to
the console. This makes it more apparent and verbose about voltage mode
in use. Also our internal tests depend on this printout to catch issues
with i.MX93 CPU types and set PMIC voltage modes.
Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
The LPCG number on iMX93 and iMX91 is 127 not 122. The wrong
value is used in ccm_reg structure and Coverity reports several
issues as out-of-bounds write.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
According to latest ELE Get FW version API, the FW version word is defined
as below. The patch version only has 4 bits and minor version has 12 bits.
However, the codes use 8 bits for patch version and minor version. Add the
patch to fix the issue.
ELE firmware version
[31] - When set indicates a dirty build.
[30] - Reserved
[29:28] - Hotfix version.
[27] - When set, indicate that ELE FW is authenticated and operational.
[26:25] - Reserved
[24] - When set, indicate that an alternative FW is running.
[23:16] - Indicate the major version. This byte is checked against the
version set in the fuses to determine if the FW execution can be authorized
[15:4] - Indicate the minor version.
[3:0] - Indicate the patch version.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The ELE MU driver needs to be probed at init_r phase as well because
some ELE APIs will be called.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The config "GIC_V3" seems to be typo, and currently "GICV3" remains
disabled. This should be removed until needed.
Fixes: 5cd4a355e0 ("board: synquacer: Add DeveloperBox 96boards EE support")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
The isprint() checks printability across all 256 characters, some of the
upper 128 characters are printable and produce artifacts on UART. Call
isascii() first to only consider the bottom 7bit ASCII characters as
printable, and then check their printability using isprint(). This fixes
a rare misprint in case the ID page content is uninitialized or corrupted.
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
The eip pointer in dh_get_value_from_eeprom_buffer() might be NULL.
The current NULL pointer check happens too late, after the eip was
accessed in variable assignment. Reorder the two, so the NULL pointer
check happens first, and any access second, otherwise the access may
trigger a hang or other undefined behavior.
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Add the HBMC and MUX_MMIO configs in the R5 SPL stage for
successful HBMC boot.
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
MUX_MMIO is needed by HBMC in SPL stage. Enable it at SPL as well
as u-boot proper stage.
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
The commit 210702ae6c ("spl: spi: fix falcon mode for spi boot") fixed
the logic of spl_start_uboot() where 0 means OS boot and 1 means u-boot.
Zynq/ZynqMP enable OS_BOOT by default but it was never really be used
that's why disable it to boot via U-Boot phase all the time.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Commit 649f4a7d3c ("board: ti: am57xx: Set fdtfile from C code
instead of findfdt script") prepends "ti/omap/" to the actual name
of the fdtfile whereas fit image boot needs exact dtb name. So, remove
"ti/omap" from name_fit_config by substituting it with an empty string.
Fixes: 649f4a7d3c ("board: ti: am57xx: Set fdtfile from C code instead of findfdt script")
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
This patch is used to restore support for i.MX95 A0 silicon. To avoid
duplicating defconfig, imx95.config is added and can be shared between
imx95_a0_19x19_evk_defconfig and imx95_19x19_evk_defconfig.
container.cfg and imximage.cfg are used to created .cfgout files that
are be passed to mkimage with -n to build flash.bin. Now they have been
deleted and replaced by adding their content to properties of node which
type is nxp-imx9image under binman node.
Fixes: 9936724aa9 ("imx95_evk: Add i.MX95 B0 support")
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Tested-By: Tim Harvey <tharvey@gateworks.com> # imx95-19x19-evk (rA0)
To support passing specific commands defined in enum imx8image_cmd to
the imx8image_copy_image() function, this patch introduces a new entry
type nxp-imx9image. This entry generates a plain text data file
containing the relevant commands, enabling flexible configuration during
image creation.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Check the compatible string of ethernet1 node for KS8851 very early on,
before calling uclass_get_device_by_of_path() which might initialize
the device and possibly attempt to configure MAC address into device
which is not KS8851. Doing the compatibility check early prevent this.
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
The layout of SYSCFG_ETHnCR on STM32MP25xx is slightly different yet again.
Add missing swizzling to program the correct register with the correct content.
Fixes: 20afca89ed ("net: dwc_eth_qos: add support of stm32mp2 platform")
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Christophe ROULLIER<christophe.roullier@foss.st.com>
The clk_register_composite() does clk_resolve_parent_clk() look up,
which requires valid udevice pointer. Do not pass NULL, pass a valid
device pointer to prevent hang on registering ck_usbo_48m clock on
STM32MP13xx.
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
SPL recover data section is broken which causes reboot failure on
some i.MX platforms (iMX8QM/iMX95).
The global variable cold_reboot_flag is assigned to weak reset_flag
function which always return 1, so restore never been executed in
warm reboot.
Fixes: 1c37e59bfb ("arm: armv8: Improve SPL data save and restore implementation")
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
spl_start_uboot is a board overridable function that switches to falcon
boot mode on return value of 0.
Though for SPI, the falcon boot mode was being enabled on return value
of 1 which is not the correct behaviour. Therefore this patch fixes it
to the expected boot flow.
Fixes: 14509a28aa ("spl: spi: Consolidate spi_load_image_os into spl_spi_load_image")
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Anshul Dalal <anshuld@ti.com> says:
On various TI's K3 platforms boot failure was observed on SPI NOR since the
commit 5609f200d0 ("arm: Kconfig: enable LTO for ARCH_K3"). This issue was
root caused to stack corruption by the 'udma_transfer' function. Where the local
variable 'paddr' of type 'dma_addr_t' was being written to as a 64-bit value
which overwrote the stack frame of the caller (dma_memcpy) as only 32-bits had
been reserved for paddr on the stack, specifically the r4 register in the frame
of dma_memcpy was being overwritten with a 0.
drivers/dma/ti/k3-udma.c:2192:
int udma_transfer(...)
{
...
dma_addr_t paddr = 0;
...
/* paddr was written to as 64-bit value here */
udma_poll_completion(uc, &paddr);
}
drivers/dma/dma-uclass.c:234:
int dma_memcpy(...)
{
dma_addr_t destination;
dma_addr_t source;
int ret;
...
/* This call resolves to udma_transfer */
ret = ops->transfer(...);
...
dma_unmap_single(destination, ...);
dma_unmap_single(...);
return ret;
}
Enabling LTO changed how gcc mapped local variables of dma_memcpy to CPU
registers, where earlier the bug was hidden since the overwritten register
'r4' was allotted to 'ret' but was allotted to 'destination' once LTO was
enabled. And since the overwritten value was 0, the bug remained undetected
as it just meant ret was 0, but having 'destination' set to 0 caused
dma_unmap_single to fail silently leading to boot failures.
The fix entails enabling DMA_ADDR_T_64BIT which changes dma_addr_t from u32 to
u64 for the R5 SPL thus reserving enough space for 'paddr' to prevent the
overflow.
Link: https://lore.kernel.org/r/20250903115207.572304-1-anshuld@ti.com
ARCH_K3 encompasses both 32 and 64-bit cores on the same SoC, though the
DMA addresses are always 64-bit in size.
With the current implementation, the R5 SPL uses a u32 for dma_addr_t
which leads to data overflow when functions such as k3_nav_*_pop_mem try
to write a 64-bit address to dma_addr_t variable.
In certain cases it leads to stack corruption which manifest as boot
failures on certain compilers, such as SPI boot on GCC 14.2 or 13.3.
Therefore this patch selects CONFIG_DMA_ADDR_T_64BIT for all ARCH_K3.
Fixes: ffcc66e8fe ("dma: ti: add driver to K3 UDMA")
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Reviewed-by: Prasanth Babu Mantena <p-mantena@ti.com>
dma_addr_t is used to store any valid DMA address which might not
necessarily be the same size as host architecture's word size. Though
various typecasts in k3's dma and usb driver expect dma_addr_t to be the
same size as the word size.
This leads the compiler to throw a "cast from pointer to integer of
different size" warning when the condition is not met, for example when
enabling CONFIG_DMA_ADDR_T_64BIT for the R5 core.
Therefore this patch fixes the typecasts by using 'uintptr_t' as an
intermediary type which is guaranteed to be the same size as void* on
the host architecture. Thus, eliminating the compiler warning.
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Since commit 5fb88fa725 "env: Rename SYS_REDUNDAND_ENVIRONMENT to ENV_REDUNDANT"
the option SYS_REDUNDAND_ENVIRONMENT is no longer available and should be
renamed to ENV_REDUNDANT.
Fixes: 95f03ee65c ("env: mmc: fix offsets relative to the end of the partition")
Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Enable CONFIG_DNS for visionfive2 board target. With CONFIG_PROT_DNS_LWIP
enabled and CONFIG_CMD_DNS disabled this restores DNS functionality
displaced by LwIP DNS refactoring during the merge window.
Signed-off-by: E Shattow <e@freeshell.de>
Booting u-boot as payload with coreboot's main branch is currently broken
since commit [1] on x86 as U-boot assumes the active GDT matches what
U-Boot would have installed in start16.S.
Make no assumptions and always load the GDT when building as coreboot
payload to make sure the segment registers are actually matching the GDT.
Fixes #GP seen when booting U-Boot as coreboot payload.
1: https://review.coreboot.org/c/coreboot/+/87255
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Link: https://review.coreboot.org/c/coreboot/+/87255
Reviewed-by: Tom Rini <trini@konsulko.com>
Neha Malcom FrancisandHeinrich Schuchardt
Sidharth SeelaandHeinrich Schuchardt
Yegor YefremovandTom Rini
Peng FanandTom Rini
Jerome ForissierandTom Rini
Marek Vasut
Mathieu OthaceheandMarek Vasut
Wadim EgorovandTom Rini
Raymond MaoandTom Rini
Primoz FiserandFabio Estevam
Ye LiandFabio Estevam
Kunihiko HayashiandTom Rini
Marek VasutandTom Rini
Anurag DuttaandTom Rini
Michal SimekandTom Rini
Alice GuoandFabio Estevam
E ShattowandTom Rini
Anshul DalalandTom Rini
Heiko ThieryandTom Rini
Patrick RudolphandTom Rini