Commit Graph
94493 Commits
Author SHA1 Message Date
Venkatesh Yadav AbbarapuandMichal Simek 8bfbc09aef arm64: versal2: Add support for mini configuration
Versal2 mini configuration is designed for running memory test.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20240619071733.10256-2-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-08-05 16:10:36 +02:00
Venkatesh Yadav AbbarapuandMichal Simek 83cb220d47 xilinx: versal-net: Handle spi seq number based on boot device
Versal NET boards has QSPI and OSPI and default bus set to 0
is not working when system is booting out of OSPI which is
controller 1, as fixed aliases are set for all the boards
i.e., QSPI to 0 and OSPI to 1. Add controller autodetection
via spi_get_env_dev().

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20240614124811.22945-3-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-08-05 16:10:36 +02:00
Venkatesh Yadav AbbarapuandMichal Simek 7d84ad1da0 env_spi: support overriding spi dev from board code
This enables boards to choose where to/from the environment
should be saved/loaded. They can then for example support using
the same device (dynamically) from which the bootloader was
launched to load and save env data and do not have to
define CONFIG_ENV_SPI_BUS statically.

In my use case, the environment needs to be on the same device I
booted from. It can be the QSPI or OSPI device.
I therefore would override spi_get_env_dev in the board code,
read the bootmode registers to determine where we booted from
and return the corresponding device index.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20240614124811.22945-2-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com> # Move spi_get_env_dev to sf.c
2024-08-05 16:10:36 +02:00
Prasad KummariandMichal Simek c43d65e266 mtd: spi-nor: ids: Add IS25LP01GG flash support
Add support for ISSI 128MB flash IS25LP01GG. This part
supports 4byte opcodes. It also supports dual and quad
read.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20240617041841.1336632-1-prasad.kummari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-08-05 16:10:36 +02:00
Michal Simek 510faea376 arm64: versal2: Remove UARTLITE from defconfig
UARTLITE can be used as console but none is testing it that's why removing
it not to pop up there.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c9b66495bbdef3fe94467ae43c50a74adaaeacae.1718716833.git.michal.simek@amd.com
2024-08-05 16:10:36 +02:00
Venkatesh Yadav AbbarapuandMichal Simek 9ae5bbf08a config: Enable the config CONFIG_MMC_SPEED_MODE_SET
Enable setting speed mode using mmc dev commands.
The speed mode is provided as the last argument in these commands
(ex: mmc dev 0 0 10) and is indicated using the index from enum
bus_mode in include/mmc.h. A speed mode can be set if it is enabled
from device tree or from capabilities register

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20240708091755.5021-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-08-05 16:10:36 +02:00
Venkatesh Yadav AbbarapuandMichal Simek aceac0c52b clk: zynqmp: Add set_rate support for display clocks
If "assigned-clock-rates" property is included in the
device tree, display driver probe is getting failed, as dp_video_ref
till dp_stc_ref clocks are missing from set rate function, adding
them to fix the probe failure.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20240711082939.29260-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-08-05 16:10:36 +02:00
Tom Rini 6becf9ba1a Merge tag 'u-boot-imx-master-20240802' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/21846

- Convert warp7 to OF_UPSTREAM.
- Add 'cpu' command to imx8m and imx93.
- Enable CMD_ERASEENV for imx8mm/mp Phytec boards.
2024-08-02 14:40:59 -06:00
Lukasz MajewskiandFabio Estevam 0ee02e1c25 config: Adjust Phytec imx8mm module config to support NVME disk
This change adds support for PCIe connected nvme disk - phyBOARD-Polis
base board.

One needs to call following commands in u-boot:
> pci enum
> nvme scan
> nvme info

And then ones to access proper file system (like fat[ls|load|write],
ext4[ls|load|write]).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2024-08-02 15:16:54 -03:00
Hou ZhiqiangandFabio Estevam 84febc4d9a configs: imx93: enable the 'cpu' command
Enable the 'cpu' command to display the CPU info and release CPU core to
run baremetal or RTOS applications.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2024-08-02 15:16:51 -03:00
Hou ZhiqiangandFabio Estevam 796b22667b configs: imx8m: enable the 'cpu' command
Enable the 'cpu' command and the depended imx CPU driver to
display the CPU info and release CPU core to run baremetal
or RTOS applications.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2024-08-02 15:16:51 -03:00
Hou ZhiqiangandFabio Estevam effe1fd2f0 MAINTAINERS: add entry for cpu command
Added the original author Simon and myself.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-08-02 15:16:51 -03:00
Hou ZhiqiangandFabio Estevam 486b6e1c43 doc: cmd: add documentation for cpu command
Add documentation for the 'cpu' command, taking NXP i.MX 8M Plus
as a example.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-08-02 15:16:51 -03:00
Hou ZhiqiangandFabio Estevam 476fb4d8ea cmd: cpu: add release subcommand
Add a new subcommand 'release' to bring up a core to run baremetal
and RTOS applications.

For example on i.MX8M Plus EVK, release the LAST core to run a RTOS
application, passing the sequence number of the CPU core to release,
here it is 3:
    u-boot=> cpu list
      0: cpu@0      NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
      1: cpu@1      NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 30C
      2: cpu@2      NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
      3: cpu@3      NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C

    u-boot=> load mmc 1:2 c0000000 /hello_world.bin
    66008 bytes read in 5 ms (12.6 MiB/s)
    u-boot=> dcache flush; icache flush
    u-boot=> cpu release 3 c0000000
    Released CPU core (mpidr: 0x3) to address 0xc0000000

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-08-02 15:16:51 -03:00
Hou ZhiqiangandFabio Estevam 8a73b5b680 cpu: imx: implement release_core callback
Release the secondary cores through the PSCI request.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2024-08-02 15:16:51 -03:00
Hou ZhiqiangandFabio Estevam 01d94d006a cpu: imx: Add i.MX 8M series SoCs
Add i.MX 8M Mini, Nano and Plus SoCs support.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2024-08-02 15:16:51 -03:00
Hou ZhiqiangandFabio Estevam b7ed7418ed cpu: imx: removed the tail '\n' of the CPU description
Return CPU description string without newline character in the end.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2024-08-02 15:16:51 -03:00
Hou ZhiqiangandFabio Estevam 37adedfb21 cpu: imx: fix the CPU type field width
Increase one more bit to cover all CPU types. Otherwise it shows
wrong CPU info on some platforms, such as i.MX8M Plus:

    U-Boot 2024.04+g674440bc73e+p0 (Jun 06 2024 - 10:05:34 +0000)

    CPU:   NXP i.MX8MM Rev1.1 A53 at 4154504685 MHz at 30C

    Model: NXP i.MX8MPlus LPDDR4 EVK board

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2024-08-02 15:16:51 -03:00
Hou ZhiqiangandFabio Estevam dc86c11556 cpu: imx: fix the CPU frequency in cpu_imx_get_info()
The cpu_freq stores the current CPU frequency in Hz.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2024-08-02 15:16:51 -03:00
Hou ZhiqiangandFabio Estevam 8b8217249f test: cpu: add test for release CPU core.
Add test for API cpu_release_core().

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-08-02 15:16:51 -03:00
Hou ZhiqiangandFabio Estevam 3694edcabc cpu: sandbox: implement release_core callback
Add empty release CPU core function for testing.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-08-02 15:16:51 -03:00
Hou ZhiqiangandFabio Estevam f2c306cd99 cpu: add release_core callback
Add a new callback release_core to the cpu_ops, which is used to
release a CPU core to run baremetal or RTOS application on a SoC
with multiple CPU cores.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-08-02 15:16:51 -03:00
Hou ZhiqiangandFabio Estevam 3cdcdcecac clk: imx8m: register ARM A53 core clock
Register ARM A53 core clock for i.MX 8M Mini, Nano and Plus, preparing
for enabling the 'cpu' command, which depends on this to print CPU core
frequency.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2024-08-02 15:16:51 -03:00
Yannic MoogandFabio Estevam ecc5dd777e configs: phycore-imx8mp_defconfig: enable CMD_ERASEENV
Enable erasing environment with eraseenv command.

Signed-off-by: Yannic Moog <y.moog@phytec.de>
2024-08-02 15:08:19 -03:00
Yannic MoogandFabio Estevam 60e01c6d9f configs: phycore-imx8mm_defconfig: enable CMD_ERASEENV
Enable erasing environment with eraseenv command.

Signed-off-by: Yannic Moog <y.moog@phytec.de>
2024-08-02 15:06:17 -03:00
Yannic MoogandFabio Estevam 01e8aaf677 configs: imx8mm-phygate-tauri-l_defconfig: enable CMD_ERASEENV
Enable erasing environment with eraseenv command.

Signed-off-by: Yannic Moog <y.moog@phytec.de>
2024-08-02 15:06:02 -03:00
Fabio Estevam 24bd74851d warp7: Convert to OF_UPSTREAM
Instead of using the local imx7s-warp devicetree copies from U-Boot,
convert the imx7s-warp board to OF_UPSTREAM so that the upstream
kernel devicetree can be used instead.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2024-08-02 15:05:44 -03:00
Michael TrimarchiandTom Rini a70d991212 clk: clk-uclass: Print clk name in clk_enable/clk_disable
Print clk name in clk_enable and clk_disable. Make sense to know
what clock get disabled/enabled before a system crash or system
hang.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2024-08-01 15:35:28 -06:00
Alexander DahlandTom Rini 133f67a361 clk: Revise help text for clk_get_parent_rate()
The function returns the rate of the parent clock, the previous text
made no sense at all.

Fixes: 4aa78300a0 ("dm: clk: Define clk_get_parent_rate() for clk operations")
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2024-08-01 15:33:19 -06:00
Jan KiszkaandTom Rini 068c346703 clk: Fix error message in clk_get_bulk
Fix a logical inversion of the printed text.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2024-08-01 15:33:14 -06:00
Tom Rini 6c243dd5e5 Merge patch series "clk: mediatek: add OPs to support OF_UPSTREAM"
Christian Marangi <ansuelsmth@gmail.com> says:

This series doesn't currently change anything and it does add all the
additional OPs to make support of OF_UPSTREAM.

While converting the mt7681/7686/7688/7623/7622 it was notice lots of
discrepancy between the downstream dtsi and the upstream one and the
clock ID between downstream clock ID and upstream clock ID.

Upstream reference clock by names and clock are handled by the
CCF (Common Clock Framework). The same can't be used here as we would
quickly reach the max space allocated before relocation.

The current mediatek clock driver reference all the parents and clocks
with offset from the clk ID related to the different tables.

Discrepancy between clock ID and the order in the clocks table cause
one clock referenced for another or even crash for trying to access
a clock at an offset that doesn't exist.

To handle this and permit use of OF_UPSTREAM, various measure and
changes are done to the mediatek clock driver to support it.

This series have all the generic clock changes. Once this is merged,
series for each SoC will came that will just change files in their
dedicated clock driver. This is to prevent massive patch and to
permit to split series, one for each SoC.

As said at the start, these changes doesn't cause regression and are
just expansion to the current API. Current behaviour is saved in every
possible way (aside from the first 2 patch that fixes latent bugs)
2024-08-01 15:32:54 -06:00
Christian MarangiandTom Rini dfbdfbbd7f clk: mediatek: add support for APMIXED parent in infra MUX
Add support for APMIXED parent in infra MUX. This is the case for mt7622
that reference APMIXED parents for the MUX1_SEL clock.

We assume the second level parent is always APMIXED.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-01 15:32:18 -06:00
Christian MarangiandTom Rini ffe3983f67 clk: mediatek: add support for GATEs for APMIXED OPs
Add support for GATEs for APMIXED OPs. It's possible that some APMIXED
have also gates on top of PLL. This is the case for mt7622. Add support
for this.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-01 15:32:18 -06:00
Christian MarangiandTom Rini 591edaebc8 clk: mediatek: implement MUX_FLAGS and MUX_MIXED_FLAGS macro
Some simple MUX might require flags to specify the parent source.
Implement MUX_FLAGS as a variant of the MUX macro that takes custom
flags as last arg.
Also implement MUX_MIXED_FLAGS for PARENT_MIXED implementation and
MUX_MIXED with no additional flags.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-01 15:32:18 -06:00
Christian MarangiandTom Rini 64ecc60e4b clk: mediatek: add support for remapping clock ID
Upstream kernel linux might have a different clock ID order in their
<soc>-clk.h header. This is the case of some clock ID for mt7623 that
upstream use the shared header clk-mt7601.h

This header doesn't have a well distincted order and have factor or mux
in the middle of the CLK ID list. This is problematic with the mtk clock
driver that expect everything well organized in block and apply offset
to reference the clk in the different array.

To solve this problem, implement in the mtk_clk_tree an additional
option .id_offs_map, an array where each CLK ID can be remapped to what
the driver expect permitting to reorganize the clock following the
expected logic of fixed, factor, mux and gates.

Each clock function is updated to tranparently handle this by first
converting the clk ID to the remapped one.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-01 15:32:18 -06:00
Christian MarangiandTom Rini 04ab229fdc clk: mediatek: provide common clk init function for infrasys
Provide common clk init function for infrasys that defaults to topckgen
driver if clock-parent is not defined. This is the case for upstream
DTSI that doesn't provide this entry.

This is needed for infracfg driver that will make use of the unified
gates + muxes implementation.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-01 15:32:18 -06:00
Christian MarangiandTom Rini a38cf1b2db clk: mediatek: add support for gate clock to reference topckgen clock
Add support for gate clock get_rate to reference topckgen clock for
infracfg-ao implementation.

In infracfg-ao implementation topckgen is on second level of parent with
infracfg in the middle.
To correctly detect this, check the driver of the dev parent and use the
second level parent if it's not mtk_clk_topckgen.

Due to all the dependency, parent tree must be filled before a gate is
used, hence is safe to assume it will be there.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-01 15:32:18 -06:00
Christian MarangiandTom Rini cd3b487752 clk: mediatek: add support for parent mux from different source for topckgen
As done for infracfg, also add support for parent mux from different
source for topckgen. This is needed as upstream linux doesn't use 1/1
factor and use directly the APMIXED clocks.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-01 15:32:18 -06:00
Christian MarangiandTom Rini 89eff11485 clk: mediatek: add support for parent mux from different source
There is a current limitation where parents for a mux can be all declared
as they are from a common source. This is not true as there are some MUX
that can have parent from both infracfg or from topckgen.

To handle this, implement a new flag for the mux, CLK_PARENT_MIXED, and
a new entry for the mux parent_flags.

To use this, CLK_PARENT_MIXED must be used and parent_flags will be used
instead of the parent variable.

Entry in parent_flags are just a struct of ID and flags where it will be
defined where that parent comes from with the usage of
CLK_PARENT_INFRASYS or CLK_PARENT_TOPCKGEN.

This permits to have MUX with parents from infracfg or topckgen.

Notice that with CLK_PARENT_MIXED applied the CLK_BYPASS_XTAL is
ignored.
With CLK_PARENT_MIXED declare CLK_PARENT_XTAL for the relevant parent
instead.

Also alias for the CLK_PARENT macro are provided to better clear their
usage. CLK_PARENT_MIXED require these alias that describe the clk type
to be defined in the clk_tree flags to prevent clk ID clash from
different subsystem that may have equal clk ID.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-01 15:32:18 -06:00
Christian MarangiandTom Rini a03174cbfa clk: mediatek: add support for gate ID at offset
Add support to clk_gate ops to reference the clk ID at an offset by
using the just introduced gates_offs value from the unified muxes +
gates implementation.

Gate clock that doesn't have gates_offs set won't be affected as the
offset will simply be 0 and won't be offset of any value.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-01 15:32:18 -06:00
Christian MarangiandTom Rini 432cb967b0 clk: mediatek: add support for gates in clk_tree for infrasys
Add support for gates in clk_tree for infrasys ops.

Infracfg clks can have a sum of gates and muxes, and current solution
handle this by duplicating the driver and split clks for mux and clks
for gates. Upstream linux kernel handle this differently and doesn't
have this distinction.

To be closer to the upstream kernel clock definition, implement
additional logic to have gates defined in the clk_tree and implement
variant for the infrasys ops to handle gates defined in the tree.

Similar to how it's done with factor and mux, we introduce gates_offs.
Upstream kernel follow the similar logic with all the ID defined as
FDIVS, MUXES and finally GATES.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-01 15:32:18 -06:00
Christian MarangiandTom Rini bf6ba78143 clk: mediatek: return XTAL rate for infrasys get_mux_rate
We currently return 0 if XTAL rate is requested in get_mux_rate. This
deviates from what is done in get_factor_rate and is totally wrong as it
can cause unwanted results (division by 0 crash)

For infrasys that makes use of CLK_XTAL, assume xtal_rate to be defined
in clk_tree and return the rate when BYPASS_XTAL is not enabled with
clk ID 0 index parents.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-01 15:32:18 -06:00
Christian MarangiandTom Rini ed908c4868 clk: mediatek: return XTAL rate directly for gates with XTAL parent
There is currently a massive bug that makes any gate clk that have
CLK_XTAL as parent to return the wrong clock.

Following the code, with CLK_XTAL defined as TOPCKGEN parent, the
topckgen get_rate is called. The clk ID (0) is parsed and only in some
corner case (scenario where fixed clock are not defined) the correct
XTAL rate will be returned as get_factor or get_mux is called (that have
correct handling for CLK_XTAL). With fixed clock defined, the rate that
will be returned will always be the FIRST ELEMENT of the fixed clock
table instead of the hardcoded XTAL rate.

To handle this, add additional logic and if the flag is set to
PARENT_XTAL for the gate, return the XTAL rate directly.

We assume the clk_tree to have xtal_rate defined with clk gates that
have XTAL as parents.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-01 15:32:18 -06:00
Philip OberfichtnerandTom Rini 151b8857d7 net: dwc_eth_qos: mdio: Implement clause 45
Bevor this commit, only clause 22 access was possible. After this commit,
clause 45 direct access will available as well.

Note that there is a slight change of behavior: Before this commit, the
C45E bit was set to whatever value was left in the register from the
previous access. After this commit, we adopt the common practice of
discerning C45 from C22 using the devad argument.

Signed-off-by: Philip Oberfichtner <pro@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2024-08-01 08:10:05 -06:00
Mikhail KshevetskiyandTom Rini 1dd034ec00 net/tftp: make tftpput working with servers that do not use OACK
Option Acknowledgment (OACK) is an extension of TFTP protocol (see rfc2347).
Not all tftp servers implements it. For example it does not supported by
tftpd server from debian-11 (https://packages.debian.org/bullseye/tftpd).

Starting the "tftpput $loadaddr $size out_file" command with such server
will results in the following packets flow:

192.168.27.3   192.168.27.1   TFTP   Write Request, ...
192.168.27.1   192.168.27.3   TFTP   Acknowledgement, Block: 0
192.168.27.3   192.168.27.1   TFTP   Write Request, ...
192.168.27.1   192.168.27.3   TFTP   Acknowledgement, Block: 0
192.168.27.3   192.168.27.1   TFTP   Write Request, ...
192.168.27.1   192.168.27.3   TFTP   Acknowledgement, Block: 0
192.168.27.1   192.168.27.3   TFTP   Acknowledgement, Block: 0
192.168.27.1   192.168.27.3   TFTP   Acknowledgement, Block: 0
...

so, no data transfer happening.

Here is a packets flow for tftp-server with OACK support
(tftpd-hpa: https://packages.debian.org/stable/tftpd-hpa)

192.168.27.3   192.168.27.1   TFTP   Write Request, ...
192.168.27.1   192.168.27.3   TFTP   Option Acknowledgement, ...
192.168.27.3   192.168.27.1   TFTP   Data Packet, Block: 1
192.168.27.1   192.168.27.3   TFTP   Acknowledgement, Block: 1
192.168.27.3   192.168.27.1   TFTP   Data Packet, Block: 2
192.168.27.1   192.168.27.3   TFTP   Acknowledgement, Block: 2

and this time data transfer starts normally.

As we can see there is no OACK packet in the first case. Investigating
an issue we'll find out:

1) tftp_start() sets

      tftp_state = STATE_SEND_WRQ;

2) on OACK tftp_handler() sets

      tftp_state = STATE_DATA;

   and send a first DATA packet.

3) on ACK tftp_handler() will call a tftp_send() function.
   tftp_send() will

   * tftpd with OACK support:

       Current state is STATE_DATA, so transmittion of data packet will
       happen.

   * tftpd without OACK support

      Current state is STATE_SEND_WRQ, so retransmission of WRQ packet
      will happen. Thus tftpd-server will retransmit an ACK.

      This will repeats until timeout happens.

      According to RFC1350 this is wrong. We should start data transfer
      instead of WRQ retransmission.

This patch fix an issue, so tftpput works fine with both types of servers.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2024-08-01 08:10:00 -06:00
Alexander SverdlinandTom Rini fb2f2a38b6 net: remove duplicate eth_env_set_enetaddr_by_index() declaration
eth_env_set_enetaddr_by_index() declaration is duplicated in eth_internal.h
and net.h, but all units including eth_internal.h already include net.h.
Remove the superfluous declaration.

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
2024-07-31 17:55:08 -06:00
Tom Rini 7010f22eba Merge tag 'video-20240731' of https://source.denx.de/u-boot/custodians/u-boot-video
- improve video sync performance with background syncing (cyclic)
 - fix dropping characters when pasting commands over the UART
 - enable background syncing by default for boards using VIDEO
 - make sandbox video more responsive
2024-07-31 13:39:14 -06:00
Simon GlassandTom Rini 59ca3a2f20 usb: bootm: Drop old USB-device-removal code
USB is stopped using driver model now, in dm_remove_devices_flags() in
announce_and_cleanup() at the top of this file.

The usb_stop() call actually unbinds devices.

When a USB device is unbound, it causes any bootflows attached to it to
be removed, via a call to bootdev_clear_bootflows() from
bootdev_pre_unbind(). This obviously makes it impossible to boot the
bootflow.

However, when booting a bootflow that relies on USB, usb_stop() is
called, which unbinds the device. At that point any information
attached to the bootflow is dropped.

This is quite risky since the contents of freed memory are not
guaranteed to remain unchanged. Depending on what other options are
done before boot, a hard-to-find bug may crop up.

Drop the call to this old function.

Leave the netconsole call there, since this needs conversion to
driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Shantur Rathore <i@shantur.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-07-31 11:20:57 -06:00
Raymond MaoandTom Rini c502d7ada2 tools: Add script to update git subtree projects
Recently we are introducing multiple git subtree projects and
it is the right time to have a universal script to update
various subtrees and replace the dts/update-dts-subtree.sh.

update-subtree.sh is a wrapper of git subtree commands.

Usage: From U-Boot top directory,
run
$ ./tools/update-subtree.sh pull <subtree-name> <release-tag>
for pulling a tag from the upstream.
Or run
$ ./tools/update-subtree.sh pick <subtree-name> <commit-id>
for cherry-pick a commit from the upstream.

Currently <subtree-name> supports dts, mbedtls and lwip.

Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
2024-07-31 11:20:36 -06:00
Mattijs KorpershoekandTom Rini b2345dbdaa env: mmc: Fix env loading with CONFIG_SYS_MMC_ENV_PART
When CONFIG_SYS_MMC_ENV_PART=2, the environment is loaded from
the USER partition (hwpart=0) instead of from the
BOOT1 partition (hwpart=2).

IS_ENABLED() cannot be used for non-boolean KConfig options.
Its documentation states:

> * IS_ENABLED(CONFIG_FOO) evaluates to 1 if CONFIG_FOO is set to 'y',
> * 0 otherwise.

So in our case, IS_ENABLED(CONFIG_SYS_MMC_ENV_PART) evaluates to 0.

Because of this, the hwpart variable is never assigned and mmc_offset()
ends up switching back to the USER hwpart (0) instead of BOOT1 (2).

Fix it by using #define instead.

Tested with:

  # have CONFIG_SYS_MMC_ENV_PART=2 in defconfig
  # 1. Erase mmc0boot1
  => mmc dev 0 2
  => mmc erase 0 400
  => mmc read ${loadaddr} 0 400
  => md ${loadaddr} 4
  82000000: 00000000 00000000 00000000 00000000  ................

  # 2. Restore default environment and save to MMC
  => env default -a -f
  => saveenv

  # 3. Read back mmc0boot1 and confirm the env is present
  => mmc read ${loadaddr} 0 400
  => md ${loadaddr} 4
  82000000: 13e0632e 72646461 7469665f 3978303d  .c..addr_fit=0x9

Fixes: 5b4acb0ff7 ("env: mmc: Apply GPT only on eMMC user HW partition")
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-07-31 11:19:20 -06:00