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Author SHA1 Message Date
Biju DasandMarek Vasut 54db9e8b8f clk: renesas: Add R8A774B1 clock tables 
This sync's the RZ/G2N clock tables with mainline linux 5.9 commit
bbf5c979011a ("Linux 5.9").

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
 2020-10-20 12:56:51 +02:00
Lad PrabhakarandMarek Vasut fc5e552209 arm: dts: r8a774c0: Import DTS from Linux 5.9 
Import R8A774C0 (RZ/G2E) SoC DTSI and headers from Linux 5.9
commit bbf5c979011a ("Linux 5.9").

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
 2020-10-20 12:56:51 +02:00
Lad PrabhakarandMarek Vasut 051f1499c9 arm: renesas: Add config option for R8A774C0 SoC 
Add config support for RZ/G2E (a.k.a R8A774C0) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
 2020-10-20 12:56:51 +02:00
Biju DasandMarek Vasut aca749a90f arm: renesas: Add config option for R8A774E1 SoC 
Add config support for RZ/G2H(a.k.a R8A774E1) SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
 2020-10-20 12:56:46 +02:00
Biju DasandMarek Vasut 4e4c0e5e42 arm: renesas: Add config option for R8A774B1 SoC 
Add config support for RZ/G2N(a.k.a R8A774B1) SoC.

Also fixed the alignment issue on R8A774A1 config.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
 2020-10-20 12:56:46 +02:00
Biju DasandMarek Vasut f4c5f97925 clk: renesas: r8a774a1-cpg-mssr: Add R8A774A1 RPC clock 
Add RPC entry into the R8A774A1 clock driver tables.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
 2020-10-20 12:56:46 +02:00
Biju DasandMarek Vasut 2f220c639a spi: renesas_rpc_spi: Add R-Car Gen3 and RZ/G2 fallback compatibility string 
Add fallback compatibility string for R-Car Gen3 and RZ/G2.

Also sorted the compatible string as per SoC ID.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
 2020-10-20 12:56:46 +02:00
Tom Rini 7ec87e4192 Merge tag 'u-boot-atmel-2021.01-b' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel 
Second set of u-boot-atmel features for 2021.01 cycle:

This feature set brings the rework of the clock tree for sam9x60 SoC.
This makes the clock tree fully compatible with Common Clock Framework
and allows full clock configuration in U-Boot. This means that the
sam9x60 boards can boot now using U-Boot.
This also includes the definitions for sam9x60 SiPs and a divisor fix
for the clock on sama7g5 SoC.
 2020-10-19 09:29:05 -04:00
Eugen Hristev dc470834a1 clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics 
This SoC has the 5th divisor for the mck0 master clock.
Adapt the characteristics accordingly.

Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 2020-10-19 09:19:53 +03:00
Eugen Hristev dff3904254 clk: at91: clk-master: add 5th divisor for mck master 
clk-master can have 5 divisors with a field width of 3 bits
on some products.

Change the mask and number of divisors accordingly.

Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 2020-10-19 09:19:53 +03:00
Nicolas FerreandEugen Hristev db228c5b46 ARM: at91: Add chip ID for SAM9X60 SiP 
SAM9X60 SiP (System in Package) are added for SoC identification.

Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
 2020-10-19 09:19:53 +03:00
Claudiu BezneaandEugen Hristev 42f2dfa789 ARM: dts: sam9x60: use alphabetical order 
Use alphabetical order for entries in sam9x60ek-u-boot.dtsi

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 2020-10-19 09:19:53 +03:00
Claudiu BezneaandEugen Hristev 6973701e27 configs: sam9x60ek: update defconfigs for CCF 
Update defconfigs for using common clock framework compatible
clocks.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 2020-10-19 09:19:53 +03:00
Claudiu BezneaandEugen Hristev c37d59a170 ARM: dts: sam9x60: use CCF compatibles for PMC 
Use CCF compatible for PMC. With this, the board/SoC will be
able to boot.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 2020-10-19 09:19:53 +03:00
Claudiu BezneaandEugen Hristev dbe10b6274 ARM: dts: sam9x60: use slow clock CCF compatible bindings 
Use slow clock CCF compatible DT bindings. This will not break
the above functionality as the SoC is not booting with current
PMC bindings.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 2020-10-19 09:19:53 +03:00
Claudiu BezneaandEugen Hristev 5dff16db16 ARM: dts: sam9x60: use u-boot,dm-pre-reloc 
Use u-boot,dm-pre-reloc for slow xtal and main xtal.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 2020-10-19 09:19:53 +03:00
Claudiu BezneaandEugen Hristev ffd204f347 ARM: dts: sam9x60ek: add clock frequencies to board file 
Slow Xtal and Main Xtal are board specific. Add their proper
frequency to board file.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 2020-10-19 09:19:53 +03:00
Claudiu BezneaandEugen Hristev a64862284f clk: at91: sam9x60: add support compatible with CCF 
Add SAM9X60 clock support compatible with CCF.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 2020-10-19 09:19:53 +03:00
Claudiu BezneaandEugen Hristev 53040bc4d9 board: atmel: sam9x60ek: add SYS_MALLOC_F_LEN to SYS_INIT_SP_ADDR 
Heap base address is computed based on SYS_INIT_SP_ADDR by
subtracting the SYS_MALLOC_F_LEN value in
board_init_f_init_reserve().

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 2020-10-19 09:19:53 +03:00
Tom Rini e3e9bfab46 Merge tag 'video-for-2021.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-video 
- add dw-mipi-dsi phy timings and Tx escape clock configuration
 - fix pwm backlight duty cycle calculation
 - migrate CONFIG_VIDEO_BMP_* and CONFIG_BMP_* to Kconfig
 2020-10-18 21:19:06 -04:00
Patrick DelaunayandAnatolij Gustschin 8fc78fc73b configs: migrate CONFIG_BMP_16/24/32BPP to defconfigs 
Done with:
./tools/moveconfig.py BMP_16BPP BMP_24BPP BMP_32BPP

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
 2020-10-18 15:27:01 +02:00
Patrick DelaunayandAnatolij Gustschin f9a48654ee configs: migrate CONFIG_VIDEO_BMP_RLE8 to defconfigs 
Done with:
./tools/moveconfig.py VIDEO_BMP_RLE8

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
 2020-10-18 15:26:14 +02:00
Patrick DelaunayandAnatolij Gustschin 0ed6c0f9cb configs: migrate CONFIG_VIDEO_BMP_GZIP to defconfigs 
Done with:
./tools/moveconfig.py VIDEO_BMP_GZIP

The 3 suspicious migration because CMD_BMP and SPLASH_SCREEN
are not activated in these defconfigs:
- trats_defconfig
- s5pc210_universal_defconfig
- trats2_defconfig

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
 2020-10-18 15:25:28 +02:00
Dario BinacchiandAnatolij Gustschin 76c2ff3e5f video: backlight: fix pwm's duty cycle calculation 
For levels equal to the maximum value, the duty cycle must be equal to
the period.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
 2020-10-18 15:07:33 +02:00
Dario BinacchiandAnatolij Gustschin f9b94055bd video: backlight: fix pwm data structure description 
The description of the 'max_level' field was incorrectly assigned to the
'min_level' field.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
 2020-10-18 15:06:56 +02:00
Neil ArmstrongandAnatolij Gustschin 01c9857fa8 video: dw-mipi-dsi: permit configuring the escape clock rate 
The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency
higher than 10MHz for the TX Escape Clock, thus make the target rate
configurable.

This is based on the Linux commit [1] and adapted to the U-Boot driver.

[1] a328ca7e4af3 ("drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate")

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
 2020-10-18 10:36:05 +02:00
Neil ArmstrongandAnatolij Gustschin b53c122631 video: dw-mipi-dsi: driver-specific configuration of phy timings 
The timing values for dw-dsi are often dependent on the used display and
according to Philippe Cornu will most likely also depend on the used phy
technology in the soc-specific implementation.

To solve this and allow specific implementations to define them as needed
add a new get_timing callback to phy_ops and call this from the dphy_timing
function to retrieve the necessary values for the specific mode.

This is based on the Linux commit [1] and adapted to the U-Boot driver.

[1] 25ed8aeb9c39 ("drm/bridge/synopsys: dsi: driver-specific configuration of phy timings")

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
 2020-10-18 10:35:06 +02:00
Sean AndersonandTom Rini 3d19a7ee8c test: Fix sandbox tests failing to build 
syslog_test.h is in test/log/, not include/

Fixes: 52d3df7fef ("log: Allow LOG_DEBUG to always enable log output")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
 2020-10-17 09:03:22 -04:00
Tom Rini dadc1e3830 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell 
- Fix Octeon SPI driver for Octeon TX2
- Fix and enhance Octeon watchdog driver
- Misc minor enhancements to Octeon TX/TX2
 2020-10-16 09:56:15 -04:00
Tom Rini da09b99ea5 Merge branch '2020-10-15-further-cleanup_dev_xxx' 
- Bring in the next round of dev_xxx cleanup patches.
 2020-10-16 09:44:51 -04:00
Sean AndersonandTom Rini 4a1989c0bc dm: Don't undefine dev_xxx macros 
Now that linux/compat.h does not define these macros, we do not need to
undefine them.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
 2020-10-16 09:44:27 -04:00
Sean AndersonandTom Rini 69dae8902b linux/compat.h: Remove redefinition of dev_xxx macros 
All users of these functions now include dm/device_compat.h directly.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
 2020-10-16 09:44:27 -04:00
Tom Rini 2e84463188 usb: dwc3: Include device_compat.h in dwc3-octeon-glue.c 
Necessary for dev_xxx.

Signed-off-by: Tom Rini <trini@konsulko.com>
 2020-10-16 09:44:27 -04:00
Tom Rini 689639798a clk: at91: Include device_compat.h in compat.c 
Necessary for dev_xxx.

Signed-off-by: Tom Rini <trini@konsulko.com>
 2020-10-16 09:44:27 -04:00
Tom Rini e1f306c07c arm: fsl-layerscape: Include device_compat.h in soc.c 
Necessary for dev_xxx.

Signed-off-by: Tom Rini <trini@konsulko.com>
 2020-10-16 09:44:27 -04:00
Sean AndersonandTom Rini 0b4826a9a8 usb: musb-new: mt85xx: Fix not calling dev_err with a device 
This driver doesn't use DM (in the correct places), so we use a device and
not a udevice. We also need to include device_compat.h

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 2020-10-16 09:44:27 -04:00
Sean AndersonandTom Rini e010524b5d usb: musb-new: Include device_compat.h 
This was included, but was ifdef'd out. We also need dm.h for struct
udevice.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 2020-10-16 09:44:27 -04:00
Sean AndersonandTom Rini f526aee31f usb: xhci: Include device_compat.h 
This header is necessary for the dev_xxx macros.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 2020-10-16 09:44:27 -04:00
Sean AndersonandTom Rini a5d4f86124 timer: Include device_compat.h 
Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
 2020-10-16 09:44:27 -04:00
Sean AndersonandTom Rini 7399897b6c tee: optee: Include device_compat.h 
Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
 2020-10-16 09:44:27 -04:00
Sean AndersonandTom Rini d13da03f3b spi: fsl_qspi: Include device_compat.h 
Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 2020-10-16 09:44:27 -04:00
Sean AndersonandTom Rini 06aaca5158 spi: nxp_fspi: Include device_compat.h 
Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 2020-10-16 09:44:27 -04:00
Stefan Roese b666714c30 arm: octeontx: Add CMD_WDT 
Enable WDT command for Octeon TX/TX2 boards.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
 2020-10-16 13:55:04 +02:00
Suneel GarapatiandStefan Roese 3981cdd8db watchdog: octeontx_wdt: Add support for start and stop 
This patch enhances the Octeon TX/TX2 watchdog driver to fully enable
the WDT. With this changes, the "wdt" command is now also supported
on these platforms.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
 2020-10-16 13:55:04 +02:00
Stefan Roese 7a78074c18 arm: octeontx: Select CLK 
Clock support is needed for all Octeon TX/TX2 boards. This patch selects
CONFIG_CLK so that it is available.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
 2020-10-16 13:55:04 +02:00
Stefan Roese 7353025dd4 mmc: octeontx_hsmmc.c: Remove test debug message 
Remove a left-over debug test message from the Octeon TX / TX2
MMC driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
 2020-10-16 13:55:04 +02:00
Stefan Roese 8a35094faa spi: octeon_spi: Use a fixed 100MHz input clock on Octeon TX2 
Octeon TX2 sets the TB100_EN bit in the config register. We need to use
a fixed 100MHz clock for this as well to work properly.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
 2020-10-16 13:55:04 +02:00
Sean AndersonandTom Rini 8d4c596644 ram: imxrt: Include device_compat.h 
Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 2020-10-15 18:36:56 -04:00
Sean AndersonandTom Rini bdc1fdf6fc phy: Include device_compat.h 
Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 2020-10-15 18:36:56 -04:00
Sean AndersonandTom Rini d878ef736d net: ldpaa_eth: Include device_compat.h 
Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 2020-10-15 18:36:56 -04:00