Add support for the Renesas MFIS mailbox, which provides an interface
between the different CPU Cores, such as AP System Core domain and the
Realtime Core domain, SCP Core domain and AP System Core domain or
Realtime Core domain and AP System Core domain or Realtime Core domain.
Signed-off-by: Tuyen Dang <tuyen.dang.xa@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Update the driver
[Marek: Rename the driver to renesas-mfis, simplify the driver.
Always use only one TX channel and no RX channel, drop all
unnecessary code. Perform 1ms delay in send callback which
is perfectly fine to do in U-Boot which does RX polling]
The current state of SCP on Renesas R-Car Gen5 is not yet final and
is still missing full clock control, the clock control is exposed as
separate enable/disable and rate controls.
Temporarily introduce custom local compound clock, which are used as
an adaptation layer between U-Boot clock tree and current state of
SCP, and which bind two SCP clock into a single compound clock, which
provides both enable/disable and rate controls.
This is mainly meant to be used by SD/eMMC controller, to allow the
driver to both turn its clock on and off, and also obtain the current
clock rate. This is going to be removed once the SCP clock protocol
solidifies.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Make sure the end of U-Boot is at 8-byte aligned offset, not 4-byte
aligned offset. This allows safely appending DT at the end of U-Boot
with the guarantee that the DT will be at 8-byte aligned offset. This
8-byte alignment is now checked by newer libfdt 1.7.2 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The redundant environment offset is already set in board configuration,
but the redundant environment itself is not explicitly enabled. Make
sure the redundant environment is enabled, as we most certainly do want
to have two copies of the environment.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The CONFIG_ENV_OVERWRITE allows easy rewrite of environment variables
like 'ethaddr' and 'serial#' without any protection against accidental
removal of those variables. Remove this setting to add extra layer of
protection to those variables. The variables can still be overridden
using 'env set -f' (force set) if really needed.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Document the image preparation and flashing techniques for
Exynos7870-based boards. This is done in a separate file in a
sub-directory, which is linked back to the main documentation.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add basic support for the Exynos7870 SoC, this includes device tree
match logic using multiple boards, where devices use a stub dtb in
Samsung's QCDT format. S-BOOT, the previous stage bootloader, places its
cmdline arguments there, which has identifying information.
This is added with support for three devices:
* Samsung Galaxy A2 Core (codename: a2corelte)
* Samsung Galaxy J6 (codename: j6lte)
* Samsung Galaxy J7 Prime (codename: on7xelte)
Add their device trees in the defconfig, and also enable the clock and
pin controller drivers.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add support for a generic platform which intends to support multiple
boards powered by ARMv8 Samsung Exynos SoCs. Some important features
include:
* Fastboot: This is present to provide an open alternative to Samsung's
proprietary Odin protocol. The board file configures certain features
for fastboot, such as a dynamically allocated fastboot buffer, and
standardized (lowercase) partition aliases.
* EFI: Kernel image can be loaded from an EFI partition. This
adopts a standard booting process, which multiple OS distributions
can rely on.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This pull request delivers a broad set of improvements across the
SoCFPGA family, including Agilex5, Cyclone V, SoC64, and common code.
Key updates include refined boot flows, new driver enablement, handoff
tooling enhancements, and several stability fixes.
Highlights:
* Agilex5:
- Enable FAT-based environment storage
- MMC driver restores legacy clkmgr-based clock lookup
- Cleanup of MMC raw mode enablement logic
* Cyclone V:
- SPL FAT boot support and updated bootcmd sequence
- Disable SPL SPI to prevent contention with FAT-based boot
- New board handoff script and BSP generator tooling
- Optimized Makefile support for SoCFPGA handoff workflows* New drivers:
- Cadence xSPI driver with full protocol and command support
- SPL enablement for DW APB GPIO controller
* Networking:
- xgmac MDIO now supports Clause 45 read/write operations
* NAND / SoC64:
- Enable ONFI detection in Denali NAND controller for SoC64 devices
* DTS and board updates:
- Sync common SoCFPGA U-Boot DTS with kernel sources
- Fixes for FPGA2SDRAM configuration and SoCFPGA boot stall behavior
- Vining_FPGA migrated to the modern LED framework
- Device tree relocation no longer forced off for Vining FPGA
* Tooling:
- Introduces a new Python-based Cyclone V BSP generator
covering EMIF, IOCSR, HPS, XML parsing, rendering, and documentation
to simplify board enablement and handoff regeneration workflows
Overall, this series improves boot robustness, enhances xSPI and MDIO
capabilities, modernizes board support, and introduces new tooling to
streamline SoCFPGA handoff generation.
Pipelines test passing
https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/28569
The problem we face currently with Azure jobs is that we're running out
of disk space on the runners as we build. There's not a good way to
split approximately 1500 configurations across 10 jobs and not be close
to or exceeding that limit. Split this in to 29 jobs instead with a goal
of averaging an hour per job. This split gets us close, but there are
still some challenging jobs to try and break up further. The list is
mostly alphabetized but with some intentional changes (catch-all are
last, mx/imx are together, SoC family splits are just grouped together).
The average build time should be close to the same, but outliers can and
will happen.
Signed-off-by: Tom Rini <trini@konsulko.com>
- Introduce socfpga_g5_handoff_prepare target in U-Boot
arch/arm/mach-socfpga/config.mk
- Users can convert the handoff via make prepare.
- Detects Altera/Intel SoCFPGA boards from .config
- Combines vendor/board extraction into a single shell call
- Checks for hps_isw_handoff folder and .hiof files
- Uses ls -d instead of find for faster folder detection
- Runs BSP generator script only if files exist
- Non-blocking: continues if handoff folder or files are missing
- HANDOFF_PATH user define allows overriding auto-detected folder
- Minimizes subshells and other slow constructs for faster CI
Signed-off-by: Brian Sune <briansune@gmail.com>
bcm54210e_config() configures the RGMII delays and then calls
bcm5461_config(). But the latter will do a PHY soft reset and thus
resets the delay settings again. Call bcm5461_config() first to fix it.
Fixes: cba79a1b2e ("net: phy: broadcom: add support for BCM54210E")
Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Rafał Miłecki <rafal@milecki.pl>
According to the TI DP83869HM datasheet Revision D (June 2025), section
7.6.1.41 STRAP_STS Register, the STRAP_OPMODE bitmask is bit [11:9].
Fix this.
In case the PHY is auto-detected via PHY ID registers, or not described
in DT, or, in case the PHY is described in DT but the optional DT property
"ti,op-mode" is not present, then the driver reads out the PHY functional
mode (RGMII, SGMII, ...) from hardware straps.
Currently, all upstream users of this PHY specify both DT compatible string
"ethernet-phy-id2000.a0f1" and ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>
property, therefore it seems no upstream users are affected by this bug.
The driver currently interprets bits [2:0] of STRAP_STS register as PHY
functional mode. Those bits are controlled by ANEG_DIS, ANEGSEL_0 straps
and an always-zero reserved bit. Systems that use RGMII-to-Copper functional
mode are unlikely to disable auto-negotiation via ANEG_DIS strap, or change
auto-negotiation behavior via ANEGSEL_0 strap. Therefore, even with this bug
in place, the STRAP_STS register content is likely going to be interpreted
by the driver as RGMII-to-Copper mode.
However, for a system with PHY functional mode strapping set to other mode
than RGMII-to-Copper, the driver is likely to misinterpret the strapping
as RGMII-to-Copper and misconfigure the PHY.
For example, on a system with SGMII-to-Copper strapping, the STRAP_STS
register reads as 0x0c20, but the PHY ends up being configured for
incompatible RGMII-to-Copper mode.
Fixes: f3e22eea81 ("net: phy: add TI DP83869HM ethernet driver")
Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Use FIELD_GET()
Disable support for using SPI in SPL to solve Cyclone V storage issue as
the OCRAM is only 64kb. The SPI configurations are only
required during uboot proper only.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Enable support for FAT filesystem with SPL for CycloneV instead of raw
mode.
Recent changes breaks CycloneV MMC boot from raw mode, and so we are taking
this opportunity to migrate MMC boot mode to FAT as smaller OCRAM size is
required, as well as aligning MMC boot flow with our other devices.
Fixes: 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
We no longer use raw mode to boot from MMC for our devices in favor
of FAT filesystem.
Maintaining this config for legacy gen5 devices as to not risk breaking
any configurations still utilizing raw mode.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Restore legacy implementation of retrieving clkmgr base address from
mach-socfpga/misc.c driver for our legacy devices.
Excluding Agilex7/7M from this implementation as these devices' clock
driver is already following clock driver model and is supporting
enable/disable APIs.
The legacy devices' clock driver will have to be refactored to support
driver model which enables us to support enable/disable APIs for these
devices.
Fixes: ab27182cac ("mmc: socfpga_dw_mmc: Enable/disable SDMMC clock via API")
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
mkeficapsule tool will be built by default if EFI_LOADER is set due to
commit b7a625b1ce ("tools: Build mkeficapsule tool by default if
EFI_LOADER is set").
This will cause compilation error on all our SoCFPGA devices, hence we will
be disabling this config as we do not utilize this tool.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
This migrates from the legacy LED API to use the modern LED framework
which makes use of the FDT.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Acked-by: Tien Fong Chee <tien.fong.chee@altera.com>
Remove setting of fdt_high to ~0, which disables device tree relocation,
from the default environment. Doing so prevents U-Boot from correcting
problems such as having an unaligned device tree and leads to various
failure modes in the OS.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
Since U-Boot 2025.07 pure SD Card
boot no longer works. Now Altera released 2025.07
shows the different on the u-boot files.
After testing, the major root case is
get_managers_addr. And this patch fix the
SD boot stall via pulling from offical.
Signed-off-by: Brian Sune <briansune@gmail.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
The dtsi for socfpga common should
turn on L2 and memory and no reason not
to do so
Signed-off-by: Brian Sune <briansune@gmail.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Enable ONFI parameter page detection for SoCFPGA SoC64 devices by
selecting SYS_NAND_ONFI_DETECTION in the NAND_DENALI Kconfig entry.
This allows SoCFPGA SoC64 platforms using the Denali NAND controller
to automatically detect NAND parameters via the ONFI interface instead
of relying on hardcoded configuration values.
The selection is limited to TARGET_SOCFPGA_SOC64 to avoid affecting
non-SoC64 platforms that use legacy NAND handling.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Since turning from old build flow.
New Altera SoCFPGA requires converting handsoff
conversion via the python script. This is from
official provided, and now sync to U-Boot with
better location at tools/cv_xxxx. Meantime,
requirement.txt is also provided to further
explain the libraries require for these scripts.
Signed-off-by: Brian Sune <briansune@gmail.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
This patch ports the Cadence xSPI controller driver from
the Linux kernel. The controller supports three operating modes:
1. ACMD (Auto Command) mode
- Includes PIO and CDMA submodes.
- CDMA mode uses linked descriptors for high-performance,
low-overhead operation.
- PIO mode is suitable for simple, single-command transactions.
2. STIG (Software Triggered Instruction Generator) mode
- Issues low-level 128-bit instructions to memory.
- Uses the Slave DMA interface for data transfers.
3. Direct mode
- Enables direct data access through the slave interface
without commands.
Currently, only the STIG work mode is enabled. Additional modes will be
supported in future updates.
At the same time, also enabling the kconfig option for xSPI driver.
This driver has been ported and functionally verified on the Intel Simics
platform. It is intended for evaluation and experimental use at this stage.
Link: https://lore.kernel.org/all/1632038734-23999-1-git-send-email-pthombar@cadence.com/
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Enable storing the U-Boot environment in a FAT filesystem for Agilex5.
This allows the board to read and write environment variables from the
first partition of the first device formatted with FAT, in addition to the
existing UBI-based environment configuration.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
After testing, w/o proper setup
the FPGA2SDRAM bridge will not work and stall.
Pulling from official fix and w/o this initialization,
both 2025.07 and 2025.10 also suffer stall on U-Boot
and distro. Any FPGA to HPS-SDRAM action will immediate
stall the CPU. As such, this patch fix the issue.
Signed-off-by: Brian Sune <briansune@gmail.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Add SPL_DWAPB_GPIO configuration option to enable the Designware APB
GPIO driver in SPL builds.
Changes:
- Add SPL_DWAPB_GPIO Kconfig option with SPL_DM_GPIO dependency
- Update Makefile to use CONFIG_$(PHASE_)DWAPB_GPIO pattern for
conditional compilation in both SPL and main U-Boot builds
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Updates for RPi for 2026.01-rc4:
- rpi: Fix DRAM size reporting to show total RAM
- rpi: Use the U-Boot control FDT for fdt_addr
- pinctrl: bcm283x: Add GPIO pull-up/down control for BCM2835 and BCM2711
- rpi: Fix compilation with larger configs
The VideoCore mailbox GET_ARM_MEMORY only reports the size of the
first accessible memory region (~947 MiB on RPi4 with 8GB), not the
total RAM. This causes U-Boot to display "DRAM: 947 MiB (total 7.9 GiB)"
instead of "DRAM: 7.9 GiB".
On Raspberry Pi 4 with 8GB RAM, the memory is split across multiple
non-contiguous banks. The dram_init() function only sets gd->ram_size
to the first bank size reported by the VideoCore firmware, while
fdtdec_setup_memory_banksize() correctly populates all memory banks
from the device tree.
Fix this by updating gd->ram_size after dram_init_banksize() has
populated all memory banks, so it reflects the actual total RAM
across all banks.
Signed-off-by: Anders Roxell <anders.roxell@linaro.org>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
We should avoid overwhelming users with non-essential messages.
'Register NbrPorts' is a debug message for EHCI. Do the same for XHCI.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
The SPL_STACK config option now depends on having SPL_HAVE_INIT_STACK
defined. This made savedefconfig dropping SPL_STACK when sending the
initial configuration.
Note that SPL/U-Boot are able to boot linux from mass storage with
SPL_STACK not set but other use cases might run out of stack or
overlap with other RAM use.
Compare with:
commit d6a53f523a ("spl: Add an SPL_HAVE_INIT_STACK option")
commit 25fefa05d7 ("configs: Resync with savedefconfig")
Fixes: ff0540fcfe ("board: toradex: add Toradex SMARC iMX95")
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Partitions can be become unusable due to power cuts or failed updates.
Use the bootmeth RAUC if partitions for at least one slot exist. The
bootmeth can then select the working slot.
Signed-off-by: Leonard Anderweit <l.anderweit@phytec.de>
Tested-by: Martin Schwan <m.schwan@phytec.de>
Only check if the root partition exists when scanning for the slots
partitions and not if the filesystem can be accessed. It is not needed
to access the filesystem of the root partition as it might not be
supported by u-boot or be encrypted.
Signed-off-by: Leonard Anderweit <l.anderweit@phytec.de>
Tested-by: Martin Schwan <m.schwan@phytec.de>
The nfsroot constructed as part of the default Analog Devices boot
strategy is missing a semicolon between the server ip and the root path
itself. This adds the missing semicolon.
Signed-off-by: Greg Malysa <malysagreg@gmail.com>
This patch fixes a boot failure on the AM64x EVM that was introduced when the do_board_detect function was removed during a refactoring.
It restores the do_board_detect function for the AM64x, AM62x, and AM65x boards to ensure the common board detection logic is executed correctly.
Fixes: 804b80288a ("board: am65x: Use generic AM6x board detection function")
Fixes: ce56e553c3 ("board: am64x: Use generic AM6x board detection functions")
Fixes: ff1b83c095 ("board: am62x: Add support for reading eeprom data")
Signed-off-by: Guillaume La Roque (TI.com) <glaroque@baylibre.com>
Currently, the bind callback of the driver namely am65_cpsw_nuss_bind()
registers all ethernet ports including the ones that have been disabled
in the device-tree. Since the ports that have been disabled are ought to
be ignored, fix the implementation to register only the enabled ports as
indicated by their 'status' in their respective device-tree node.
Fixes: 3943531a54 ("net: ti: am65-cpsw-nuss: Define bind method for CPSW driver")
Reported-by: Wadim Egorov <w.egorov@phytec.de>
Closes: https://patch.msgid.link/8b4ac072-125c-493b-b12a-f0a4e9d56e7e@phytec.de
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
The helper function "ti_pd_get()" is responsible for powering on a
domain if it is powered off. In the current implementation, if a power
domain is determined to be powered off - no prior users and the PDCTL
register indicates that the user desired state is OFF, then powering on
the domain constitutes setting 'PDCTL_STATE_ON' field of the PDCTL
register.
While the current implementation indeed requests the power domain to be
transition to the ON state, the helper function "ti_pd_get()" doesn't
verify that the power domain has 'transitioned' to the ON state before
returning to its caller. As a result, it is possible that the device(s)
belonging to the power domain may be accessed before it is truly powered
on, leading to a bus abort.
Fix this by waiting for the power domain to transition to the ON state
by using "ti_pd_wait()" before returning from "ti_pd_get()".
Fixes: 144464bd2c ("power: domain: Introduce driver for raw TI K3 PDs")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Tested-by: Hrushikesh Salunke <h-salunke@ti.com>
extension_get_list() will return NULL if there is no extension device.
Check for this situation.
Addresses-Coverity-ID: 638557 - Null pointer dereferences (NULL_RETURNS)
Fixes: 2d12958ee7 ("boot: Remove legacy extension board support")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Kory Maincent <kory.maincent@bootlin.com>
