The implementation of FW_LOADER requires CMDLINE to be enabled, and
expressses this. In order to not have to have every users also depends
on CMDLINE introduce SUPPORTS_FW_LOADER. This depends on CMDLINE and
ENV_SUPPORT and then we have all users depends on SUPPORTS_FW_LOADER.
Signed-off-by: Tom Rini <trini@konsulko.com>
In cases where phys_addr_t/phys_size_t is being printed, it's possible to
use tiny-printf-friendly %pap instead of %llx. For instance, in SPL, with
tiny-printf:
Before the patch:
fdtdec_setup_memory_banksize: DRAM Bank #0: start = 0xx, size = 0xx
After the patch:
fdtdec_setup_memory_banksize: DRAM Bank #0: start = 80000000, size = 40000000
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
Sync the command configuration across ADI SC5xx defconfigs by
enabling commands that were missing on some boards.
Signed-off-by: Ozan Durgut <ozan.durgut@analog.com>
The virtio spec clearly states in "3.1.1 Driver Requirements: Device
Initialization" the sequence a client has to follow after device reset.
Because u-boot resets here again, it also needs to set the "acknowledge"
bit again even if this was done in virtio_uclass_child_post_bind already
once before.
Signed-off-by: Christian Pötzsch <christian.poetzsch@kernkonzept.com>
Signed-off-by: Adam Lackorzynski <adam@l4re.org>
[trini: Add VIRTIO_CONFIG_S_ACKNOWLEDGE flag check to the test]
Signed-off-by: Tom Rini <trini@konsulko.com>
Meet Patel <meet.patel2@arm.com> says:
The virtio-rng test to verify effective handling of oversized return
buffers checks that an (undocumented) error is raised, instead of the
real concern, which is the surrounding buffer integrity following a rng
function call.
Update the test to check that the other contents of a buffer remain
unchanged instead of looking for an error code.
Link: https://lore.kernel.org/r/20260309165505.4001705-1-meet.patel2@arm.com
If extra random bytes are returned, truncate and use the requested number
instead of returning an error.
Signed-off-by: Kavin Gunasekara <kavin.gunasekara@arm.com>
Signed-off-by: Meet Patel <meet.patel2@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
The virtio-rng test to verify effective handling of oversized return
buffers checks that an (undocumented) error is raised, instead of the
real concern, which is the surrounding buffer integrity following a rng
function call.
Update the test to check that the other contents of a buffer remain
unchanged instead of looking for an error code.
Signed-off-by: Kavin Gunasekara <kavin.gunasekara@arm.com>
Signed-off-by: Meet Patel <meet.patel2@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
- MAINTAINERS patch for new MediaTek custodians
- MediaTek pinctrl fix to allow using GPIOs on recent platforms
- The rest is a second wave of MediaTek clock refactoring to remove
duplicate ways of doing the same thing.
Commit f4df9f53b7 ("pinctrl: mediatek: Bind gpio while binding pinctrl")
refactored pinctrl-mtk-common.c and the SoC-specific drivers to register
the gpiochip during the bind phase instead of probe. As part of this
change, each SoC driver must implement a bind callback.
The drivers recently added for mt8188, mt8189, mt8195 and mt8365 do not
define this callback, which prevents the gpiochip from being registered
properly.
Add the missing bind callback to these drivers.
Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260312-pinctrl-mtk-bind-gpio-v1-1-21b8968902ed@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Convert the mt8195 clock driver to use ext_clock_rates.
Now that we have the ext_clock_rates feature and also mux clock parents
have been converted to struct mtk_parent, we can remove the hack of
adding "missing" topckgen clocks. Instead we can use the proper parents.
The topckgen ID map is still needed though because the upstream
dt-bindings didn't use the conventional number ordering by clock type
for these.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260309-clk-mtk-mt8188-drop-extra-top-clocks-v1-2-6ee4743a8465@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Convert the mt8188 clock driver to use ext_clock_rates.
Now that we have the ext_clock_rates feature and also mux clock parents
have been converted to struct mtk_parent, we can remove the hack of
adding "missing" topckgen clocks. Instead we can use the proper parents.
The topckgen ID map is still needed though because the upstream
dt-bindings didn't use the conventional number ordering by clock type
for these.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260309-clk-mtk-mt8188-drop-extra-top-clocks-v1-1-6ee4743a8465@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Remove CLK_PARENT_MIXED and all dead code paths related to it.
All mux clocks have been converted to use struct mtk_parent (the
parent_flags field of the parent/parent_flags union). Use of this
struct was indicated by CLK_PARENT_MIXED. Now, this is always the case
and we can drop the flag and the union. All MUX_MIXED* macros are
change to use the equivalent MUX* macros since we no longer need to
set the flag.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-15-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Remove the CLK_BYPASS_XTAL flag completely.
It was a bit of a hack that was meant to handle mux clocks that had
mixed parents (e.g. XTAL and TOPCKGEN). The idea was that if you didn't
have CLK_XTAL as a parent, then you were supposed to add the
CLK_BYPASS_XTAL flag to the clock tree. There are likely a number of
drivers missing this since it is not intuitive.
In the meantime, we have introduced the CLK_PARENT_MIXED flag which
handles this more robustly. All of the affected drivers (the ones
without CLK_BYPASS_XTAL) have been updated to use CLK_PARENT_MIXED, so
the CLK_BYPASS_XTAL flag is no longer needed on other drivers.
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-14-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
Move the existing 16GB single-rank configuration to HW_CFG 0x03 and use
the previous HW_CFG 0x01 value for the new 16GB dual-rank configuration.
There is no hardware using the former 16GB single-rank configuration,
so reuse the HW_CFG value for the new 16GB dual-rank configuration,
which will be used in production.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
The memory controller configuration doesn't depend only on the memory
size, so refactor the code to use the memory configuration read from
the HW_CFG pin instead of the memory size.
Additionally, make use of one header file for all the memory
configurations.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Tom Rini
Alexander SverdlinandTom Rini
Ozan DurgutandTom Rini
Christian PötzschandTom Rini
Kavin GunasekaraandTom Rini
David Lechner
Julien StephanandDavid Lechner
Emanuele GhidoliandTom Rini