AMD/Xilinx/FPGA changes for v2026.04-rc1
xilinx:
- Sync ESRT with detected GUID
- DT cleanups
- Add logic for FRU information multiple times
- Enable more drivers pca9541, usb5744
- Enable more commands
- Cleanup firmware DT bindings
firmware:
- Add enhancement SMC format support
clk/versal:
- Various cleanups
- Add support for Versal Gen 2
i2c:
- cdns: Add timeout for RXDV status bit polling
spi:
- cadence: Remove cdns,is-dma DT property
- cadence: Remove duplicated return
- cadence_versal: Update flash reset delay
memtop:
- Update max memory reserved spaces to 64
Versal Gen 2:
- Aligned addresses with default memory map
- Add support for reading multiboot value
MB-V:
- Make SPL smaller
- Add support for SPI
- Move SPL to run out of BRAM
ZynqMP:
- Change default load address for BL32
U-Boot SPL should be executed from LMB BRAM, where its text
and data sections are located, while the heap and stack are
allocated in DDR memory.
Because on the MB-V platform, after power-up, reset, or FPGA
load, execution begins from LMB BRAM at address 0x0. Therefore,
the SPL binary must be placed in BRAM to support this boot flow.
Without it, the system can only be booted via JTAG.
A 64KB LMB BRAM region is allocated for U-Boot SPL, starting at
address 0x0. This region contains the SPL's text, data, and device
tree blob (DTB) sections. The .bss section is placed separately at
address 0xF000.
_________________0xFFFF
|BSS |
|_______________|0xF000
|DTB |
|_______________|
|Data |
|_______________|
|Text |
|_______________|0x0000
A 2MB region of DDR memory is allocated for U-Boot SPL, with the
heap starting at address 0x80000000 and the stack at 0x80200000.
_________________0xBFFFFFFF
|Full U-Boot |
|_______________|0x80400000
|Load FIT Image |
|_______________|0x80200000
|Stack |
|_______________|
|Heap |
|_______________|0x80000000
Since LMB BRAM is a limited resource with a practical size
constraint of 64KB - it cannot accommodate all runtime data.
Therefore, the heap and stack are placed at the beginning of
DDR memory to ensure sufficient space for SPL execution.
Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ed4a3618875869287b87b6b57fd55f4c6a36f046.1765206211.git.michal.simek@amd.com
Add a timeout mechanism when waiting for the RXDV (Receive Data
Valid) status bit to be set before reading data from the FIFO.
This prevents infinite polling loops that could occur if the
hardware doesn't respond as expected.
The timeout is set to 1000ms (CDNS_I2C_RXDV_TIMEOUT_MS) and uses
the wait_for_bit_le32() function to poll the status register. If
the timeout expires, an error code is returned.
Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Reviewed-by: Heiko Schocher <hs@nabladev.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ba53d57c179f3390b32bc6094f3ffb5f4cde931e.1764169953.git.michal.simek@amd.com
Remove xlnx-versal-power.h dt binding header because they should be moved
directly to folder where DTs are. In the Linux kernel this shift already
started by moving xlnx-zynqmp-clk.h to arch/arm64/boot/dts/xilinx/ folder.
U-Boot is using only one PD_DEV_OSPI constact which is moved to
zynqmp_firmware.h header. But handling around it should be fixed anyway
because no driver should be calling xilinx_pm_request() directly.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a0f0154ef89929517c3217efe025e8021a910b90.1764233963.git.michal.simek@amd.com
This pull request brings together a set of fixes and enhancements across
the SoCFPGA platform family, with a focus on MMC/SPL robustness, EFI
boot enablement, and Agilex5 SD/eMMC support.
CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/28776
Highlights:
*
SPL / MMC:
o
Fix Kconfig handling for
SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
o
Correct raw sector calculations and respect explicit sector values
when loading U-Boot from MMC in SPL
o
Adjust raw MMC loading logic for SoCFPGA platforms
*
EFI boot:
o
Permit EFI booting on SoCFPGA platforms
o
Disable mkeficapsule tool build for Arria 10 where unsupported
*
Agilex5:
o
Upgrade SDHCI controller from SD4HC to SD6HC
o
Enable MMC and Cadence SDHCI support in defconfig
o
Add dedicated eMMC device tree and defconfig for Agilex5 SoCDK
o
Revert incorrect GPIO configuration for SDIO_SEL
o
Refine U-Boot DT handling for SD and eMMC boot variants
*
SPI:
o
Allow disabling the DesignWare SPI driver in SPL via Kconfig
*
Board / configuration fixes:
o
Enable random MAC address generation for Cyclone V
o
Fix DE0-Nano-SoC boot configuration
o
Remove obsolete or conflicting options from multiple legacy
SoCFPGA defconfigs
Commit f369e1564c turned those off because the SPL size grew too
large. It also argued that those boards would never support EFI booting.
The former is correct, therefore keep CONFIG_SPL_EFI_PARTITION off.
CONFIG_SPL_ISO_PARTITION is default off. What is not correct is that
those boards are limited to legacy boot - you just need a hybrid
partition table to make both the bootrom and UEFI happy.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
By default, the de0_nano_soc used raw sectors, but the address became
invalid due the raw-mode refactorings. With loading via partition type
fixed, we can switch to that mode which is in line with what the ROM
loader does.
Fixes: 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
If U-Boot is located on MMC, SPL and U-Boot proper are glued together.
More precisely, SPL is stored 4 times. Take this and its padding into
account and adjust sector number via board_spl_mmc_get_uboot_raw_sector.
This allows loading from a partition, without the need to hard-code the
offset via SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
This function and the sector parameter evolved over the time. By now,
sector is influenced by spl_mmc_get_uboot_raw_sector which allows to
adjust the read sector with an offset that U-Boot proper may have inside
the partition. That used to work by chance if both
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR and
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION were enabled. Since
2a00d73d08 they are a choice, and we need to drop the condition to
maintain this feature.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Add SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE as condition where so
far SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION was enough - though often
by chance as both options were enabled.
Reorder the #ifdef blocks at this chance to follow the order in the
Kconfig menu.
Fixes: 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
We need to explicitly select SPL_LOAD_BLOCK when USE_PARTITION_TYPE is
enabled, just like the other choices do.
Fixes: 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
To reduce SPL size, make it possible to exclude designware driver,
while keeping it enabled in the main u-boot.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
mkeficapsule tool will be built by default if EFI_LOADER is set due to
commit b7a625b1ce ("tools: Build mkeficapsule tool by default if
EFI_LOADER is set").
This will cause compilation error on all our SoCFPGA devices, hence we will
be disabling this config as we do not utilize this tool.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Add dedicated device tree support for eMMC configuration on the Agilex5
SoCDK board, providing an alternative to the default SD card setup.
Changes to socfpga_agilex5.dtsi:
-
- Configure always-on regulator for stable eMMC operation
New device tree files:
- socfpga_agilex5_socdk_emmc.dts: Main eMMC device tree configuration
* Configure for eMMC operation (no-sd, no-sdio, non-removable)
* Set 8-bit bus width and high speed capability
* Add timing parameters for legacy and SDR modes
* Configure voltage supplies for eMMC power and I/O
* Add fixed 1.8V regulator for eMMC I/O voltage supply
- socfpga_agilex5_socdk_emmc-u-boot.dtsi: U-Boot specific additions
* Include common Agilex5 U-Boot configurations
* Set SPL boot order with eMMC support
* Enable necessary peripherals for boot-time operation
Configuration files:
- configs/socfpga_agilex5_emmc_defconfig: eMMC-specific configuration
* Inherit from base Agilex5 configuration
* Disable GPIO regulator support (not needed for fixed eMMC setup)
* Set eMMC-specific device tree
Build system integration:
- Add socfpga_agilex5_socdk_emmc.dtb target to Makefile
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Enable MMC support with Cadence SDHCI controller for both SPL and
U-Boot proper on Agilex5 platform to support SD card operations in
legacy and high speed timing modes.
MMC controller configuration:
- Enable MMC subsystem (CONFIG_MMC=y, CONFIG_DM_MMC=y)
- Add Cadence SDHCI controller support (CONFIG_MMC_SDHCI_CADENCE=y)
- Enable SDHCI with ADMA support for better performance
- Add MMC command support for user interaction
SPL configuration:
- Enable MMC support in SPL (CONFIG_SPL_DM_MMC=y)
- Add SDHCI ADMA support in SPL (CONFIG_SPL_MMC_SDHCI_ADMA=y)
- Enable GPIO support in SPL (CONFIG_SPL_DWAPB_GPIO=y)
Voltage regulator support:
- Add device model regulator framework (CONFIG_DM_REGULATOR=y)
- Enable fixed voltage regulator support for card power
- Add GPIO-controlled regulator for I/O voltage switching
- Include regulator support in SPL for early initialization
These changes enable SD card functionality with legacy and high speed
timing modes, providing proper voltage regulation and GPIO control
for the Agilex5 SoCDK platform.
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Upgrade the SDHCI Cadence controller from SD4HC to SD6HC for Agilex5
platform to support the newer controller version with enhanced features.
Key changes:
- Remove combophy0 node and associated references as SD6HC doesn't require
separate PHY configuration node
- Upgrade MMC controller compatible from "cdns,sd4hc" to "cdns,sd6hc"
- Add Agilex5-specific compatible string "altr,agilex5-sd6hc" for
platform-specific optimizations
Hardware configuration updates:
- Add voltage regulator support:
* sd_emmc_power: Fixed 3.3V regulator for card power supply
* sd_io_1v8_reg: GPIO-controlled regulator for 1.8V/3.3V I/O switching
- Configure proper reset control with named resets including combophy
reset
- Add GPIO control via portb pin 3 for voltage switching
SD card operation:
- Configure for SD card specific operation (no-mmc, cap-sd-highspeed)
- Set maximum frequency to 200MHz
- Configure timing parameters for SD modes:
* Default Speed (DS) and UHS-I SDR12 mode timing:
* High Speed and UHS-I SDR25 mode timing:
- Add PHY timing delays for optimal signal integrity
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Remove GPIO hog configuration for SDIO_SEL pin as it is now handled
through the voltage regulator framework for SD ultra high speed mode
support. The GPIO pin 3 on portb controller is used to control the
level shifter for SD card I/O voltage switching.
The regulator-based approach provides proper voltage switching control
for UHS-I modes (SDR50, SDR104) while maintaining compatibility with
the MMC subsystem's voltage switching protocols.
This reverts commit b0dbc9fcb7.
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Enable CONFIG_NET_RANDOM_ETHADDR to allow U-Boot to assign a random MAC
address during Ethernet initialization when a valid MAC is not programmed
in hardware.
This avoids network initialization failures and MAC address conflicts,
especially on boards used for development or shipped without a
factory-programmed MAC.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Quentin Schulz <foss+uboot@0leil.net> says:
This does a bit of "cleanup" by reusing constants for some FIT
properties instead of having the same string in multiple places.
Additionally, this adds a new constant for the compatible property in
FIT configuration nodes[1] which is useful for FIT images with multiple
FIT configuration nodes to support multiple devices in the same blob.
U-Boot will try to figure out which node to select based on that
compatible[2].
However, if this property is missing (and the first blob in the fdt
property of the configuration node is uncompressed), the compatible from
the root node of the associated kernel FDT will be used for the
autoselection mechanism. For now, I only print the property if it
exists, but maybe it'd make sense to expose the fallback one if it's
missing. I guess we can implement that later on if desired.
[1] https://fitspec.osfw.foundation/#optional-properties compatible paragraph
[2] https://fitspec.osfw.foundation/#select-a-configuration-to-boot
Link: https://lore.kernel.org/r/20251203-fit-compat-v2-0-0fea56f23809@cherry.de
Fit conf node may have a compatible property[1] which stores the
compatible of the first blob in the fdt property of the node. This can
be used to automatically select the proper conf node based on the
compatible from the running U-Boot (matching the former's compatible
with the latter)[2].
This brings the ability to mkimage/dumpimage to print the compatibles of
the configuration node(s). U-Boot CLI commands such as iminfo also see
this addition to their output.
[1] https://fitspec.osfw.foundation/#optional-properties compatible paragraph
[2] https://fitspec.osfw.foundation/#select-a-configuration-to-boot
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Fit conf node may have a compatible property[1] which stores the root
compatible of the first blob in the fdt property of the node. This can
be used to automatically select the proper conf node based on the
compatible from the running U-Boot (matching the former's compatible
with the latter)[2].
This adds (and uses) this constant for FIT node parsing.
Note that this property may also appear in fpga image nodes[3] but that
isn't done in this commit.
[1] https://fitspec.osfw.foundation/#optional-properties compatible paragraph
[2] https://fitspec.osfw.foundation/#select-a-configuration-to-boot
[3] https://fitspec.osfw.foundation/#images-node 2.3.2 Conditionally mandatory property
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Some FIT image properties have their string represented in
include/image.h via constants. FIT_ALGO_PROP does exist and would fit the
bill so let's use it instead of using a hardcoded string.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Some properties have their string represented in include/image.h via
constants, so let's use those constants instead of using a hardcoded
string.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
We are trying to get rid of the legacy LED API and this is one of the
last users.
As far as I understood from the code, only one LED is controllable and
it is a GPIO led. When initializing the LED, it is always enabled
regardless of the passed argument, same for the mask.
In addition, the LED is used as a BOOT LED.
To keep the same behavior, a GPIO driver should be written, then add a
gpio-leds node which makes use of a GPIO from said driver, add the
/options/u-boot/boot-led property pointing at this new GPIO LED node and
then enable CONFIG_LED as well as CONFIG_LED_BOOT. This should result in
the same behavior using the modern framework.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
The usage of fdt_fixup_reserved is repeated for ATF and OP-TEE for
multiple platforms, this patch creates a single fdt API for fixing up
the reserved-memory node with added error handling.
All k3 platforms already share a common tispl template which ensures
binaries are loaded as per the respective CONFIG_*_LOAD_ADDR. And the
provided new_size for the fixup is overridden by the size from fdt node
anyways. This allows for safe abstraction of the reserved memory fixups
for all current platforms.
fdt_fixup_reserved now abstracts the ATF and OP-TEE fixups by calling
the renamed static fdt_fixup_reserved_memory function with the required
parameters.
Signed-off-by: Anshul Dalal <anshuld@ti.com>
If func->pins could not be allocated, one must also free
func variable that was allocated previously.
Signed-off-by: Francois Berder <fberder@outlook.fr>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
