The TF-A DRAM bank setup currently assumes that the number of
banks reported by TF-A matches the number of entries available in
gd->bd->bi_dram[]. Limit the loop by CONFIG_NR_DRAM_BANKS so that
a platform with fewer configured DRAM banks does not write past the
array.
The reserved RAM setup also checks higher DRAM banks before falling
back to bank 0. When a higher bank is empty and board_reserve_ram_top()
returns 0, the old test succeeds for a zero-sized bank. This can set
gd->arch.resv_ram to 0.
On systems with CONFIG_GIC_V3_ITS this value is later used by
ls_gic_rd_tables_init() to place the GIC LPI tables:
gd->arch.resv_ram - GIC_LPI_SIZE
If gd->arch.resv_ram is 0, the subtraction underflows and the GIC LPI
tables are placed at an invalid high address.
Skip empty banks when selecting the reserved RAM area and fail GIC LPI
table setup if no reserved RAM address was established.
This fixes LS1028A systems with 2 GiB of RAM, where TF-A reports only
one populated DRAM bank.
Tested on an LS1028ARDB with TF-A modified to report 2 GiB of RAM, and
on a custom LS1028A-based board equipped with 2 GiB of RAM.
Signed-off-by: Patryk Biel <pbiel7@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Allow for a proper configuration of CFI flash banks avaialble on the vexpress_ca9x4
board. Without this option, the CFI flash incorrectly detects that the board has two
banks of 32MB flash devices, while in reality, the board provides
two flash banks, each with 64MB size. As a result, it becomes impossible to e.g. to
save u-boot env in flash. According to device tree for this board and
its implementation in QEMU, the CFI width should be set to 32 bits.
After applying this fix, CFI flash will correctly detect both flash
banks each with a size of 64MB. As as result the functionality of e.g. saving u-boot
env will work correctly.
Tested on QEMU 6.2.0.
Cc: Kristian Amlie <kristian.amlie@northern.tech>
Signed-off-by: Patryk Biel <pbiel7@gmail.com>
Reviewed-by: Kristian Amlie <kristian.amlie@northern.tech>
Patryk BielandPeng Fan
