mmc: mtk-sd: use GENMASK and FIELD macros
Replace separate mask and shift definitions with GENMASK and FIELD_* macros for better readability and maintainability. All macros ending in _M have the suffix dropped. The value remains the same but is now generated with GENMASK. All macros ending in _S are removed and their uses replaced with FIELD_PREP and FIELD_GET macros. Signed-off-by: David Lechner <dlechner@baylibre.com> Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
David Lechner
Peng Fan
+151
-206
@@ -16,6 +16,7 @@
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#include <asm/gpio.h>
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#include <dm/device_compat.h>
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#include <dm/pinctrl.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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@@ -23,15 +24,11 @@
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/* MSDC_CFG */
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#define MSDC_CFG_HS400_CK_MODE_EXT BIT(22)
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#define MSDC_CFG_CKMOD_EXT_M 0x300000
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#define MSDC_CFG_CKMOD_EXT_S 20
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#define MSDC_CFG_CKDIV_EXT_M 0xfff00
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#define MSDC_CFG_CKDIV_EXT_S 8
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#define MSDC_CFG_CKMOD_EXT GENMASK(21, 20)
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#define MSDC_CFG_CKDIV_EXT GENMASK(19, 8)
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#define MSDC_CFG_HS400_CK_MODE BIT(18)
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#define MSDC_CFG_CKMOD_M 0x30000
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#define MSDC_CFG_CKMOD_S 16
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#define MSDC_CFG_CKDIV_M 0xff00
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#define MSDC_CFG_CKDIV_S 8
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#define MSDC_CFG_CKMOD GENMASK(17, 16)
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#define MSDC_CFG_CKDIV GENMASK(15, 8)
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#define MSDC_CFG_CKSTB BIT(7)
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#define MSDC_CFG_PIO BIT(3)
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#define MSDC_CFG_RST BIT(2)
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@@ -45,8 +42,7 @@
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/* MSDC_PS */
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#define MSDC_PS_DAT0 BIT(16)
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#define MSDC_PS_CDDBCE_M 0xf000
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#define MSDC_PS_CDDBCE_S 12
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#define MSDC_PS_CDDBCE GENMASK(15, 12)
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#define MSDC_PS_CDSTS BIT(1)
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#define MSDC_PS_CDEN BIT(0)
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@@ -63,30 +59,22 @@
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/* MSDC_FIFOCS */
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#define MSDC_FIFOCS_CLR BIT(31)
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#define MSDC_FIFOCS_TXCNT_M 0xff0000
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#define MSDC_FIFOCS_TXCNT_S 16
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#define MSDC_FIFOCS_RXCNT_M 0xff
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#define MSDC_FIFOCS_RXCNT_S 0
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#define MSDC_FIFOCS_TXCNT GENMASK(23, 16)
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#define MSDC_FIFOCS_RXCNT GENMASK(7, 0)
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/* #define SDC_CFG */
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#define SDC_CFG_DTOC_M 0xff000000
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#define SDC_CFG_DTOC_S 24
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#define SDC_CFG_DTOC GENMASK(31, 24)
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#define SDC_CFG_SDIOIDE BIT(20)
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#define SDC_CFG_SDIO BIT(19)
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#define SDC_CFG_BUSWIDTH_M 0x30000
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#define SDC_CFG_BUSWIDTH_S 16
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#define SDC_CFG_BUSWIDTH GENMASK(17, 16)
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/* SDC_CMD */
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#define SDC_CMD_BLK_LEN_M 0xfff0000
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#define SDC_CMD_BLK_LEN_S 16
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#define SDC_CMD_BLK_LEN GENMASK(27, 16)
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#define SDC_CMD_STOP BIT(14)
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#define SDC_CMD_WR BIT(13)
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#define SDC_CMD_DTYPE_M 0x1800
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#define SDC_CMD_DTYPE_S 11
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#define SDC_CMD_RSPTYP_M 0x380
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#define SDC_CMD_RSPTYP_S 7
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#define SDC_CMD_CMD_M 0x3f
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#define SDC_CMD_CMD_S 0
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#define SDC_CMD_DTYPE GENMASK(12, 11)
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#define SDC_CMD_RSPTYP GENMASK(9, 7)
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#define SDC_CMD_CMD GENMASK(5, 0)
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/* SDC_STS */
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#define SDC_STS_CMDBUSY BIT(1)
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@@ -96,102 +84,73 @@
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#define SDC_RX_ENHANCE_EN BIT(20)
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/* PATCH_BIT0 */
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#define MSDC_INT_DAT_LATCH_CK_SEL_M 0x380
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#define MSDC_INT_DAT_LATCH_CK_SEL_S 7
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#define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7)
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/* PATCH_BIT1 */
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#define MSDC_PB1_STOP_DLY_M 0xf00
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#define MSDC_PB1_STOP_DLY_S 8
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#define MSDC_PB1_STOP_DLY GENMASK(11, 8)
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/* PATCH_BIT2 */
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#define MSDC_PB2_CRCSTSENSEL_M 0xe0000000
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#define MSDC_PB2_CRCSTSENSEL_S 29
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#define MSDC_PB2_CRCSTSENSEL GENMASK(31, 29)
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#define MSDC_PB2_CFGCRCSTS BIT(28)
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#define MSDC_PB2_RESPSTSENSEL_M 0x70000
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#define MSDC_PB2_RESPSTSENSEL_S 16
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#define MSDC_PB2_RESPSTSENSEL GENMASK(18, 16)
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#define MSDC_PB2_CFGRESP BIT(15)
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#define MSDC_PB2_RESPWAIT_M 0x0c
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#define MSDC_PB2_RESPWAIT_S 2
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#define MSDC_PB2_RESPWAIT GENMASK(3, 2)
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/* MSDC_PAD_CTRL0 */
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#define MSDC_PAD_CTRL0_CLKRDSEL_M 0xff000000
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#define MSDC_PAD_CTRL0_CLKRDSEL_S 24
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#define MSDC_PAD_CTRL0_CLKRDSEL GENMASK(31, 24)
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#define MSDC_PAD_CTRL0_CLKTDSEL BIT(20)
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#define MSDC_PAD_CTRL0_CLKIES BIT(19)
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#define MSDC_PAD_CTRL0_CLKSMT BIT(18)
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#define MSDC_PAD_CTRL0_CLKPU BIT(17)
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#define MSDC_PAD_CTRL0_CLKPD BIT(16)
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#define MSDC_PAD_CTRL0_CLKSR BIT(8)
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#define MSDC_PAD_CTRL0_CLKDRVP_M 0x70
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#define MSDC_PAD_CTRL0_CLKDRVP_S 4
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#define MSDC_PAD_CTRL0_CLKDRVN_M 0x7
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#define MSDC_PAD_CTRL0_CLKDRVN_S 0
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#define MSDC_PAD_CTRL0_CLKDRVP GENMASK(6, 4)
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#define MSDC_PAD_CTRL0_CLKDRVN GENMASK(2, 0)
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/* MSDC_PAD_CTRL1 */
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#define MSDC_PAD_CTRL1_CMDRDSEL_M 0xff000000
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#define MSDC_PAD_CTRL1_CMDRDSEL_S 24
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#define MSDC_PAD_CTRL1_CMDRDSEL GENMASK(31, 24)
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#define MSDC_PAD_CTRL1_CMDTDSEL BIT(20)
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#define MSDC_PAD_CTRL1_CMDIES BIT(19)
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#define MSDC_PAD_CTRL1_CMDSMT BIT(18)
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#define MSDC_PAD_CTRL1_CMDPU BIT(17)
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#define MSDC_PAD_CTRL1_CMDPD BIT(16)
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#define MSDC_PAD_CTRL1_CMDSR BIT(8)
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#define MSDC_PAD_CTRL1_CMDDRVP_M 0x70
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#define MSDC_PAD_CTRL1_CMDDRVP_S 4
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#define MSDC_PAD_CTRL1_CMDDRVN_M 0x7
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#define MSDC_PAD_CTRL1_CMDDRVN_S 0
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#define MSDC_PAD_CTRL1_CMDDRVP GENMASK(6, 4)
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#define MSDC_PAD_CTRL1_CMDDRVN GENMASK(2, 0)
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/* MSDC_PAD_CTRL2 */
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#define MSDC_PAD_CTRL2_DATRDSEL_M 0xff000000
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#define MSDC_PAD_CTRL2_DATRDSEL_S 24
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#define MSDC_PAD_CTRL2_DATRDSEL GENMASK(31, 24)
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#define MSDC_PAD_CTRL2_DATTDSEL BIT(20)
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#define MSDC_PAD_CTRL2_DATIES BIT(19)
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#define MSDC_PAD_CTRL2_DATSMT BIT(18)
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#define MSDC_PAD_CTRL2_DATPU BIT(17)
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#define MSDC_PAD_CTRL2_DATPD BIT(16)
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#define MSDC_PAD_CTRL2_DATSR BIT(8)
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#define MSDC_PAD_CTRL2_DATDRVP_M 0x70
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#define MSDC_PAD_CTRL2_DATDRVP_S 4
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#define MSDC_PAD_CTRL2_DATDRVN_M 0x7
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#define MSDC_PAD_CTRL2_DATDRVN_S 0
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#define MSDC_PAD_CTRL2_DATDRVP GENMASK(6, 4)
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#define MSDC_PAD_CTRL2_DATDRVN GENMASK(2, 0)
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/* PAD_TUNE */
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#define MSDC_PAD_TUNE_CLKTDLY_M 0xf8000000
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#define MSDC_PAD_TUNE_CLKTDLY_S 27
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#define MSDC_PAD_TUNE_CMDRRDLY_M 0x7c00000
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#define MSDC_PAD_TUNE_CMDRRDLY_S 22
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#define MSDC_PAD_TUNE_CLKTDLY GENMASK(31, 27)
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#define MSDC_PAD_TUNE_CMDRRDLY GENMASK(26, 22)
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#define MSDC_PAD_TUNE_CMD_SEL BIT(21)
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#define MSDC_PAD_TUNE_CMDRDLY_M 0x1f0000
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#define MSDC_PAD_TUNE_CMDRDLY_S 16
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#define MSDC_PAD_TUNE_CMDRDLY GENMASK(20, 16)
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#define MSDC_PAD_TUNE_RXDLYSEL BIT(15)
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#define MSDC_PAD_TUNE_RD_SEL BIT(13)
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#define MSDC_PAD_TUNE_DATRRDLY_M 0x1f00
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#define MSDC_PAD_TUNE_DATRRDLY_S 8
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#define MSDC_PAD_TUNE_DATWRDLY_M 0x1f
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#define MSDC_PAD_TUNE_DATWRDLY_S 0
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#define MSDC_PAD_TUNE_DATRRDLY GENMASK(12, 8)
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#define MSDC_PAD_TUNE_DATWRDLY GENMASK(4, 0)
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#define PAD_CMD_TUNE_RX_DLY3 0x3E
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#define PAD_CMD_TUNE_RX_DLY3_S 1
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#define PAD_CMD_TUNE_RX_DLY3 GENMASK(5, 1)
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/* PAD_TUNE0 */
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#define MSDC_PAD_TUNE0_DAT0RDDLY_M 0x1f000000
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#define MSDC_PAD_TUNE0_DAT0RDDLY_S 24
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#define MSDC_PAD_TUNE0_DAT1RDDLY_M 0x1f0000
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#define MSDC_PAD_TUNE0_DAT1RDDLY_S 16
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#define MSDC_PAD_TUNE0_DAT2RDDLY_M 0x1f00
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#define MSDC_PAD_TUNE0_DAT2RDDLY_S 8
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#define MSDC_PAD_TUNE0_DAT3RDDLY_M 0x1f
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#define MSDC_PAD_TUNE0_DAT3RDDLY_S 0
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#define MSDC_PAD_TUNE0_DAT0RDDLY GENMASK(28, 24)
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#define MSDC_PAD_TUNE0_DAT1RDDLY GENMASK(20, 16)
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#define MSDC_PAD_TUNE0_DAT2RDDLY GENMASK(12, 8)
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#define MSDC_PAD_TUNE0_DAT3RDDLY GENMASK(4, 0)
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/* PAD_TUNE1 */
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#define MSDC_PAD_TUNE1_DAT4RDDLY_M 0x1f000000
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#define MSDC_PAD_TUNE1_DAT4RDDLY_S 24
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#define MSDC_PAD_TUNE1_DAT5RDDLY_M 0x1f0000
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#define MSDC_PAD_TUNE1_DAT5RDDLY_S 16
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#define MSDC_PAD_TUNE1_DAT6RDDLY_M 0x1f00
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#define MSDC_PAD_TUNE1_DAT6RDDLY_S 8
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#define MSDC_PAD_TUNE1_DAT7RDDLY_M 0x1f
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#define MSDC_PAD_TUNE1_DAT7RDDLY_S 0
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#define MSDC_PAD_TUNE1_DAT4RDDLY GENMASK(28, 24)
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#define MSDC_PAD_TUNE1_DAT5RDDLY GENMASK(20, 16)
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#define MSDC_PAD_TUNE1_DAT6RDDLY GENMASK(12, 8)
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#define MSDC_PAD_TUNE1_DAT7RDDLY GENMASK(4, 0)
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/* EMMC50_CFG0 */
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#define EMMC50_CFG_CFCSTS_SEL BIT(4)
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@@ -203,21 +162,19 @@
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/* EMMC_TOP_CONTROL mask */
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#define PAD_RXDLY_SEL BIT(0)
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#define DELAY_EN BIT(1)
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#define PAD_DAT_RD_RXDLY2 (0x1f << 2)
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#define PAD_DAT_RD_RXDLY (0x1f << 7)
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#define PAD_DAT_RD_RXDLY_S 7
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#define PAD_DAT_RD_RXDLY2 GENMASK(6, 2)
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#define PAD_DAT_RD_RXDLY GENMASK(11, 7)
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#define PAD_DAT_RD_RXDLY2_SEL BIT(12)
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#define PAD_DAT_RD_RXDLY_SEL BIT(13)
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#define DATA_K_VALUE_SEL BIT(14)
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#define SDC_RX_ENH_EN BIT(15)
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/* EMMC_TOP_CMD mask */
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#define PAD_CMD_RXDLY2 (0x1f << 0)
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#define PAD_CMD_RXDLY (0x1f << 5)
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#define PAD_CMD_RXDLY_S 5
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#define PAD_CMD_RXDLY2 GENMASK(4, 0)
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#define PAD_CMD_RXDLY GENMASK(9, 5)
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#define PAD_CMD_RD_RXDLY2_SEL BIT(10)
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#define PAD_CMD_RD_RXDLY_SEL BIT(11)
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#define PAD_CMD_TX_DLY (0x1f << 12)
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#define PAD_CMD_TX_DLY GENMASK(16, 12)
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/* SDC_CFG_BUSWIDTH */
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#define MSDC_BUS_1BITS 0x0
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@@ -428,14 +385,12 @@ static void msdc_fifo_clr(struct msdc_host *host)
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static u32 msdc_fifo_rx_bytes(struct msdc_host *host)
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{
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return (readl(&host->base->msdc_fifocs) &
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MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S;
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return FIELD_GET(MSDC_FIFOCS_RXCNT, readl(&host->base->msdc_fifocs));
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}
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static u32 msdc_fifo_tx_bytes(struct msdc_host *host)
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{
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return (readl(&host->base->msdc_fifocs) &
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MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S;
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return FIELD_GET(MSDC_FIFOCS_TXCNT, readl(&host->base->msdc_fifocs));
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}
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static u32 msdc_cmd_find_resp(struct msdc_host *host, struct mmc_cmd *cmd)
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@@ -504,10 +459,10 @@ static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
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blocksize = data->blocksize;
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}
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rawcmd |= ((opcode << SDC_CMD_CMD_S) & SDC_CMD_CMD_M) |
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((resp_type << SDC_CMD_RSPTYP_S) & SDC_CMD_RSPTYP_M) |
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((blocksize << SDC_CMD_BLK_LEN_S) & SDC_CMD_BLK_LEN_M) |
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((dtype << SDC_CMD_DTYPE_S) & SDC_CMD_DTYPE_M);
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rawcmd |= FIELD_PREP(SDC_CMD_CMD, opcode) |
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FIELD_PREP(SDC_CMD_RSPTYP, resp_type) |
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FIELD_PREP(SDC_CMD_BLK_LEN, blocksize) |
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FIELD_PREP(SDC_CMD_DTYPE, dtype);
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if (opcode == MMC_CMD_STOP_TRANSMISSION)
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rawcmd |= SDC_CMD_STOP;
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@@ -590,10 +545,8 @@ static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd,
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if (!msdc_cmd_is_ready(host))
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return -EIO;
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if ((readl(&host->base->msdc_fifocs) &
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MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S ||
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(readl(&host->base->msdc_fifocs) &
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MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S) {
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if (FIELD_GET(MSDC_FIFOCS_TXCNT, readl(&host->base->msdc_fifocs)) ||
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FIELD_GET(MSDC_FIFOCS_RXCNT, readl(&host->base->msdc_fifocs))) {
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pr_err("TX/RX FIFO non-empty before start of IO. Reset\n");
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msdc_reset_hw(host);
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}
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@@ -814,37 +767,35 @@ static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
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/* unit is 1048576 sclk cycles */
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timeout = (timeout + (0x1 << shift) - 1) >> shift;
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if (host->dev_comp->clk_div_bits == 8)
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mode = (readl(&host->base->msdc_cfg) &
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MSDC_CFG_CKMOD_M) >> MSDC_CFG_CKMOD_S;
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mode = FIELD_GET(MSDC_CFG_CKMOD, readl(&host->base->msdc_cfg));
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else
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mode = (readl(&host->base->msdc_cfg) &
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MSDC_CFG_CKMOD_EXT_M) >> MSDC_CFG_CKMOD_EXT_S;
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mode = FIELD_GET(MSDC_CFG_CKMOD_EXT, readl(&host->base->msdc_cfg));
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/* DDR mode will double the clk cycles for data timeout */
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timeout = mode >= 2 ? timeout * 2 : timeout;
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timeout = timeout > 1 ? timeout - 1 : 0;
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timeout = timeout > 255 ? 255 : timeout;
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}
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clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
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timeout << SDC_CFG_DTOC_S);
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clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC,
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FIELD_PREP(SDC_CFG_DTOC, timeout));
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}
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static void msdc_set_buswidth(struct msdc_host *host, u32 width)
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{
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u32 val = readl(&host->base->sdc_cfg);
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val &= ~SDC_CFG_BUSWIDTH_M;
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val &= ~SDC_CFG_BUSWIDTH;
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switch (width) {
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default:
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case 1:
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val |= (MSDC_BUS_1BITS << SDC_CFG_BUSWIDTH_S);
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val |= FIELD_PREP(SDC_CFG_BUSWIDTH, MSDC_BUS_1BITS);
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break;
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case 4:
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val |= (MSDC_BUS_4BITS << SDC_CFG_BUSWIDTH_S);
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val |= FIELD_PREP(SDC_CFG_BUSWIDTH, MSDC_BUS_4BITS);
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break;
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case 8:
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val |= (MSDC_BUS_8BITS << SDC_CFG_BUSWIDTH_S);
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val |= FIELD_PREP(SDC_CFG_BUSWIDTH, MSDC_BUS_8BITS);
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break;
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}
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@@ -918,18 +869,17 @@ static void msdc_set_mclk(struct udevice *dev,
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clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
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if (host->dev_comp->clk_div_bits == 8) {
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div = min(div, (u32)(MSDC_CFG_CKDIV_M >> MSDC_CFG_CKDIV_S));
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div = min(div, (u32)FIELD_MAX(MSDC_CFG_CKDIV));
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clrsetbits_le32(&host->base->msdc_cfg,
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MSDC_CFG_CKMOD_M | MSDC_CFG_CKDIV_M,
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(mode << MSDC_CFG_CKMOD_S) |
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(div << MSDC_CFG_CKDIV_S));
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MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
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FIELD_PREP(MSDC_CFG_CKMOD, mode) |
|
||||
FIELD_PREP(MSDC_CFG_CKDIV, div));
|
||||
} else {
|
||||
div = min(div, (u32)(MSDC_CFG_CKDIV_EXT_M >>
|
||||
MSDC_CFG_CKDIV_EXT_S));
|
||||
div = min(div, (u32)FIELD_MAX(MSDC_CFG_CKDIV_EXT));
|
||||
clrsetbits_le32(&host->base->msdc_cfg,
|
||||
MSDC_CFG_CKMOD_EXT_M | MSDC_CFG_CKDIV_EXT_M,
|
||||
(mode << MSDC_CFG_CKMOD_EXT_S) |
|
||||
(div << MSDC_CFG_CKDIV_EXT_S));
|
||||
MSDC_CFG_CKMOD_EXT | MSDC_CFG_CKDIV_EXT,
|
||||
FIELD_PREP(MSDC_CFG_CKMOD_EXT, mode) |
|
||||
FIELD_PREP(MSDC_CFG_CKDIV_EXT, div));
|
||||
}
|
||||
|
||||
readl_poll_timeout(&host->base->msdc_cfg, reg,
|
||||
@@ -1085,10 +1035,10 @@ static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
|
||||
|
||||
if (host->top_base)
|
||||
clrsetbits_le32(&host->top_base->emmc_top_cmd, PAD_CMD_RXDLY,
|
||||
value << PAD_CMD_RXDLY_S);
|
||||
FIELD_PREP(PAD_CMD_RXDLY, value));
|
||||
else
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
|
||||
value << MSDC_PAD_TUNE_CMDRDLY_S);
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY,
|
||||
FIELD_PREP(MSDC_PAD_TUNE_CMDRDLY, value));
|
||||
}
|
||||
|
||||
static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
|
||||
@@ -1100,10 +1050,10 @@ static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
|
||||
|
||||
if (host->top_base)
|
||||
clrsetbits_le32(&host->top_base->emmc_top_control,
|
||||
PAD_DAT_RD_RXDLY, value << PAD_DAT_RD_RXDLY_S);
|
||||
PAD_DAT_RD_RXDLY, FIELD_PREP(PAD_DAT_RD_RXDLY, value));
|
||||
else
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
|
||||
value << MSDC_PAD_TUNE_DATRRDLY_S);
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY,
|
||||
FIELD_PREP(MSDC_PAD_TUNE_DATRRDLY, value));
|
||||
}
|
||||
|
||||
static int hs400_tune_response(struct udevice *dev, u32 opcode)
|
||||
@@ -1122,9 +1072,9 @@ static int hs400_tune_response(struct udevice *dev, u32 opcode)
|
||||
|
||||
if (mmc->selected_mode == MMC_HS_200 ||
|
||||
mmc->selected_mode == UHS_SDR104)
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
|
||||
host->hs200_cmd_int_delay <<
|
||||
MSDC_PAD_TUNE_CMDRRDLY_S);
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
|
||||
FIELD_PREP(MSDC_PAD_TUNE_CMDRRDLY,
|
||||
host->hs200_cmd_int_delay));
|
||||
|
||||
if (host->r_smpl)
|
||||
clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
|
||||
@@ -1133,7 +1083,7 @@ static int hs400_tune_response(struct udevice *dev, u32 opcode)
|
||||
|
||||
for (i = 0; i < PAD_DELAY_MAX; i++) {
|
||||
clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
|
||||
i << PAD_CMD_TUNE_RX_DLY3_S);
|
||||
FIELD_PREP(PAD_CMD_TUNE_RX_DLY3, i));
|
||||
|
||||
for (j = 0; j < 3; j++) {
|
||||
cmd_err = mmc_send_tuning(mmc, opcode);
|
||||
@@ -1148,8 +1098,7 @@ static int hs400_tune_response(struct udevice *dev, u32 opcode)
|
||||
|
||||
final_cmd_delay = get_best_delay(dev, host, cmd_delay);
|
||||
clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
|
||||
final_cmd_delay.final_phase <<
|
||||
PAD_CMD_TUNE_RX_DLY3_S);
|
||||
FIELD_PREP(PAD_CMD_TUNE_RX_DLY3, final_cmd_delay.final_phase));
|
||||
final_delay = final_cmd_delay.final_phase;
|
||||
|
||||
dev_info(dev, "Final cmd pad delay: %x\n", final_delay);
|
||||
@@ -1175,15 +1124,15 @@ static int msdc_tune_response(struct udevice *dev, u32 opcode)
|
||||
|
||||
if (mmc->selected_mode == MMC_HS_200 ||
|
||||
mmc->selected_mode == UHS_SDR104)
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
|
||||
host->hs200_cmd_int_delay <<
|
||||
MSDC_PAD_TUNE_CMDRRDLY_S);
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
|
||||
FIELD_PREP(MSDC_PAD_TUNE_CMDRRDLY,
|
||||
host->hs200_cmd_int_delay));
|
||||
|
||||
clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
|
||||
|
||||
for (i = 0; i < PAD_DELAY_MAX; i++) {
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
|
||||
i << MSDC_PAD_TUNE_CMDRDLY_S);
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY,
|
||||
FIELD_PREP(MSDC_PAD_TUNE_CMDRDLY, i));
|
||||
|
||||
for (j = 0; j < 3; j++) {
|
||||
cmd_err = mmc_send_tuning(mmc, opcode);
|
||||
@@ -1204,8 +1153,8 @@ static int msdc_tune_response(struct udevice *dev, u32 opcode)
|
||||
|
||||
setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
|
||||
for (i = 0; i < PAD_DELAY_MAX; i++) {
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
|
||||
i << MSDC_PAD_TUNE_CMDRDLY_S);
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY,
|
||||
FIELD_PREP(MSDC_PAD_TUNE_CMDRDLY, i));
|
||||
|
||||
for (j = 0; j < 3; j++) {
|
||||
cmd_err = mmc_send_tuning(mmc, opcode);
|
||||
@@ -1224,15 +1173,13 @@ skip_fall:
|
||||
final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
|
||||
if (final_maxlen == final_rise_delay.maxlen) {
|
||||
clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
|
||||
final_rise_delay.final_phase <<
|
||||
MSDC_PAD_TUNE_CMDRDLY_S);
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY,
|
||||
FIELD_PREP(MSDC_PAD_TUNE_CMDRDLY, final_rise_delay.final_phase));
|
||||
final_delay = final_rise_delay.final_phase;
|
||||
} else {
|
||||
setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
|
||||
final_fall_delay.final_phase <<
|
||||
MSDC_PAD_TUNE_CMDRDLY_S);
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY,
|
||||
FIELD_PREP(MSDC_PAD_TUNE_CMDRDLY, final_fall_delay.final_phase));
|
||||
final_delay = final_fall_delay.final_phase;
|
||||
}
|
||||
|
||||
@@ -1240,9 +1187,8 @@ skip_fall:
|
||||
goto skip_internal;
|
||||
|
||||
for (i = 0; i < PAD_DELAY_MAX; i++) {
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
|
||||
i << MSDC_PAD_TUNE_CMDRRDLY_S);
|
||||
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
|
||||
FIELD_PREP(MSDC_PAD_TUNE_CMDRRDLY, i));
|
||||
cmd_err = mmc_send_tuning(mmc, opcode);
|
||||
if (!cmd_err)
|
||||
internal_delay |= (1 << i);
|
||||
@@ -1251,9 +1197,9 @@ skip_fall:
|
||||
dev_dbg(dev, "Final internal delay: 0x%x\n", internal_delay);
|
||||
|
||||
internal_delay_phase = get_best_delay(dev, host, internal_delay);
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
|
||||
internal_delay_phase.final_phase <<
|
||||
MSDC_PAD_TUNE_CMDRRDLY_S);
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
|
||||
FIELD_PREP(MSDC_PAD_TUNE_CMDRRDLY,
|
||||
internal_delay_phase.final_phase));
|
||||
|
||||
skip_internal:
|
||||
dev_dbg(dev, "Final cmd pad delay: %x\n", final_delay);
|
||||
@@ -1278,8 +1224,8 @@ static int msdc_tune_data(struct udevice *dev, u32 opcode)
|
||||
clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
|
||||
|
||||
for (i = 0; i < PAD_DELAY_MAX; i++) {
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
|
||||
i << MSDC_PAD_TUNE_DATRRDLY_S);
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY,
|
||||
FIELD_PREP(MSDC_PAD_TUNE_DATRRDLY, i));
|
||||
|
||||
ret = mmc_send_tuning(mmc, opcode);
|
||||
if (!ret) {
|
||||
@@ -1301,8 +1247,8 @@ static int msdc_tune_data(struct udevice *dev, u32 opcode)
|
||||
setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
|
||||
|
||||
for (i = 0; i < PAD_DELAY_MAX; i++) {
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
|
||||
i << MSDC_PAD_TUNE_DATRRDLY_S);
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY,
|
||||
FIELD_PREP(MSDC_PAD_TUNE_DATRRDLY, i));
|
||||
|
||||
ret = mmc_send_tuning(mmc, opcode);
|
||||
if (!ret) {
|
||||
@@ -1322,24 +1268,24 @@ skip_fall:
|
||||
if (final_maxlen == final_rise_delay.maxlen) {
|
||||
clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
|
||||
clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
|
||||
final_rise_delay.final_phase <<
|
||||
MSDC_PAD_TUNE_DATRRDLY_S);
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY,
|
||||
FIELD_PREP(MSDC_PAD_TUNE_DATRRDLY,
|
||||
final_rise_delay.final_phase));
|
||||
final_delay = final_rise_delay.final_phase;
|
||||
} else {
|
||||
setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
|
||||
setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
|
||||
final_fall_delay.final_phase <<
|
||||
MSDC_PAD_TUNE_DATRRDLY_S);
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY,
|
||||
FIELD_PREP(MSDC_PAD_TUNE_DATRRDLY,
|
||||
final_fall_delay.final_phase));
|
||||
final_delay = final_fall_delay.final_phase;
|
||||
}
|
||||
|
||||
if (mmc->selected_mode == MMC_HS_200 ||
|
||||
mmc->selected_mode == UHS_SDR104)
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATWRDLY_M,
|
||||
host->hs200_write_int_delay <<
|
||||
MSDC_PAD_TUNE_DATWRDLY_S);
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATWRDLY,
|
||||
FIELD_PREP(MSDC_PAD_TUNE_DATWRDLY,
|
||||
host->hs200_write_int_delay));
|
||||
|
||||
dev_dbg(dev, "Final data pad delay: %x\n", final_delay);
|
||||
|
||||
@@ -1426,7 +1372,7 @@ static int msdc_execute_tuning(struct udevice *dev, uint opcode)
|
||||
clrbits_le32(&host->base->msdc_iocon,
|
||||
MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
|
||||
clrsetbits_le32(&host->base->pad_tune,
|
||||
MSDC_PAD_TUNE_DATRRDLY_M, 0);
|
||||
MSDC_PAD_TUNE_DATRRDLY, 0);
|
||||
|
||||
writel(host->hs400_ds_delay, &host->base->pad_ds_tune);
|
||||
/* for hs400 mode it must be set to 0 */
|
||||
@@ -1488,8 +1434,8 @@ static void msdc_init_hw(struct msdc_host *host)
|
||||
/* Enable/disable hw card detection according to fdt option */
|
||||
if (host->builtin_cd)
|
||||
clrsetbits_le32(&host->base->msdc_ps,
|
||||
MSDC_PS_CDDBCE_M,
|
||||
(DEFAULT_CD_DEBOUNCE << MSDC_PS_CDDBCE_S) |
|
||||
MSDC_PS_CDDBCE,
|
||||
FIELD_PREP(MSDC_PS_CDDBCE, DEFAULT_CD_DEBOUNCE) |
|
||||
MSDC_PS_CDEN);
|
||||
else
|
||||
clrbits_le32(&host->base->msdc_ps, MSDC_PS_CDEN);
|
||||
@@ -1518,8 +1464,8 @@ static void msdc_init_hw(struct msdc_host *host)
|
||||
writel(0xffff4089, &host->base->patch_bit1);
|
||||
|
||||
if (host->dev_comp->stop_clk_fix) {
|
||||
clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M,
|
||||
3 << MSDC_PB1_STOP_DLY_S);
|
||||
clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY,
|
||||
FIELD_PREP(MSDC_PB1_STOP_DLY, 3));
|
||||
clrbits_le32(&host->base->sdc_fifo_cfg,
|
||||
SDC_FIFO_CFG_WRVALIDSEL);
|
||||
clrbits_le32(&host->base->sdc_fifo_cfg,
|
||||
@@ -1532,8 +1478,8 @@ static void msdc_init_hw(struct msdc_host *host)
|
||||
setbits_le32(&host->base->emmc50_cfg0, EMMC50_CFG_CFCSTS_SEL);
|
||||
|
||||
if (host->dev_comp->async_fifo) {
|
||||
clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPWAIT_M,
|
||||
3 << MSDC_PB2_RESPWAIT_S);
|
||||
clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPWAIT,
|
||||
FIELD_PREP(MSDC_PB2_RESPWAIT, 3));
|
||||
|
||||
if (host->dev_comp->enhance_rx) {
|
||||
if (host->top_base)
|
||||
@@ -1544,11 +1490,11 @@ static void msdc_init_hw(struct msdc_host *host)
|
||||
SDC_RX_ENHANCE_EN);
|
||||
} else {
|
||||
clrsetbits_le32(&host->base->patch_bit2,
|
||||
MSDC_PB2_RESPSTSENSEL_M,
|
||||
2 << MSDC_PB2_RESPSTSENSEL_S);
|
||||
MSDC_PB2_RESPSTSENSEL,
|
||||
FIELD_PREP(MSDC_PB2_RESPSTSENSEL, 2));
|
||||
clrsetbits_le32(&host->base->patch_bit2,
|
||||
MSDC_PB2_CRCSTSENSEL_M,
|
||||
2 << MSDC_PB2_CRCSTSENSEL_S);
|
||||
MSDC_PB2_CRCSTSENSEL,
|
||||
FIELD_PREP(MSDC_PB2_CRCSTSENSEL, 2));
|
||||
}
|
||||
|
||||
/* use async fifo to avoid tune internal delay */
|
||||
@@ -1574,9 +1520,9 @@ static void msdc_init_hw(struct msdc_host *host)
|
||||
setbits_le32(tune_reg,
|
||||
MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
|
||||
clrsetbits_le32(&host->base->patch_bit0,
|
||||
MSDC_INT_DAT_LATCH_CK_SEL_M,
|
||||
host->latch_ck <<
|
||||
MSDC_INT_DAT_LATCH_CK_SEL_S);
|
||||
MSDC_INT_DAT_LATCH_CK_SEL,
|
||||
FIELD_PREP(MSDC_INT_DAT_LATCH_CK_SEL,
|
||||
host->latch_ck));
|
||||
}
|
||||
} else {
|
||||
/* choose clock tune */
|
||||
@@ -1590,39 +1536,38 @@ static void msdc_init_hw(struct msdc_host *host)
|
||||
if (host->dev_comp->builtin_pad_ctrl) {
|
||||
/* Set pins driving strength */
|
||||
writel(MSDC_PAD_CTRL0_CLKPD | MSDC_PAD_CTRL0_CLKSMT |
|
||||
MSDC_PAD_CTRL0_CLKIES | (4 << MSDC_PAD_CTRL0_CLKDRVN_S) |
|
||||
(4 << MSDC_PAD_CTRL0_CLKDRVP_S), &host->base->pad_ctrl0);
|
||||
MSDC_PAD_CTRL0_CLKIES | FIELD_PREP(MSDC_PAD_CTRL0_CLKDRVN, 4) |
|
||||
FIELD_PREP(MSDC_PAD_CTRL0_CLKDRVP, 4), &host->base->pad_ctrl0);
|
||||
writel(MSDC_PAD_CTRL1_CMDPU | MSDC_PAD_CTRL1_CMDSMT |
|
||||
MSDC_PAD_CTRL1_CMDIES | (4 << MSDC_PAD_CTRL1_CMDDRVN_S) |
|
||||
(4 << MSDC_PAD_CTRL1_CMDDRVP_S), &host->base->pad_ctrl1);
|
||||
MSDC_PAD_CTRL1_CMDIES | FIELD_PREP(MSDC_PAD_CTRL1_CMDDRVN, 4) |
|
||||
FIELD_PREP(MSDC_PAD_CTRL1_CMDDRVP, 4), &host->base->pad_ctrl1);
|
||||
writel(MSDC_PAD_CTRL2_DATPU | MSDC_PAD_CTRL2_DATSMT |
|
||||
MSDC_PAD_CTRL2_DATIES | (4 << MSDC_PAD_CTRL2_DATDRVN_S) |
|
||||
(4 << MSDC_PAD_CTRL2_DATDRVP_S), &host->base->pad_ctrl2);
|
||||
MSDC_PAD_CTRL2_DATIES | FIELD_PREP(MSDC_PAD_CTRL2_DATDRVN, 4) |
|
||||
FIELD_PREP(MSDC_PAD_CTRL2_DATDRVP, 4), &host->base->pad_ctrl2);
|
||||
}
|
||||
|
||||
if (host->dev_comp->default_pad_dly) {
|
||||
/* Default pad delay may be needed if tuning not enabled */
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CLKTDLY_M |
|
||||
MSDC_PAD_TUNE_CMDRRDLY_M |
|
||||
MSDC_PAD_TUNE_CMDRDLY_M |
|
||||
MSDC_PAD_TUNE_DATRRDLY_M |
|
||||
MSDC_PAD_TUNE_DATWRDLY_M,
|
||||
(0x10 << MSDC_PAD_TUNE_CLKTDLY_S) |
|
||||
(0x10 << MSDC_PAD_TUNE_CMDRRDLY_S) |
|
||||
(0x10 << MSDC_PAD_TUNE_CMDRDLY_S) |
|
||||
(0x10 << MSDC_PAD_TUNE_DATRRDLY_S) |
|
||||
(0x10 << MSDC_PAD_TUNE_DATWRDLY_S));
|
||||
|
||||
writel((0x10 << MSDC_PAD_TUNE0_DAT0RDDLY_S) |
|
||||
(0x10 << MSDC_PAD_TUNE0_DAT1RDDLY_S) |
|
||||
(0x10 << MSDC_PAD_TUNE0_DAT2RDDLY_S) |
|
||||
(0x10 << MSDC_PAD_TUNE0_DAT3RDDLY_S),
|
||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CLKTDLY |
|
||||
MSDC_PAD_TUNE_CMDRRDLY |
|
||||
MSDC_PAD_TUNE_CMDRDLY |
|
||||
MSDC_PAD_TUNE_DATRRDLY |
|
||||
MSDC_PAD_TUNE_DATWRDLY,
|
||||
FIELD_PREP(MSDC_PAD_TUNE_CLKTDLY, 0x10) |
|
||||
FIELD_PREP(MSDC_PAD_TUNE_CMDRRDLY, 0x10) |
|
||||
FIELD_PREP(MSDC_PAD_TUNE_CMDRDLY, 0x10) |
|
||||
FIELD_PREP(MSDC_PAD_TUNE_DATRRDLY, 0x10) |
|
||||
FIELD_PREP(MSDC_PAD_TUNE_DATWRDLY, 0x10));
|
||||
writel(FIELD_PREP(MSDC_PAD_TUNE0_DAT0RDDLY, 0x10) |
|
||||
FIELD_PREP(MSDC_PAD_TUNE0_DAT1RDDLY, 0x10) |
|
||||
FIELD_PREP(MSDC_PAD_TUNE0_DAT2RDDLY, 0x10) |
|
||||
FIELD_PREP(MSDC_PAD_TUNE0_DAT3RDDLY, 0x10),
|
||||
rd_dly0_reg);
|
||||
|
||||
writel((0x10 << MSDC_PAD_TUNE1_DAT4RDDLY_S) |
|
||||
(0x10 << MSDC_PAD_TUNE1_DAT5RDDLY_S) |
|
||||
(0x10 << MSDC_PAD_TUNE1_DAT6RDDLY_S) |
|
||||
(0x10 << MSDC_PAD_TUNE1_DAT7RDDLY_S),
|
||||
writel(FIELD_PREP(MSDC_PAD_TUNE1_DAT4RDDLY, 0x10) |
|
||||
FIELD_PREP(MSDC_PAD_TUNE1_DAT5RDDLY, 0x10) |
|
||||
FIELD_PREP(MSDC_PAD_TUNE1_DAT6RDDLY, 0x10) |
|
||||
FIELD_PREP(MSDC_PAD_TUNE1_DAT7RDDLY, 0x10),
|
||||
rd_dly1_reg);
|
||||
}
|
||||
|
||||
@@ -1633,8 +1578,8 @@ static void msdc_init_hw(struct msdc_host *host)
|
||||
clrbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIOIDE);
|
||||
|
||||
/* Configure to default data timeout */
|
||||
clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
|
||||
3 << SDC_CFG_DTOC_S);
|
||||
clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC,
|
||||
FIELD_PREP(SDC_CFG_DTOC, 3));
|
||||
|
||||
host->def_tune_para.iocon = readl(&host->base->msdc_iocon);
|
||||
host->def_tune_para.pad_tune = readl(&host->base->pad_tune);
|
||||
|
||||
Reference in New Issue
Block a user