global: Migrate CONFIG_FEC_MXC_PHYADDR to CFG

Perform a simple rename of CONFIG_FEC_MXC_PHYADDR to CFG_FEC_MXC_PHYADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2022-12-23 10:09:42 -05:00
parent 4daffb58e6
commit fa760c3240
38 changed files with 40 additions and 40 deletions
+1 -1
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@@ -214,7 +214,7 @@ int board_eth_init(struct bd_info *bis)
gpio_set_value(CL_SOM_IMX7_ETH1_PHY_NRST, 1);
/* MAC initialization */
return fecmxc_initialize_multi(bis, CL_SOM_IMX7_FEC_DEV_ID_PRI,
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
CFG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
}
/*
@@ -104,7 +104,7 @@ int board_eth_init(struct bd_info *bis)
setup_fec();
ret = fecmxc_initialize_multi(bis, 1,
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
CFG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
if (ret)
printf("FEC%d MXC: %s:failed\n", 1, __func__);
+1 -1
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@@ -18,7 +18,7 @@ CONFIG_PHYLIB
CONFIG_FEC_MXC_NO_ANEG
Relevant only if PHYLIB not used. Skips auto-negotiation restart.
CONFIG_FEC_MXC_PHYADDR
CFG_FEC_MXC_PHYADDR
Optional, selects the exact phy address that should be connected
and function fecmxc_initialize will try to initialize it.
+2 -2
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@@ -1086,8 +1086,8 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
int addr;
addr = device_get_phy_addr(priv, dev);
#ifdef CONFIG_FEC_MXC_PHYADDR
addr = CONFIG_FEC_MXC_PHYADDR;
#ifdef CFG_FEC_MXC_PHYADDR
addr = CFG_FEC_MXC_PHYADDR;
#endif
phydev = phy_connect(priv->bus, addr, dev, priv->interface);
+1 -1
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@@ -26,7 +26,7 @@
/* MMC Configs */
#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0
#define CFG_FEC_MXC_PHYADDR 0
#ifdef CONFIG_IMX_HAB
#define HAB_EXTRA_SETTINGS \
+1 -1
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@@ -20,7 +20,7 @@
/* ENET1 connects to base board and MUX with ESAI */
#define CFG_FEC_ENET_DEV 1
#define CONFIG_FEC_MXC_PHYADDR 0x0
#define CFG_FEC_MXC_PHYADDR 0x0
/* EEPROM */
#define EEPROM_I2C_BUS 0 /* I2C0 */
+1 -1
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@@ -118,6 +118,6 @@
#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */
/* Networking */
#define CONFIG_FEC_MXC_PHYADDR -1
#define CFG_FEC_MXC_PHYADDR -1
#endif /* __CGTQMX8_H */
+1 -1
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@@ -13,7 +13,7 @@
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
/* Network */
#define CONFIG_FEC_MXC_PHYADDR 0
#define CFG_FEC_MXC_PHYADDR 0
/* ENET1 */
#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
+1 -1
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@@ -132,7 +132,7 @@
/* APBH DMA is required for NAND support */
/* Ethernet */
#define CONFIG_FEC_MXC_PHYADDR 0
#define CFG_FEC_MXC_PHYADDR 0
/* USB */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+1 -1
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@@ -19,7 +19,7 @@
/* Ethernet Configs */
#define CONFIG_FEC_MXC_PHYADDR 0
#define CFG_FEC_MXC_PHYADDR 0
#define CFG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
+1 -1
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@@ -40,7 +40,7 @@
/* MMC */
/* Ethernet */
#define CONFIG_FEC_MXC_PHYADDR 1
#define CFG_FEC_MXC_PHYADDR 1
/* USB */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+1 -1
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@@ -136,7 +136,7 @@
#define CFG_SYS_FSL_USDHC_NUM 2
#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_FEC_MXC_PHYADDR 0
#define CFG_FEC_MXC_PHYADDR 0
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+1 -1
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@@ -61,6 +61,6 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_FEC_MXC_PHYADDR 0
#define CFG_FEC_MXC_PHYADDR 0
#endif
+1 -1
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@@ -13,7 +13,7 @@
#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#if defined(CONFIG_CMD_NET)
#define CONFIG_FEC_MXC_PHYADDR 1
#define CFG_FEC_MXC_PHYADDR 1
#define PHY_ANEG_TIMEOUT 20000
+1 -1
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@@ -14,7 +14,7 @@
#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#if defined(CONFIG_CMD_NET)
#define CONFIG_FEC_MXC_PHYADDR 1
#define CFG_FEC_MXC_PHYADDR 1
#define DWC_NET_PHYADDR 1
+1 -1
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@@ -39,7 +39,7 @@
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_FEC_MXC_PHYADDR 4
#define CFG_FEC_MXC_PHYADDR 4
#define PHY_ANEG_TIMEOUT 20000
+1 -1
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@@ -24,7 +24,7 @@
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_FEC_MXC_PHYADDR 0
#define CFG_FEC_MXC_PHYADDR 0
#endif
#define BOOT_TARGET_DEVICES(func) \
+1 -1
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@@ -21,7 +21,7 @@
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_FEC_MXC_PHYADDR 0
#define CFG_FEC_MXC_PHYADDR 0
#endif
#define CONFIG_MFG_ENV_SETTINGS \
+1 -1
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@@ -21,7 +21,7 @@
#if defined(CONFIG_FEC_MXC)
#define PHY_ANEG_TIMEOUT 20000
#define CONFIG_FEC_MXC_PHYADDR 1
#define CFG_FEC_MXC_PHYADDR 1
#endif
#ifdef CONFIG_DISTRO_DEFAULTS
+1 -1
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@@ -25,7 +25,7 @@
/* ENET1 Config */
#if defined(CONFIG_CMD_NET)
#define CONFIG_FEC_MXC_PHYADDR 0
#define CFG_FEC_MXC_PHYADDR 0
#define PHY_ANEG_TIMEOUT 20000
+1 -1
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@@ -102,7 +102,7 @@
#ifdef CONFIG_CMD_NET
#define CFG_FEC_ENET_DEV 0
#define CONFIG_FEC_MXC_PHYADDR 0x0
#define CFG_FEC_MXC_PHYADDR 0x0
#endif
#endif
+1 -1
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@@ -54,7 +54,7 @@
* Ethernet on SOC (FEC)
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_MXC_PHYADDR 0x0
#define CFG_FEC_MXC_PHYADDR 0x0
#endif
#define CFG_SYS_RTC_BUS_NUM 1 /* I2C2 */
+1 -1
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@@ -31,7 +31,7 @@
#define CFG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) }
/* Ethernet Configuration */
#define CONFIG_FEC_MXC_PHYADDR 1
#define CFG_FEC_MXC_PHYADDR 1
#define CFG_EXTRA_ENV_SETTINGS \
"console=ttymxc0,115200 quiet\0" \
+1 -1
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@@ -17,7 +17,7 @@
#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#if defined(CONFIG_CMD_NET)
#define CONFIG_FEC_MXC_PHYADDR 1
#define CFG_FEC_MXC_PHYADDR 1
#define PHY_ANEG_TIMEOUT 20000
#endif
+1 -1
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@@ -93,7 +93,7 @@
/* Network */
#define IMX_FEC_BASE ENET2_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
#define CFG_FEC_MXC_PHYADDR 0x0
#ifdef CONFIG_CMD_USB
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+1 -1
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@@ -115,7 +115,7 @@
/* Network */
#define CONFIG_FEC_MXC_PHYADDR 0x1
#define CFG_FEC_MXC_PHYADDR 0x1
#ifdef CONFIG_CMD_USB
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+2 -2
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@@ -124,9 +124,9 @@
#define CFG_FEC_ENET_DEV 1
#if (CFG_FEC_ENET_DEV == 0)
#define CONFIG_FEC_MXC_PHYADDR 0x2
#define CFG_FEC_MXC_PHYADDR 0x2
#elif (CFG_FEC_ENET_DEV == 1)
#define CONFIG_FEC_MXC_PHYADDR 0x1
#define CFG_FEC_MXC_PHYADDR 0x1
#endif
#endif
+1 -1
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@@ -18,7 +18,7 @@
#define CFG_SYS_FSL_USDHC_NUM 2
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 6
#define CFG_FEC_MXC_PHYADDR 6
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+1 -1
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@@ -33,7 +33,7 @@
#define CONFIG_MXC_USB_FLAGS 0
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_MXC_PHYADDR 0x1
#define CFG_FEC_MXC_PHYADDR 0x1
#endif
#define CFG_FEC_ENET_DEV 1
+1 -1
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@@ -98,6 +98,6 @@
/* Environment organization */
/* Ethernet Configuration */
#define CONFIG_FEC_MXC_PHYADDR 1
#define CFG_FEC_MXC_PHYADDR 1
#endif /* __CONFIG_H * */
+1 -1
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@@ -15,7 +15,7 @@
/* Network support */
#define CONFIG_FEC_MXC_PHYADDR 0x1
#define CFG_FEC_MXC_PHYADDR 0x1
#define CONFIG_MXC_UART_BASE UART6_BASE_ADDR
+1 -1
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@@ -21,7 +21,7 @@
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_FEC_MXC_PHYADDR 1
#define CFG_FEC_MXC_PHYADDR 1
#endif
/* Initial environment variables */
+1 -1
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@@ -66,7 +66,7 @@
#endif
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_MXC_PHYADDR 0x1
#define CFG_FEC_MXC_PHYADDR 0x1
#endif
#endif
+1 -1
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@@ -9,7 +9,7 @@
#ifndef __CONFIG_TQMA6_MBA6_H
#define __CONFIG_TQMA6_MBA6_H
#define CONFIG_FEC_MXC_PHYADDR 0x03
#define CFG_FEC_MXC_PHYADDR 0x03
#define CONFIG_MXC_UART_BASE UART2_BASE
#define CONSOLE_DEV "ttymxc1"
+1 -1
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@@ -7,7 +7,7 @@
#define __CONFIG_TQMA6_WRU4_H
/* Ethernet */
#define CONFIG_FEC_MXC_PHYADDR 0x01
#define CFG_FEC_MXC_PHYADDR 0x01
/* UART */
#define CONFIG_MXC_UART_BASE UART4_BASE
+1 -1
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@@ -21,7 +21,7 @@
#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_FEC_MXC_PHYADDR 0
#define CFG_FEC_MXC_PHYADDR 0
/* I2C Configs */
+1 -1
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@@ -34,7 +34,7 @@
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
/* Network */
#define CONFIG_FEC_MXC_PHYADDR 0x0
#define CFG_FEC_MXC_PHYADDR 0x0
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
+1 -1
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@@ -32,7 +32,7 @@
#define CONFIG_MXC_USB_FLAGS 0
#define CFG_FEC_ENET_DEV 0
#define CONFIG_FEC_MXC_PHYADDR 0x0
#define CFG_FEC_MXC_PHYADDR 0x0
#define CFG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \