pinctrl: qcom: add sdm670 pinctrl driver
Add a pinctrl driver for the TLMM block found in the SDM670 SoC. Signed-off-by: David Wronek <david.wronek@mainlining.org> Link: https://lore.kernel.org/r/20251003-sdm670-v2-3-52c0fa481286@mainlining.org Signed-off-by: Casey Connolly <kcxt@postmarketos.org>
This commit is contained in:
David Wronek
committed by
Casey Connolly
Casey Connolly
parent
8111e1357e
commit
f977cee372
@@ -68,6 +68,13 @@ config PINCTRL_QCOM_SC7280
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help
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Say Y here to enable support for pinctrl on the Snapdragon SC7280 SoC,
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config PINCTRL_QCOM_SDM670
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bool "Qualcomm SDM670 Pinctrl"
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select PINCTRL_QCOM
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help
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Say Y here to enable support for pinctrl on the Snapdragon SDM670 SoC,
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as well as the associated GPIO driver.
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config PINCTRL_QCOM_SDM660
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bool "Qualcomm SDM630/660 Pinctrl"
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select PINCTRL_QCOM
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@@ -13,6 +13,7 @@ obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
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obj-$(CONFIG_PINCTRL_QCOM_SA8775P) += pinctrl-sa8775p.o
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obj-$(CONFIG_PINCTRL_QCOM_SC7280) += pinctrl-sc7280.o
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obj-$(CONFIG_PINCTRL_QCOM_SDM660) += pinctrl-sdm660.o
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obj-$(CONFIG_PINCTRL_QCOM_SDM670) += pinctrl-sdm670.o
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obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
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obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o
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obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o
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@@ -0,0 +1,247 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Qualcomm SDM670 pinctrl
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*
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* (C) Copyright 2025 David Wronek <david.wronek@mainlining.org>
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*/
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#include <dm.h>
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#include "pinctrl-qcom.h"
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#define NORTH 0x00500000
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#define SOUTH 0x00900000
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#define WEST 0x00100000
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#define MAX_PIN_NAME_LEN 32
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static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
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static const struct pinctrl_function sdm670_pinctrl_functions[] = {
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{ "gpio", 0 },
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{ "blsp_uart2", 3 }, /* gpio 4 and 5, used for debug uart */
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};
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static const unsigned int sdm670_pin_offsets[] = {
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[0] = SOUTH,
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[1] = SOUTH,
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[2] = SOUTH,
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[3] = SOUTH,
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[4] = NORTH,
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[5] = NORTH,
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[6] = NORTH,
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[7] = NORTH,
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[8] = WEST,
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[9] = WEST,
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[10] = NORTH,
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[11] = NORTH,
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[12] = SOUTH,
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[13] = WEST,
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[14] = WEST,
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[15] = WEST,
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[16] = WEST,
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[17] = WEST,
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[18] = WEST,
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[19] = WEST,
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[20] = WEST,
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[21] = WEST,
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[22] = WEST,
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[23] = WEST,
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[24] = WEST,
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[25] = WEST,
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[26] = WEST,
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[27] = WEST,
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[28] = WEST,
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[29] = WEST,
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[30] = WEST,
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[31] = WEST,
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[32] = WEST,
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[33] = WEST,
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[34] = WEST,
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[35] = NORTH,
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[36] = NORTH,
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[37] = NORTH,
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[38] = NORTH,
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[39] = NORTH,
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[40] = NORTH,
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[41] = SOUTH,
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[42] = SOUTH,
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[43] = SOUTH,
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[44] = SOUTH,
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[45] = SOUTH,
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[46] = SOUTH,
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[47] = SOUTH,
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[48] = SOUTH,
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[49] = NORTH,
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[50] = NORTH,
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[51] = NORTH,
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[52] = NORTH,
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[53] = NORTH,
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[54] = NORTH,
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[55] = NORTH,
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[56] = NORTH,
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[57] = NORTH,
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[65] = NORTH,
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[66] = NORTH,
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[67] = NORTH,
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[68] = NORTH,
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[75] = NORTH,
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[76] = NORTH,
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[77] = NORTH,
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[78] = NORTH,
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[79] = NORTH,
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[80] = NORTH,
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[81] = NORTH,
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[82] = NORTH,
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[83] = NORTH,
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[84] = NORTH,
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[85] = SOUTH,
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[86] = SOUTH,
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[87] = SOUTH,
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[88] = SOUTH,
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[89] = SOUTH,
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[90] = SOUTH,
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[91] = SOUTH,
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[92] = SOUTH,
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[93] = SOUTH,
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[94] = SOUTH,
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[95] = SOUTH,
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[96] = SOUTH,
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[97] = WEST,
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[98] = WEST,
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[99] = NORTH,
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[100] = WEST,
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[101] = WEST,
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[102] = WEST,
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[103] = WEST,
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[105] = NORTH,
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[106] = NORTH,
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[107] = NORTH,
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[108] = NORTH,
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[109] = NORTH,
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[110] = NORTH,
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[111] = NORTH,
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[112] = NORTH,
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[113] = NORTH,
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[114] = WEST,
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[115] = WEST,
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[116] = SOUTH,
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[117] = NORTH,
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[118] = NORTH,
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[119] = NORTH,
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[120] = NORTH,
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[121] = NORTH,
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[122] = NORTH,
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[123] = NORTH,
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[124] = NORTH,
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[125] = NORTH,
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[126] = NORTH,
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[127] = WEST,
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[128] = WEST,
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[129] = WEST,
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[130] = WEST,
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[131] = WEST,
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[132] = WEST,
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[133] = NORTH,
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[134] = NORTH,
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[135] = WEST,
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[136] = WEST,
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[137] = WEST,
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[138] = WEST,
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[139] = WEST,
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[140] = WEST,
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[141] = WEST,
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[142] = WEST,
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[143] = WEST,
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[144] = SOUTH,
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[145] = SOUTH,
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[146] = WEST,
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[147] = WEST,
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[148] = WEST,
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[149] = WEST,
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};
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#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
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{ \
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.name = pg_name, \
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.ctl_reg = ctl, \
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.io_reg = 0, \
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.pull_bit = pull, \
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.drv_bit = drv, \
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.oe_bit = -1, \
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.in_bit = -1, \
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.out_bit = -1, \
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}
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#define UFS_RESET(pg_name, offset) \
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{ \
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.name = pg_name, \
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.ctl_reg = offset, \
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.io_reg = offset + 0x4, \
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.pull_bit = 3, \
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.drv_bit = 0, \
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.oe_bit = -1, \
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.in_bit = -1, \
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.out_bit = 0, \
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}
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static const struct msm_special_pin_data sdm670_special_pins_data[] = {
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UFS_RESET("ufs_reset", 0x99d000),
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SDC_QDSD_PINGROUP("sdc1_rclk", NORTH + 0x99000, 15, 0),
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SDC_QDSD_PINGROUP("sdc1_clk", NORTH + 0x99000, 13, 6),
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SDC_QDSD_PINGROUP("sdc1_cmd", NORTH + 0x99000, 11, 3),
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SDC_QDSD_PINGROUP("sdc1_data", NORTH + 0x99000, 9, 0),
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SDC_QDSD_PINGROUP("sdc2_clk", NORTH + 0x9a000, 14, 6),
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SDC_QDSD_PINGROUP("sdc2_cmd", NORTH + 0x9a000, 11, 3),
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SDC_QDSD_PINGROUP("sdc2_data", NORTH + 0x9a000, 9, 0),
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};
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static const char *sdm670_get_function_name(struct udevice *dev, unsigned int selector)
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{
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return sdm670_pinctrl_functions[selector].name;
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}
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static const char *sdm670_get_pin_name(struct udevice *dev, unsigned int selector)
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{
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if (selector >= 150 && selector <= 157)
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snprintf(pin_name, MAX_PIN_NAME_LEN,
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sdm670_special_pins_data[selector - 150].name);
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else
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snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
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return pin_name;
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}
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static int sdm670_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
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{
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if (selector >= 0 && selector < ARRAY_SIZE(sdm670_pinctrl_functions))
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return sdm670_pinctrl_functions[selector].val;
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return -EINVAL;
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}
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struct msm_pinctrl_data sdm670_data = {
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.pin_data = {
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.pin_offsets = sdm670_pin_offsets,
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.pin_count = ARRAY_SIZE(sdm670_pin_offsets) + ARRAY_SIZE(sdm670_special_pins_data),
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.special_pins_start = 150,
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.special_pins_data = sdm670_special_pins_data,
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},
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.functions_count = ARRAY_SIZE(sdm670_pinctrl_functions),
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.get_function_name = sdm670_get_function_name,
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.get_function_mux = sdm670_get_function_mux,
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.get_pin_name = sdm670_get_pin_name,
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};
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static const struct udevice_id msm_pinctrl_ids[] = {
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{
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.compatible = "qcom,sdm670-tlmm",
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.data = (ulong)&sdm670_data
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},
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{ /* Sentinel */ }
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};
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U_BOOT_DRIVER(pinctrl_ssdm670) = {
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.name = "pinctrl_sdm670",
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.id = UCLASS_NOP,
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.of_match = msm_pinctrl_ids,
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.ops = &msm_pinctrl_ops,
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.bind = msm_pinctrl_bind,
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};
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