Kconfig: arch: restyle

Restyle all Kconfigs other then "arm":
Menu entries   : no space left
Menu attributes: 1 TAB
Help text      : 1 TAB + 2 spaces

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

arch/Kconfig

@@ -11,14 +11,14 @@ config HAVE_ARCH_IOREMAP
 config HAVE_SETJMP
 	bool
 	help
-	 The architecture supports setjmp() and longjmp().
+	  The architecture supports setjmp() and longjmp().
 
 config HAVE_INITJMP
 	bool
 	depends on HAVE_SETJMP
 	help
-	 The architecture supports initjmp(), a non-standard companion to
-	 setjmp() and longjmp().
+	  The architecture supports initjmp(), a non-standard companion to
+	  setjmp() and longjmp().
 
 config SUPPORT_BIG_ENDIAN
 	bool
@@ -457,11 +457,11 @@ config SYS_CONFIG_NAME
 config SYS_DISABLE_DCACHE_OPS
 	bool
 	help
-	 This option disables dcache flush and dcache invalidation
-	 operations. For example, on coherent systems where cache
-	 operatios are not required, enable this option to avoid them.
-	 Note that, its up to the individual architectures to implement
-	 this functionality.
+	  This option disables dcache flush and dcache invalidation
+	  operations. For example, on coherent systems where cache
+	  operatios are not required, enable this option to avoid them.
+	  Note that, its up to the individual architectures to implement
+	  this functionality.
 
 config SYS_IMMR
 	hex "Address for the Internal Memory-Mapped Registers (IMMR) window"

arch/m68k/Kconfig

@@ -11,56 +11,56 @@ config STATIC_RELA
 config MCF520x
 	select OF_CONTROL
 	select DM
-        select DM_SERIAL
+	select DM_SERIAL
 	select ARCH_COLDFIRE
 	bool
 
 config MCF52x2
 	select OF_CONTROL
 	select DM
-        select DM_SERIAL
+	select DM_SERIAL
 	select ARCH_COLDFIRE
 	bool
 
 config MCF523x
 	select OF_CONTROL
 	select DM
-        select DM_SERIAL
+	select DM_SERIAL
 	select ARCH_COLDFIRE
 	bool
 
 config MCF530x
 	select OF_CONTROL
 	select DM
-        select DM_SERIAL
+	select DM_SERIAL
 	select ARCH_COLDFIRE
 	bool
 
 config MCF5301x
 	select OF_CONTROL
 	select DM
-        select DM_SERIAL
+	select DM_SERIAL
 	select ARCH_COLDFIRE
 	bool
 
 config MCF532x
 	select OF_CONTROL
 	select DM
-        select DM_SERIAL
+	select DM_SERIAL
 	select ARCH_COLDFIRE
 	bool
 
 config MCF537x
 	select OF_CONTROL
 	select DM
-        select DM_SERIAL
+	select DM_SERIAL
 	select ARCH_COLDFIRE
 	bool
 
 config MCF5441x
 	select OF_CONTROL
 	select DM
-        select DM_SERIAL
+	select DM_SERIAL
 	select ARCH_COLDFIRE
 	select CREATE_ARCH_SYMLINK
 	bool
@@ -191,9 +191,9 @@ config TARGET_AMCORE
 	select M5307
 
 config TARGET_STMARK2
-        bool "Support stmark2"
-        select CF_DSPI
-        select M54418
+	bool "Support stmark2"
+	select CF_DSPI
+	select M54418
 
 config TARGET_QEMU_M68K
 	bool "Support QEMU m68k virt"

arch/mips/Kconfig

@@ -267,8 +267,8 @@ config CPU_MIPS64_OCTEON
 	select 64BIT
 	select SPL_64BIT if SPL
 	help
-	 Choose this option for Marvell Octeon CPUs.  These CPUs are between
-	 MIPS64 R5 and R6 with other extensions.
+	  Choose this option for Marvell Octeon CPUs.  These CPUs are between
+	  MIPS64 R5 and R6 with other extensions.
 
 endchoice
 
@@ -351,7 +351,7 @@ config MIPS_RELOCATION_TABLE_SIZE
 	range 0x100 0x10000
 	default "0xc000" if TARGET_MALTA
 	default "0x8000"
-	---help---
+	help
 	  A table of relocation data will be appended to the U-Boot binary
 	  and parsed in relocate_code() to fix up all offsets in the relocated
 	  U-Boot.
@@ -526,7 +526,7 @@ config MIPS_SRAM_INIT
 config DMA_ADDR_T_64BIT
 	bool
 	help
-	 Select this to enable 64-bit DMA addressing
+	  Select this to enable 64-bit DMA addressing
 
 config SYS_DCACHE_SIZE
 	int

arch/mips/mach-octeon/Kconfig

@@ -25,8 +25,8 @@ choice
 config SOC_OCTEON3
 	bool "Octeon III family"
 	help
-	 This selects the Octeon III SoC family CN70xx, CN73XX, CN78xx
-	 and CNF75XX.
+	  This selects the Octeon III SoC family CN70xx, CN73XX, CN78xx
+	  and CNF75XX.
 
 endchoice
 
@@ -38,14 +38,14 @@ config TARGET_OCTEON_EBB7304
 	bool "Marvell Octeon EBB7304"
 	select OCTEON_CN73XX
 	help
-	 Choose this for the Octeon EBB7304 board
+	  Choose this for the Octeon EBB7304 board
 
 config TARGET_OCTEON_NIC23
 	bool "Marvell Octeon NIC23"
 	select ARCH_MISC_INIT
 	select OCTEON_CN73XX
 	help
-	 Choose this for the Octeon NIC23 board
+	  Choose this for the Octeon NIC23 board
 
 endchoice
 

arch/powerpc/cpu/mpc85xx/Kconfig

@@ -966,14 +966,14 @@ config E500
 	bool
 	default y
 	help
-		Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
+	  Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
 
 config E500MC
 	bool
 	select BTB
 	imply CMD_PCI
 	help
-		Enable PowerPC E500MC core
+	  Enable PowerPC E500MC core
 
 config E5500
 	bool
@@ -982,7 +982,7 @@ config E6500
 	bool
 	select BTB
 	help
-		Enable PowerPC E6500 core
+	  Enable PowerPC E6500 core
 
 config NOBQFMAN
 	bool
@@ -990,7 +990,7 @@ config NOBQFMAN
 config FSL_LAW
 	bool
 	help
-		Use Freescale common code for Local Access Window
+	  Use Freescale common code for Local Access Window
 
 config HETROGENOUS_CLUSTERS
 	bool
@@ -1054,10 +1054,10 @@ config SYS_CCSRBAR_DEFAULT
 				ARCH_T4240
 	default 0xe0000000 if ARCH_QEMU_E500
 	help
-		Default value of CCSRBAR comes from power-on-reset. It
-		is fixed on each SoC. Some SoCs can have different value
-		if changed by pre-boot regime. The value here must match
-		the current value in SoC. If not sure, do not change.
+	  Default value of CCSRBAR comes from power-on-reset. It
+	  is fixed on each SoC. Some SoCs can have different value
+	  if changed by pre-boot regime. The value here must match
+	  the current value in SoC. If not sure, do not change.
 
 config SYS_DPAA_PME
 	bool
@@ -1287,8 +1287,8 @@ config SYS_FSL_NUM_LAWS
 	default 8 if	ARCH_MPC8540	|| \
 			ARCH_MPC8560
 	help
-		Number of local access windows. This is fixed per SoC.
-		If not sure, do not change.
+	  Number of local access windows. This is fixed per SoC.
+	  If not sure, do not change.
 
 config SYS_FSL_CORES_PER_CLUSTER
 	int
@@ -1308,8 +1308,8 @@ config SYS_NUM_TLBCAMS
 	default 64 if E500MC
 	default 16
 	help
-		Number of TLB CAM entries for Book-E chips. 64 for E500MC,
-		16 for other E500 SoCs.
+	  Number of TLB CAM entries for Book-E chips. 64 for E500MC,
+	  16 for other E500 SoCs.
 
 config L2_CACHE
 	bool "Enable L2 cache support"
@@ -1401,12 +1401,12 @@ config SYS_PPC_E500_DEBUG_TLB
 			ARCH_BSC9132	|| \
 			ARCH_C29X
 	help
-		Select a temporary TLB entry to be used during boot to work
-                around limitations in e500v1 and e500v2 external debugger
-                support. This reduces the portions of the boot code where
-                breakpoints and single stepping do not work. The value of this
-                symbol should be set to the TLB1 entry to be used for this
-                purpose. If unsure, do not change.
+	  Select a temporary TLB entry to be used during boot to work
+	  around limitations in e500v1 and e500v2 external debugger
+	  support. This reduces the portions of the boot code where
+	  breakpoints and single stepping do not work. The value of this
+	  symbol should be set to the TLB1 entry to be used for this
+	  purpose. If unsure, do not change.
 
 config SYS_FSL_IFC_CLK_DIV
 	int "Divider of platform clock"
@@ -1419,8 +1419,8 @@ config SYS_FSL_IFC_CLK_DIV
 			ARCH_T4240
 	default 1
 	help
-		Defines divider of platform clock(clock input to
-		IFC controller).
+	  Defines divider of platform clock(clock input to
+	  IFC controller).
 
 config SYS_FSL_LBC_CLK_DIV
 	int "Divider of platform clock"
@@ -1435,8 +1435,8 @@ config SYS_FSL_LBC_CLK_DIV
 	default 1
 
 	help
-		Defines divider of platform clock(clock input to
-		eLBC controller).
+	  Defines divider of platform clock(clock input to
+	  eLBC controller).
 
 config ENABLE_36BIT_PHYS
 	bool "Enable 36bit physical address space support"

arch/x86/Kconfig

@@ -44,9 +44,9 @@ config X86_RUN_64BIT_NO_SPL
 	bool "64-bit"
 	select X86_64
 	help
-          Build U-Boot as a 64-bit binary without SPL. As U-Boot enters
-          in 64-bit mode, the assumption is that the silicon is fully
-          initialized (MP, page tables, etc.).
+	  Build U-Boot as a 64-bit binary without SPL. As U-Boot enters
+	  in 64-bit mode, the assumption is that the silicon is fully
+	  initialized (MP, page tables, etc.).
 
 endchoice
 
@@ -585,11 +585,11 @@ config DCACHE_RAM_MRC_VAR_SIZE
 	  not boot.
 
 config HAVE_REFCODE
-        bool "Add a Reference Code binary"
-        help
-          Select this option to add a Reference Code binary to the resulting
-          U-Boot image. This is an Intel binary blob that handles system
-          initialisation, in this case the PCH and System Agent.
+	bool "Add a Reference Code binary"
+	help
+	  Select this option to add a Reference Code binary to the resulting
+	  U-Boot image. This is an Intel binary blob that handles system
+	  initialisation, in this case the PCH and System Agent.
 
           Note: Without this binary (on platforms that need it such as
           broadwell) U-Boot will be missing some critical setup steps.
@@ -617,8 +617,8 @@ config SMP_AP_WORK
 	bool
 	depends on SMP
 	help
-	 Allow APs to do other work after initialisation instead of going
-	 to sleep.
+	  Allow APs to do other work after initialisation instead of going
+	  to sleep.
 
 config MAX_CPUS
 	int "Maximum number of CPUs permitted"