spi: cadence: Use reset_reset_bulk() for proper reset cycling

Use the new reset_reset_bulk() API to properly cycle reset signals
during probe instead of just deasserting them. This ensures the
controller is properly reset before initialization.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/92e614075d2c4820d3e4485aa0bdda11efd1f7ca.1779709539.git.michal.simek@amd.com
This commit is contained in:
Michal Simek
2026-06-08 10:50:06 +02:00
parent 4e3f64c7cc
commit f59b7a010e
+4 -12
View File
@@ -31,6 +31,8 @@
#define CQSPI_DISABLE_STIG_MODE BIT(0)
#define CQSPI_DMA_MODE BIT(1)
#define CQSPI_RESET_DELAY_US 10
__weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
const struct spi_mem_op *op)
{
@@ -256,19 +258,9 @@ static int cadence_spi_probe(struct udevice *bus)
priv->resets = devm_reset_bulk_get_optional(bus);
if (priv->resets) {
/* Assert all OSPI reset lines */
ret = reset_assert_bulk(priv->resets);
ret = reset_reset_bulk(priv->resets, CQSPI_RESET_DELAY_US);
if (ret) {
dev_err(bus, "Failed to assert OSPI reset: %d\n", ret);
return ret;
}
udelay(10);
/* Deassert all OSPI reset lines */
ret = reset_deassert_bulk(priv->resets);
if (ret) {
dev_err(bus, "Failed to deassert OSPI reset: %d\n", ret);
dev_err(bus, "Failed to reset OSPI: %d\n", ret);
return ret;
}
}