Merge patch series "drivers: ata: Remove duplicate newlines"

Drop all duplicate newlines from the driver directory files.
2024-07-22 10:54:13 -06:00
parent 9b186f68af f553d29ae8
commit f1aa32d65d
228 changed files with 0 additions and 397 deletions
@@ -294,7 +294,6 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv)
 	return 0;
 }

-
 static void ahci_print_info(struct ahci_uc_priv *uc_priv)
 {
 	void __iomem *mmio = uc_priv->mmio_base;
@@ -520,7 +519,6 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
 	return wait_spinup(port_mmio);
 }

-
 static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis,
 			       int fis_len, u8 *buf, int buf_len, u8 is_write)
 {
@@ -647,7 +645,6 @@ static int ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv,
 	return 0;
 }

-
 /*
 * SCSI READ10/WRITE10 command operation.
 */
@@ -759,7 +756,6 @@ static int ata_scsiop_read_write(struct ahci_uc_priv *uc_priv,
 	return 0;
 }

-
 /*
 * SCSI READ CAPACITY10 command operation.
 */
@@ -790,7 +786,6 @@ static int ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv,
 	return 0;
 }

-
 /*
 * SCSI READ CAPACITY16 command operation.
 */
@@ -817,7 +812,6 @@ static int ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv,
 	return 0;
 }

-
 /*
 * SCSI TEST UNIT READY command operation.
 */
@@ -827,7 +821,6 @@ static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv,
 	return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM;
 }

-
 static int ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
 {
 	struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev->parent);
@@ -422,7 +422,6 @@ static u32 BE_accessReg(int regOffset, u32 value, int func)
 	u16 val16;
 	u32 val32;

-
 	/* Decode the configuration register values for the register we wish to
 	 * access
 	 */
@@ -105,7 +105,6 @@

 #ifdef CONFIG_X86EMU_DEBUG

-
 # define DECODE_PRINTF(x)	if (DEBUG_DECODE()) \
 				    x86emu_decode_printf(x)
 # define DECODE_PRINTF2(x,y)	if (DEBUG_DECODE()) \
@@ -97,7 +97,6 @@
 *
 ****************************************************************************/

-
 #define PRIM_OPS_NO_REDEFINE_ASM
 #include "x86emu/x86emui.h"

@@ -120,7 +119,6 @@ static u32 x86emu_parity_tab[8] =

 /*----------------------------- Implementation ----------------------------*/

-
 /*--------- Side effects helper functions -------*/

 /****************************************************************************
@@ -790,7 +790,6 @@ static ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 			pwrsave = 1;
 	}

-
 	while (blkcnt-- > 0) {
 		c = ide_wait(device, IDE_TIME_OUT);

@@ -62,7 +62,6 @@ static int l2x0_probe(struct udevice *dev)
 	return 0;
 }

-
 static const struct udevice_id l2x0_ids[] = {
 	{ .compatible = "arm,pl310-cache" },
 	{}
@@ -27,7 +27,6 @@ static int snadbox_disable(struct udevice *dev)
 	return 0;
 }

-
 static const struct cache_ops sandbox_cache_ops = {
 	.get_info	= sandbox_get_info,
 	.enable		= sandbox_enable,
@@ -130,7 +130,6 @@ static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
 		return log_ret(ret);
 	}

-
 	return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
 				     index, clk);
 }
@@ -109,7 +109,6 @@ static const resource_size_t zynqmp_crl_apb_clkc_base = 0xff5e0020;
 #define PLLCTRL_PRE_SRC_SHFT	20
 #define PLLCTRL_PRE_SRC_MASK	(0x7 << PLLCTRL_PRE_SRC_SHFT)

-
 #define NUM_MIO_PINS	77

 enum zynqmp_clk {
@@ -113,8 +113,6 @@ static int imxrt1170_clk_probe(struct udevice *dev)
 	/* Anatop clocks */
 	base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop"));

-
-
 	clk_dm(IMXRT1170_CLK_RCOSC_48M,
 	       imx_clk_fixed_factor("rcosc48M", "rcosc16M", 3, 1));
 	clk_dm(IMXRT1170_CLK_RCOSC_400M,
@@ -122,7 +120,6 @@ static int imxrt1170_clk_probe(struct udevice *dev)
 	clk_dm(IMXRT1170_CLK_RCOSC_48M_DIV2,
 	       imx_clk_fixed_factor("rcosc48M_div2",  "rcosc48M", 1, 2));

-
 	clk_dm(IMXRT1170_CLK_PLL_ARM,
 	       imx_clk_pllv3(IMX_PLLV3_SYS, "pll_arm", "osc",
 			     base + 0x200, 0xff));
@@ -248,7 +248,6 @@ static ulong clk_pll1416x_set_rate(struct clk *clk, unsigned long drate)
 	tmp |= BYPASS_MASK;
 	writel(tmp, pll->base);

-
 	div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
 		(rate->sdiv << SDIV_SHIFT);
 	writel(div_val, pll->base + 0x4);
@@ -376,7 +376,6 @@ static int qcom_power_set(struct power_domain *pwr, bool on)
 					 !(value & GDSC_PWR_ON_MASK),
 					 GDSC_STATUS_POLL_TIMEOUT_US);

-
 	if (ret == -ETIMEDOUT)
 		printf("WARNING: GDSC %lu is stuck during power on/off\n",
 		       pwr->id);
@@ -67,7 +67,6 @@
 #define EMAC_PTP_CMD_RCGR		(0x4e014)
 #define EMAC_CMD_RCGR			(0x4e01c)

-
 /* GPLL0 clock control registers */
 #define GPLL0_STATUS_ACTIVE BIT(31)

@@ -334,7 +334,6 @@ void rk3328_configure_cpu(struct rk3328_cru *cru,
 		     aclkm_div << ACLKM_CORE_DIV_SHIFT);
 }

-
 static ulong rk3328_i2c_get_clk(struct rk3328_cru *cru, ulong clk_id)
 {
 	u32 div, con;
@@ -401,7 +401,6 @@ out:
 	return ret;
 }

-
 static int __of_address_to_resource(const struct device_node *dev,
 		const __be32 *addrp, u64 size, unsigned int flags,
 		const char *name, struct resource *r)
@@ -691,7 +691,6 @@
 #define OP_ALG_RNG4_MAS                (0x1f3 << OP_ALG_RNG4_SHIFT)
 #define OP_ALG_RNG4_SK         (0x100 << OP_ALG_RNG4_SHIFT)

-
 /* Structures for Protocol Data Blocks */
 struct __packed pdb_ecdsa_verify {
 	uint32_t pdb_hdr;
@@ -26,7 +26,6 @@
 #define JRSTA_DECOERR_INDEX_MASK    0xff00
 #define JRSTA_DECOERR_ERROR_MASK    0x00ff

-
 static const struct {
 	u8 value;
 	const char *error_text;
@@ -645,7 +645,6 @@ static int of_sdram_firewall_setup(const void *blob)
 	writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
 	writel(0, &socfpga_noc_fw_ddr_l3_base->enable);

-
 	for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
 		sprintf(name, "%s", firewall_table[i].prop_name);
 		ret = fdtdec_get_int_array(blob, child, name,
@@ -689,7 +689,6 @@ static void scc_mgr_apply_group_dm_out1_delay(struct socfpga_sdrseq *seq,
 	}
 }

-
 /* apply and load delay on both DQS and OCT out1 */
 static void scc_mgr_apply_group_dqs_io_and_oct_out1(struct socfpga_sdrseq *seq,
 						    u32 write_group, u32 delay)
@@ -2580,7 +2579,6 @@ static int rw_mgr_mem_calibrate_vfifo_center(struct socfpga_sdrseq *seq,
 			 &sticky_bit_chk,
 			 left_edge, right_edge, use_read_test);

-
 	/* Search for the right edge of the window for each bit */
 	ret = search_right_edge(seq, 0, rank_bgn, rw_group, rw_group,
 				start_dqs, start_dqs_en,
@@ -164,7 +164,6 @@ struct param_type {
 	u32	write_correct_mask_vg;
 };

-
 /* global variable holder */
 struct gbl_type {
 	uint32_t phy_debug_mode_flags;
@@ -19,7 +19,6 @@
 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
 #endif

-
 /*
 * regs has the to-be-set values for DDR controller registers
 * ctrl_num is the DDR controller number
@@ -1209,7 +1209,6 @@ void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
 	for (i = 0; i < 18; i++)
 		printf("%c", spd->mpart[i]);

-
 	printf("<<* 73 Manufacturer's Part Number *\n");

 	printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
@@ -1227,7 +1226,6 @@ void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
 	for (i = 0; i < 27; i++)
 		printf("%02x", spd->mspec[i]);

-
 	printf("* 99 Manufacturer Specific Data *\n");
 }
 #endif
@@ -1946,7 +1944,6 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
 		if (argc == 0)
 			continue;

-
 		if (strcmp(argv[0], "help") == 0) {
 			puts(usage);
 			continue;
@@ -2042,7 +2039,6 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
 			debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n",
 				src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask);

-
 			switch (step_mask) {

 			case STEP_GET_SPD:
@@ -2117,7 +2113,6 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
 			if (error)
 				continue;

-
 			/* Check arguments */

 			/* ERROR: If no steps were found */
@@ -191,7 +191,6 @@ compute_cas_latency(const unsigned int ctrl_num,
 	      lowest_good_caslat);
 	outpdimm->lowest_common_spd_caslat = lowest_good_caslat;

-
 	/*
 	 * Compute a common 'de-rated' CAS latency.
 	 *
@@ -78,7 +78,6 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing)

 		dwc_ddrphy_apb_wr(0xd0000, 0x1);

-
 		fsp_msg++;
 	}

@@ -75,7 +75,6 @@ int ddr3_init(void)
 #endif
 	}

-
 	status = ddr3_silicon_post_init();
 	if (MV_OK != status) {
 		printf("DDR3 Post Init - FAILED 0x%x\n", status);
@@ -89,7 +88,6 @@ int ddr3_init(void)
 		return status;
 	}

-
 	/* Post MC/PHY initializations */
 	mv_ddr_post_training_soc_config(ddr_type);

@@ -285,7 +285,6 @@ int ddr3_tip_tune_training_params(u32 dev_num,
 	if (params->g_rtt_park != PARAM_UNDEFINED)
 		g_rtt_park = params->g_rtt_park;

-
 	DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
 			  ("DGL parameters: 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n",
 			   g_zpri_data, g_znri_data, g_zpri_ctrl, g_znri_ctrl, g_zpodt_data, g_znodt_data,
@@ -870,7 +869,6 @@ int ddr3_tip_validate_algo_components(u8 dev_num)
 	return (status == 1) ? MV_OK : MV_NOT_INITIALIZED;
 }

-
 int ddr3_pre_algo_config(void)
 {
 	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
@@ -1114,7 +1112,6 @@ int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type interface_access,
 		mv_ddr_phy_write(phy_access, phy_id, phy_type, reg_addr, data_value, OPERATION_WRITE);
 }

-
 /*
 * Phy read-modify-write
 */
@@ -1406,7 +1403,6 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
 			t2t = (cs_num == 1) ? 0 : 1;
 		}

-
 		if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_INTERLEAVE_WA) == 1) {
 			/* Use 1T mode if 1:1 ratio configured */
 			if (config_func_info[dev_num].tip_get_clock_ratio(frequency) == 1) {
@@ -82,7 +82,6 @@
 #define ADDR_SIZE_8GB			0x40000000
 #define ADDR_SIZE_16GB			0x80000000

-
 enum hws_edge_compare {
 	EDGE_PF,
 	EDGE_FP,
@@ -1677,7 +1677,6 @@ static int mpr_rd_frmt_config(
 	u32 val, mask;
 	u8 cs_bitmask_inv;

-
 	if (dis_auto_refresh == 1) {
 		ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_CTRL_CTRL_REG,
 			  ODPG_CTRL_AUTO_REFRESH_DIS << ODPG_CTRL_AUTO_REFRESH_OFFS,
@@ -79,7 +79,6 @@
 #define MV_DEBUG_WL_FULL
 #endif

-
 /* The following is a list of Marvell status */
 #define MV_ERROR	(-1)
 #define MV_OK		(0x00)	/* Operation succeeded                   */
@@ -1144,7 +1144,6 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
 	uint64_t cs_mem_size = 0;
 	uint64_t mem_total_size_c, cs_mem_size_c;

-
 #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
 	u32 physical_mem_size;
 	u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE;
@@ -55,7 +55,6 @@

 #define MARVELL_BOARD				MARVELL_BOARD_ID_BASE

-
 #define REG_DEVICE_SAR1_ADDR			0xe4204
 #define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET	17
 #define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK	0x1f
@@ -520,5 +520,4 @@ enum {
 #define RESULT_PHY_RX_OFFS			5
 #define RESULT_PHY_TX_OFFS			0

-
 #endif /* _MV_DDR_REGS_H */
@@ -269,7 +269,6 @@ int dfu_get_medium_size_mmc(struct dfu_entity *dfu, u64 *size)
 	}
 }

-
 static int mmc_file_buf_read(struct dfu_entity *dfu, u64 offset, void *buf,
 			     long *len)
 {
@@ -21,7 +21,6 @@
 #define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT)
 #endif

-
 #if defined(CONFIG_MPC83xx)
 dma83xx_t *dma_base = (void *)(CFG_SYS_MPC83xx_DMA_ADDR);
 #elif defined(CONFIG_MPC85xx)
@@ -1710,7 +1710,6 @@ static int udma_probe(struct udevice *dev)
 	struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
 	ofnode navss_ofnode = ofnode_get_parent(dev_ofnode(dev));

-
 	ud->match_data = (void *)dev_get_driver_data(dev);
 	ret = udma_get_mmrs(dev);
 	if (ret)
@@ -139,7 +139,6 @@ static struct ti_sci_xfer *ti_sci_setup_one_xfer(struct ti_sci_info *info,
 		return ERR_PTR(-ERANGE);
 	}

-
 	info->seq = ~info->seq;
 	xfer->tx_message.buf = buf;
 	xfer->tx_message.len = tx_message_size;
@@ -79,7 +79,6 @@ int ACEX1K_info( Altera_desc *desc )
 	return FPGA_SUCCESS;
 }

-
 /* ------------------------------------------------------------------------- */
 /* ACEX1K Passive Serial Generic Implementation                                  */

@@ -30,7 +30,6 @@ static void fpga_no_sup(char *fn, char *msg)
 		printf("No FPGA support!\n");
 }

-
 /* fpga_get_desc
 *	map a device number to a descriptor
 */
@@ -580,7 +580,6 @@ void ispVMFreeMem(void)
 	}
 }

-
 /*
 *
 * ispVMDataSize
@@ -35,7 +35,6 @@ extern unsigned short g_usIntelDataIndex;
 extern unsigned short g_usIntelBufferSize;
 extern char *const g_szSupportedVersions[];

-
 /*
 * ispVMDelay
 *
@@ -85,7 +85,6 @@ static int spartan2_info(xilinx_desc *desc)
 	return FPGA_SUCCESS;
 }

-
 /* ------------------------------------------------------------------------- */
 /* Spartan-II Slave Parallel Generic Implementation */

@@ -285,7 +284,6 @@ static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }

-
 /* ------------------------------------------------------------------------- */

 static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
@@ -91,7 +91,6 @@ static int spartan3_info(xilinx_desc *desc)
 	return FPGA_SUCCESS;
 }

-
 /* ------------------------------------------------------------------------- */
 /* Spartan-II Slave Parallel Generic Implementation */

@@ -293,7 +292,6 @@ static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }

-
 /* ------------------------------------------------------------------------- */

 static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
@@ -59,7 +59,6 @@ static int altera_pio_get_value(struct udevice *dev, unsigned pin)
 	return !!(readl(&regs->data) & (1 << pin));
 }

-
 static int altera_pio_set_value(struct udevice *dev, unsigned pin, int val)
 {
 	struct altera_pio_plat *plat = dev_get_plat(dev);
@@ -39,7 +39,6 @@
 #define PCA957X_INVERT          1
 #define PCA957X_DIRECTION       4

-
 #define PCA_GPIO_MASK           0x00FF
 #define PCA_INT                 0x0100
 #define PCA_PCAL		BIT(9)
@@ -157,7 +157,6 @@ void sunxi_gpio_set_pull_bank(void *bank_base, int pin_offset, u32 val)
 			0x3U << offset, val << offset);
 }

-
 /* =========== Non-DM code, used by the SPL. ============ */

 #if !CONFIG_IS_ENABLED(DM_GPIO)
@@ -76,7 +76,6 @@ DECLARE_GLOBAL_DATA_PTR;
 				 HSI2C_TRANS_ABORT)
 #define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS)

-
 /* I2C_FIFO_STAT Register bits */
 #define HSI2C_RX_FIFO_EMPTY		(1u << 24)
 #define HSI2C_RX_FIFO_FULL		(1u << 23)
@@ -198,7 +198,6 @@ static int uniphier_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 	return 0;
 }

-
 static const struct dm_i2c_ops uniphier_i2c_ops = {
 	.xfer = uniphier_i2c_xfer,
 	.set_bus_speed = uniphier_i2c_set_bus_speed,
@@ -263,7 +263,6 @@ static int bus_i2c_write(struct udevice *bus, u32 chip, u8 *buf, int len)
 	return result;
 }

-
 u32 __weak imx_get_i2cclk(u32 i2c_num)
 {
 	return 0;
@@ -38,7 +38,6 @@ struct i2c_mux_gpio_priv {
 	u32 idle;
 };

-
 static int i2c_mux_gpio_select(struct udevice *dev, struct udevice *bus,
 			       uint channel)
 {
@@ -512,7 +512,6 @@ static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
 	return ret;
 }

-
 static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
 			  int len)
 {
@@ -54,7 +54,6 @@
 #define RCAR_I2C_ICFBSCR		0x38
 #define RCAR_I2C_ICFBSCR_TCYC17		0x0f /* 17*Tcyc */

-
 enum rcar_i2c_type {
 	RCAR_I2C_TYPE_GEN2,
 	RCAR_I2C_TYPE_GEN3,
@@ -96,7 +96,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define I2C_ACK		0		/* PD_SDA level to ack a byte */
 #define I2C_NOACK	1		/* PD_SDA level to noack a byte */

-
 #ifdef DEBUG_I2C
 #define PRINTD(fmt,args...)	do {	\
 		printf (fmt ,##args);	\
@@ -28,7 +28,6 @@ struct cros_ec_keyb_priv {
 	int ghost_filter;		/* 1 to enable ghost filter, else 0 */
 };

-
 /**
 * Check the keyboard controller and return a list of key matrix positions
 * for which a key is pressed
@@ -122,7 +122,6 @@ static int lp5562_led_reg_update(struct udevice *dev, int regnum,
 	else
 		ret = dm_i2c_reg_clrset(dev, regnum, mask, value);

-
 	/*
 	 * Data sheet says "Delay between consecutive I2C writes to
 	 * ENABLE register (00h) need to be longer than 488 us
@@ -521,7 +520,6 @@ U_BOOT_DRIVER(lp5562_led) = {
 	.ops = &lp5562_led_ops,
 };

-
 static int lp5562_led_wrap_probe(struct udevice *dev)
 {
 	struct lp5562_led_wrap_priv *priv = dev_get_priv(dev);
@@ -99,7 +99,6 @@ static int cros_ec_i2c_packet(struct udevice *udev, int out_bytes, int in_bytes)
 		return -EBADMSG;
 	}

-
 	/* drop result and packet_len */
 	memmove(dev->din, &ec_response_i2c->ec_response, in_bytes);

@@ -76,7 +76,6 @@ static int stm32_rcc_bind(struct udevice *dev)
 					    dev_ofnode(dev), &child);
 }

-
 static const struct udevice_id stm32_rcc_ids[] = {
 	{.compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32_rcc_clk_f42x },
 	{.compatible = "st,stm32f469-rcc", .data = (ulong)&stm32_rcc_clk_f469 },
@@ -93,7 +93,6 @@ U_BOOT_DRIVER(aspeed_sdhci_drv) = {
 	.plat_auto	= sizeof(struct aspeed_sdhci_plat),
 };

-
 static int aspeed_sdc_probe(struct udevice *parent)
 {
 	struct clk clk;
@@ -473,7 +473,6 @@ int davinci_mmc_init(struct bd_info *bis, struct davinci_mmc *host)
 }
 #else

-
 static int davinci_mmc_probe(struct udevice *dev)
 {
 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
@@ -55,7 +55,6 @@ static void dwmci_prepare_data(struct dwmci_host *host,
 	unsigned int i = 0, flags, cnt, blk_cnt;
 	ulong data_start, data_end;

-
 	blk_cnt = data->blocks;

 	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
@@ -357,7 +356,6 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 		return -EIO;
 	}

-
 	if (cmd->resp_type & MMC_RSP_PRESENT) {
 		if (cmd->resp_type & MMC_RSP_136) {
 			cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
@@ -850,7 +850,6 @@ __weak int esdhc_status_fixup(void *blob, const char *compat)
 	return 0;
 }

-
 #if CONFIG_IS_ENABLED(DM_MMC)
 static int fsl_esdhc_get_cd(struct udevice *dev);
 static void esdhc_disable_for_no_card(void *blob)
@@ -25,7 +25,6 @@ extern uchar mmc_u_boot_offs[];
 #define MBRDBR_BOOT_SIG_55	0x1fe
 #define MBRDBR_BOOT_SIG_AA	0x1ff

-
 void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst)
 {
 	uint blk_start, blk_cnt, err;
@@ -538,7 +538,6 @@ U_BOOT_DRIVER(mmc_blk) = {
 };
 #endif /* CONFIG_BLK */

-
 UCLASS_DRIVER(mmc) = {
 	.id		= UCLASS_MMC,
 	.name		= "mmc",
@@ -785,7 +785,6 @@ static int mmc_complete_op_cond(struct mmc *mmc)
 	return 0;
 }

-
 int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
 {
 	struct mmc_cmd cmd;
@@ -114,7 +114,6 @@ static int msm_sdc_mci_init(struct msm_sdhc *prv)
 	writel(readl(prv->base + SDCC_MCI_POWER) | SDCC_MCI_POWER_SW_RST,
 	       prv->base + SDCC_MCI_POWER);

-
 	/* Wait for reset to be written to register */
 	if (wait_for_bit_le32(prv->base + SDCC_MCI_STATUS2,
 			      SDCC_MCI_STATUS2_MCI_ACT, false, 10, false)) {
@@ -1631,7 +1631,6 @@ static void msdc_init_hw(struct msdc_host *host)
 	clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
 			3 << SDC_CFG_DTOC_S);

-
 	host->def_tune_para.iocon = readl(&host->base->msdc_iocon);
 	host->def_tune_para.pad_tune = readl(&host->base->pad_tune);
 }
@@ -22,7 +22,6 @@
 #include <log.h>
 #include <mmc.h>

-
 #define PITON_MMC_DUMMY_F_MAX 20000000
 #define PITON_MMC_DUMMY_F_MIN 10000000
 #define PITON_MMC_DUMMY_CAPACITY SZ_4G << 3
@@ -60,7 +60,6 @@ static const char * const rpmb_err_msg[] = {
 	"Authentication key not yet programmed",
 };

-
 /* Structure of RPMB data frame. */
 struct s_rpmb {
 	unsigned char stuff[RPMB_SZ_STUFF];
@@ -80,7 +80,6 @@ static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv,
 {
 	unsigned char ctrl;

-
 	debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
 		bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
 		data->blocksize);
@@ -85,13 +85,11 @@ enum uaddr {
 	MTD_UADDR_UNNECESSARY,		/* Does not require any address */
 };

-
 struct unlock_addr {
 	u32 addr1;
 	u32 addr2;
 };

-
 /*
 * I don't like the fact that the first entry in unlock_addrs[]
 * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore,
@@ -139,7 +137,6 @@ static const struct unlock_addr  unlock_addrs[] = {
 	}
 };

-
 struct amd_flash_info {
 	const __u16 mfr_id;
 	const __u16 dev_id;
@@ -172,7 +172,6 @@ bool mtd_dev_list_updated(void)
 #ifndef __UBOOT__
 static LIST_HEAD(mtd_notifiers);

-
 #define MTD_DEVT(index) MKDEV(MTD_CHAR_MAJOR, (index)*2)

 /* REVISIT once MTD uses the driver model better, whoever allocates
@@ -747,7 +746,6 @@ out:
 }
 EXPORT_SYMBOL_GPL(get_mtd_device);

-
 int __get_mtd_device(struct mtd_info *mtd)
 {
 	int err;
@@ -25,7 +25,6 @@ static struct nand_chip nand_chip;
 					CFG_SYS_NAND_ECCSIZE)
 #define ECCTOTAL	(ECCSTEPS * CFG_SYS_NAND_ECCBYTES)

-
 /*
 * NAND command for large page NAND devices (2k)
 */
@@ -87,7 +86,6 @@ static int nand_command(int block, int page, uint32_t offs,

 	hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);

-
 	/*
 	 * Program and erase have their own busy handlers status, sequential
 	 * in and status need no delay.
@@ -408,7 +408,6 @@ static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size)
 		for (i = 0; i < pktsize/4; i++)
 			bufptr[i] = readl(&info->reg->buf_dataport);

-
 		bufptr += pktsize/4;

 		if (rdcount >= pktnum)
@@ -1012,7 +1012,6 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
 		priv->bufnum_mask = 0;
 		break;

-
 	default:
 		printf("ifc nand: bad csor %#x: bad page size\n", csor);
 		return -ENODEV;
@@ -277,7 +277,6 @@ static inline int mxs_nand_calc_ecc_for_large_oob(struct bch_geometry *geo,
 	max_ecc = min(round_down(max_ecc, 2),
 				nand_info->max_ecc_strength_supported);

-
 	/* search a supported ecc strength that makes bbm */
 	/* located in data chunk  */
 	geo->ecc_strength = chip->ecc_strength_ds;
@@ -90,7 +90,6 @@ static int mxs_nand_dt_probe(struct udevice *dev)

 	info->gpmi_regs = devm_ioremap(dev, res.start, resource_size(&res));

-
 	ret = dev_read_resource_byname(dev, "bch", &res);
 	if (ret)
 		return ret;
@@ -2767,7 +2767,6 @@ out:
 	return ret;
 }

-
 /**
 * nand_write_page_raw - [INTERN] raw page write function
 * @mtd: mtd info structure
@@ -2927,7 +2926,6 @@ static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 	return 0;
 }

-
 /**
 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
 * @mtd:	mtd info structure
@@ -2994,7 +2992,6 @@ static int nand_write_subpage_hwecc(struct mtd_info *mtd,
 	return 0;
 }

-
 /**
 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
 * @mtd: mtd info structure
@@ -22,7 +22,6 @@
 * this file might be covered by the GNU General Public License.
 */

-
 #include <linux/errno.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand_ecc.h>
@@ -19,7 +19,6 @@ static struct nand_chip nand_chip;
 					CFG_SYS_NAND_ECCSIZE)
 #define ECCTOTAL	(ECCSTEPS * CFG_SYS_NAND_ECCBYTES)

-
 #if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
 /*
 * NAND command for small page NAND devices (512)
@@ -153,7 +152,6 @@ static int nand_read_page(int block, int page, uchar *dst)
 	for (i = 0; i < ECCTOTAL; i++)
 		ecc_code[i] = oob_data[nand_ecc_pos[i]];

-
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 		this->ecc.hwctl(mtd, NAND_ECC_READ);
 		this->read_buf(mtd, p, eccsize);
@@ -276,7 +276,6 @@ int nand_get_lock_status(struct mtd_info *mtd, loff_t offset)
 	chipnr = (int)(offset >> chip->chip_shift);
 	chip->select_chip(mtd, chipnr);

-
 	if ((offset & (mtd->writesize - 1)) != 0) {
 		printf("nand_get_lock_status: "
 			"Start address must be beginning of "
@@ -134,7 +134,6 @@ int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count,
 	return 0;
 }

-
 /**
 * elm_config - Configure ELM module
 * @level: 4 / 8 / 16 bit BCH
@@ -34,7 +34,6 @@ enum bch_level {
 	BCH_16_BIT
 };

-
 /* BCH syndrome registers */
 struct syndrome {
 	u32 syndrome_fragment_x[7];	/* 0x400, 0x404.... 0x418 */
@@ -47,7 +47,6 @@
 #define NFC_CTL_PAGE_SIZE_MASK     (0xf << 8)
 #define NFC_CTL_PAGE_SIZE(a)       ((fls(a) - 11) << 8)

-
 #define NFC_ECC_EN                 (1 << 0)
 #define NFC_ECC_PIPELINE           (1 << 3)
 #define NFC_ECC_EXCEPTION          (1 << 4)
@@ -55,7 +54,6 @@
 #define NFC_ECC_RANDOM_EN          (1 << 9)
 #define NFC_ECC_RANDOM_DIRECTION   (1 << 10)

-
 #define NFC_ADDR_NUM_OFFSET        16
 #define NFC_SEND_ADDR              (1 << 19)
 #define NFC_ACCESS_DIR             (1 << 20)
@@ -679,7 +679,6 @@ static int nand_write_page_hwecc(struct mtd_info *mtd,
 	return 0;
 }

-
 /**
 * Read raw page data without ecc
 *
@@ -51,7 +51,6 @@
 				(0x5 << 0))	/* t_rc from nand_cycles */
 #endif

-
 #define ZYNQ_NAND_DIRECT_CMD	((0x4 << 23) |	/* Chip 0 from interface 1 */ \
 				(0x2 << 21))	/* UpdateRegs operation */

@@ -11,10 +11,8 @@
 #endif
 #include <linux/mtd/spinand.h>

-
 #define SPINAND_MFR_PARAGON	0xa1

-
 #define PN26G0XA_STATUS_ECC_BITMASK		(3 << 4)

 #define PN26G0XA_STATUS_ECC_NONE_DETECTED	(0 << 4)
@@ -22,7 +20,6 @@
 #define PN26G0XA_STATUS_ECC_ERRORED		(2 << 4)
 #define PN26G0XA_STATUS_ECC_8_CORRECTED		(3 << 4)

-
 static SPINAND_OP_VARIANTS(read_cache_variants,
 		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
 		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
@@ -39,7 +36,6 @@ static SPINAND_OP_VARIANTS(update_cache_variants,
 		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
 		SPINAND_PROG_LOAD(false, 0, NULL, 0));

-
 static int pn26g0xa_ooblayout_ecc(struct mtd_info *mtd, int section,
 				   struct mtd_oob_region *region)
 {
@@ -97,7 +93,6 @@ static const struct mtd_ooblayout_ops pn26g0xa_ooblayout = {
 	.rfree = pn26g0xa_ooblayout_free,
 };

-
 static const struct spinand_info paragon_spinand_table[] = {
 	SPINAND_INFO("PN26G01A",
 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe1),
@@ -503,7 +503,6 @@ static int onenand_wait(struct mtd_info *mtd, int state)
 		return -EIO;
 	}

-
 	return 0;
 }

@@ -1278,7 +1277,6 @@ int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from,
 	return ret;
 }

-
 #ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
 /**
 * onenand_verify_oob - [GENERIC] verify the oob contents after a write
@@ -1720,7 +1718,6 @@ static int onenand_block_isbad_nolock(struct mtd_info *mtd, loff_t ofs, int allo
 	return bbm->isbad_bbt(mtd, ofs, allowbbt);
 }

-
 /**
 * onenand_erase - [MTD Interface] erase block(s)
 * @param mtd		MTD device structure
@@ -2128,7 +2125,6 @@ static void onenand_unlock_all(struct mtd_info *mtd)
 	onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK);
 }

-
 /**
 * onenand_check_features - Check and set OneNAND features
 * @param mtd           MTD data structure
@@ -361,7 +361,6 @@ static int rpc_hf_probe(struct udevice *dev)
 	if (addrc != 2 || sizec != 2)
 		return -EINVAL;

-
 	ret = clk_get_by_index(dev, 0, &clk);
 	if (ret < 0) {
 		dev_err(dev, "Failed to get RPC clock\n");
@@ -79,7 +79,6 @@ extern const struct flash_info spi_nor_ids[];
 /* Get software write-protect value (BP bits) */
 int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash);

-
 #if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
 int spi_flash_mtd_register(struct spi_flash *flash);
 void spi_flash_mtd_unregister(struct spi_flash *flash);
@@ -1275,7 +1275,6 @@ int ubi_init(void)
 	if (err)
 		goto out_slab;

-
 	/* Attach MTD devices */
 	for (i = 0; i < mtd_devs; i++) {
 		struct mtd_dev_param *p = &mtd_dev_param[i];
@@ -105,7 +105,6 @@ size_t ubi_calc_fm_size(struct ubi_device *ubi)
 	return roundup(size, ubi->leb_size);
 }

-
 /**
 * new_fm_vhdr - allocate a new volume header for fastmap usage.
 * @ubi: UBI device description object
@@ -680,7 +679,6 @@ static int ubi_attach_fastmap(struct ubi_device *ubi,
 		goto fail_bad;
 	}

-
 	if (fm->max_pool_size > UBI_FM_MAX_POOL_SIZE ||
 	    fm->max_pool_size < 0) {
 		ubi_err(ubi, "bad maximal pool size: %i", fm->max_pool_size);
@@ -1241,7 +1239,6 @@ static int ubi_write_fastmap(struct ubi_device *ubi,
 	}
 	fmh->scrub_peb_count = cpu_to_be32(scrub_peb_count);

-
 	list_for_each_entry(ubi_wrk, &ubi->works, list) {
 		if (ubi_is_erase_work(ubi_wrk)) {
 			wl_e = ubi_wrk->e;
@@ -18,7 +18,6 @@
 #define GMAC0_INTR_RECV_LAZY_ADDR	(GMAC0_REG_BASE + 0x100)
 #define GMAC0_PHY_CTRL_ADDR		(GMAC0_REG_BASE + 0x188)

-
 #define GMAC_DMA_PTR_OFFSET		0x04
 #define GMAC_DMA_ADDR_LOW_OFFSET	0x08
 #define GMAC_DMA_ADDR_HIGH_OFFSET	0x0c
@@ -3,7 +3,6 @@
 * Copyright 2019-2021 Broadcom.
 */

-
 #include <asm/io.h>
 #include <dm.h>
 #include <linux/delay.h>
@@ -64,7 +64,6 @@ struct eth_mac_regs {
 #define MII_REGMSK		(0x1F << 6)
 #define MII_ADDRMSK		(0x1F << 11)

-
 struct eth_dma_regs {
 	u32 busmode;		/* 0x00 */
 	u32 txpolldemand;	/* 0x04 */
@@ -7,10 +7,8 @@ tested on both gig copper and gig fiber boards
 ***************************************************************************/
 /*******************************************************************************

-
  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.

-
  Contact Information:
  Linux NICS <linux.nics@intel.com>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
@@ -1742,7 +1740,6 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw)
 		reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
 		E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);

-
 		switch (hw->mac_type) {
 		case e1000_igb:			/* IGB is cool */
 			return;
@@ -2594,7 +2591,6 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
 				return ret_val;
 		}

-
 	} else {

 		if (hw->mac_type == e1000_ich8lan) {
@@ -5216,7 +5212,6 @@ e1000_configure_tx(struct e1000_hw *hw)
 		E1000_WRITE_REG(hw, TARC1, tarc);
 	}

-
 	e1000_config_collision_dist(hw);
 	/* Setup Transmit Descriptor Settings for eop descriptor */
 	hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
@@ -5227,7 +5222,6 @@ e1000_configure_tx(struct e1000_hw *hw)
 	else
 		hw->txd_cmd |= E1000_TXD_CMD_RS;

-
 	if (hw->mac_type == e1000_igb) {
 		E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);

@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*******************************************************************************

-
  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  Copyright 2011 Freescale Semiconductor, Inc.

@@ -402,7 +401,6 @@ struct e1000_phy_stats {
 							off */
 #define IFE_PSCL_PROBE_LEDS_ON               0x0007  /* Force LEDs 0 and 2 on */

-
 #define NUM_DEV_IDS 16

 #define NODE_ADDRESS_SIZE 6
@@ -1069,7 +1067,6 @@ typedef enum {
    e1000_ffe_config_blocked
 } e1000_ffe_config;

-
 /* Structure containing variables used by the shared code (e1000_hw.c) */
 struct e1000_hw {
 	const char *name;
@@ -2128,7 +2125,6 @@ struct e1000_hw {
 /* In-Band Control Register (Page 194, Register 18) */
 #define GG82563_ICR_DIS_PADDING		0x0010 /* Disable Padding Use */

-
 /* Bits...
 * 15-5: page
 * 4-0: register offset
@@ -218,7 +218,6 @@ void qbman_eq_desc_set_response(struct qbman_eq_desc *d,
 	qb_attr_code_encode(&code_eq_rsp_stash, cl, !!stash);
 }

-
 void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, uint32_t qdid,
 			  uint32_t qd_bin, uint32_t qd_prio)
 {
@@ -365,7 +364,6 @@ static struct qb_attr_code code_dqrr_stat = QB_CODE(0, 8, 8);
 #define QBMAN_DQRR_RESPONSE_BPSCN     0x29
 #define QBMAN_DQRR_RESPONSE_CSCN_WQ   0x2a

-
 /* NULL return if there are no unconsumed DQRR entries. Returns a DQRR entry
 * only once, so repeated calls can return a sequence of DQRR entries, without
 * requiring they be consumed immediately or in any particular order. */
@@ -16,7 +16,6 @@
 #define QBMAN_VER_4_0_DQRR_SIZE 4
 #define QBMAN_VER_4_1_DQRR_SIZE 8

-
 /* --------------------- */
 /* portal data structure */
 /* --------------------- */
@@ -130,7 +129,6 @@ static inline uint32_t qb_attr_code_decode(const struct qb_attr_code *code,
 	return d32_uint32_t(code->lsoffset, code->width, cacheline[code->word]);
 }

-
 /* encode a field to a cacheline */
 static inline void qb_attr_code_encode(const struct qb_attr_code *code,
 				       uint32_t *cacheline, uint32_t val)
@@ -101,7 +101,6 @@ static int _ftmac100_init(struct ftmac100_data *priv, unsigned char enetaddr[6])
 	/* set the ethernet address */
 	ftmac100_set_mac(priv, enetaddr);

-
 	/* disable all interrupts */

 	writel (0, &ftmac100->imr);
@@ -51,7 +51,6 @@ struct rk_gmac_ops {
 	void (*set_to_rgmii)(struct gmac_rockchip_plat *pdata);
 };

-
 static int gmac_rockchip_of_to_plat(struct udevice *dev)
 {
 	struct gmac_rockchip_plat *pdata = dev_get_plat(dev);
@@ -114,7 +114,6 @@
 #define TXSR_TXFID_SHIFT		(0)
 #define TXSR_TXFID_GET(_v)		(((_v) >> 0) & 0x3f)

-
 #define KS_RXCR1			0x74
 #define RXCR1_FRXQ			(1 << 15)
 #define RXCR1_RXUDPFCC			(1 << 14)
--- a/Show More
+++ b/Show More