video: add MT8183 scanout driver for firmware-initialized displays
Add a display driver for the MT8183 kukui family of ChromeOS devices (e.g. the Lenovo IdeaPad Duet, google,krane), where the display pipeline is already initialized and running when the payload is handed off by depthcharge. depthcharge's display_cleanup() stops the overlay engines and turns the backlight off before the jump, so the driver only revives the pipeline: it re-enables the OVL0 engines (OVL_EN @ +0x000c and OVL0_2L_EN @ +0x100c, offsets from depthcharge's device-era mtk_ddp.c), drives the backlight GPIOs high (DISP_PWM, pin 43, and EN_LCD_BL, pin 176, through the GPIO controller dout block at 0x10005000+0x100), and renders the console into the live scanout surface. The geometry comes from the coreboot table framebuffer record, which sits at the fixed kukui address 0xffed9000; when its physical_address is 0 (what upstream coreboot 4.14 publishes on kukui), the live scanout address is taken from the OVL layer 0 address register (+0x0f40), which the firmware leaves in place across the handoff. The driver binds to the existing ovl0 device tree node (mediatek,mt8183-disp-ovl) and requires no display initialization.
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vhaudiquet
@@ -1022,6 +1022,19 @@ config VIDEO_MCDE_SIMPLE
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before u-boot starts, and u-boot will simply render to the pre-
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allocated frame buffer surface.
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config VIDEO_MT8183_SCANOUT
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bool "Enable MT8183 scanout driver for firmware-initialized displays"
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depends on ARCH_MEDIATEK
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help
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Enables a display driver for the MediaTek MT8183 on boards where
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the display pipeline has already been initialized by the boot
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firmware (e.g. ChromeOS coreboot + depthcharge on the kukui
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family). The driver revives the overlay engines and backlight that
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the firmware disables before handoff, discovers the live scanout
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surface from the coreboot table (with a fallback to the overlay
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layer address register), and lets the standard vidconsole render
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into it. No display initialization is performed.
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config OSD
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bool "Enable OSD support"
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depends on DM
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@@ -80,6 +80,7 @@ obj-$(CONFIG_VIDEO_LCD_SAMSUNG_S6E63M0) += samsung-s6e63m0.o
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obj-$(CONFIG_VIDEO_MCDE_SIMPLE) += mcde_simple.o
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obj-${CONFIG_VIDEO_MESON} += meson/
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obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_dsi.o
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obj-$(CONFIG_VIDEO_MT8183_SCANOUT) += mt8183_scanout.o
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obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o
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obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
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obj-$(CONFIG_VIDEO_NX) += nexell_display.o videomodes.o nexell/
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@@ -0,0 +1,223 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* MT8183 display scanout driver for firmware-initialized pipelines.
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*
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* On the MT8183 kukui family of ChromeOS devices (e.g. the Lenovo IdeaPad
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* Duet, "google,krane"), the display pipeline (MMSYS -> OVL0 -> OVL0_2L ->
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* RDMA -> COLOR -> DSI -> panel) is fully initialized and running by the
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* time control is passed to the next boot stage: coreboot (through
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* libpayload/depthcharge) sets up the panel and programs the overlay scanout
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* address. The payload, however, is handed over with the pipeline STOPPED:
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* depthcharge's display_cleanup() disables the overlay engines and turns the
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* backlight off right before jumping to the payload.
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*
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* This driver does not initialize any display hardware. It only revives the
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* pipeline (re-enabling the overlay engines and the backlight), discovers
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* the geometry and the live scanout address from the coreboot table
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* framebuffer record (falling back to the OVL L0 layer address register,
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* which still holds the address depthcharge used), and hands the surface to
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* the video uclass so the standard vidconsole can render into it.
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*/
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#include <dm.h>
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#include <video.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/unaligned.h>
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#include <linux/kernel.h>
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#include <linux/sizes.h>
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/*
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* OVL0 register offsets. Source: Linux drivers/gpu/drm/mediatek/
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* mtk_disp_ovl.c (DISP_REG_OVL_EN) and device-era depthcharge
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* src/drivers/video/mtk_ddp.c (ChromeOS R93, the generation shipped on
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* kukui); both agree on 0x000c for OVL_EN. The 2L sub-engine enable
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* (DISP_REG_OVL0_2L_EN) lives in the same register block on MT8183.
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* The layer-0 source address register (DISP_REG_OVL_L0_ADDR) is not reset
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* by depthcharge's stop() and holds the live scanout address.
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*/
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#define DISP_REG_OVL_L0_ADDR 0x0f40
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#define DISP_REG_OVL_EN 0x000c
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#define DISP_REG_OVL0_2L_EN 0x100c
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/*
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* Backlight GPIOs. The MT8183 GPIO controller is at 0x10005000; the dout
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* block starts at +0x100 with 16 bytes per 32-pin group and set@+4 (layout
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* of GpioRegs/GpioValRegs in device-era depthcharge src/drivers/gpio/
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* mt8183.h). On kukui the backlight is driven by two dedicated GPIOs:
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* DISP_PWM (pin 43) and EN_LCD_BL (PERIPHERAL_EN13, pin 176); depthcharge's
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* kukui_backlight_update() drives both high to turn the backlight on.
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*/
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#define MTK_GPIO_BASE 0x10005000
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#define MTK_GPIO_DOUT_SET(pin) (MTK_GPIO_BASE + 0x100 + ((pin) / 32) * 16 + 4)
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#define MTK_GPIO_DOUT_BIT(pin) BIT((pin) % 32)
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#define PAD_DISP_PWM 43
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#define PAD_EN_LCD_BL 176
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/*
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* The coreboot table sits at a fixed address on kukui: 0xffed9000, size
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* 0x380 (coreboot memlayout; confirmed on the device through
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* /sys/firmware/fdt and the coreboot sysfs tags). It is deliberately
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* hardcoded here rather than read from the handoff DTB: on this platform
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* the FDT pointer passed at entry cannot be relied upon, and U-Boot boots
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* with its own embedded control DTB which has no /firmware/coreboot node.
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*/
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#define COREBOOT_TABLE_ADDR 0xffed9000
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#define LB_TAG_FRAMEBUFFER 0x12
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/*
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* Layout from coreboot src/commonlib/include/commonlib/coreboot_tables.h:
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* struct lb_header: sig[4] "LBIO", header_bytes, header_checksum,
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* table_bytes, table_checksum, table_entries (LE u32)
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* struct lb_record: tag, size
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* struct lb_framebuffer (record payload):
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* physical_address @8 (4-byte-aligned LE u64), x_resolution @16,
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* y_resolution @20, bytes_per_line @24, bits_per_pixel @28,
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* red_pos/size @29/30, green @31/32, blue @33/34,
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* reserved @35/36, orientation @37, flags @38, pad @39; size 40.
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*
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* physical_address == 0 is legitimate: upstream coreboot 4.14 (the
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* generation shipped on kukui) publishes the framebuffer record with
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* fb_addr=0. The live scanout address then comes from OVL_L0_ADDR.
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*/
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struct lb_framebuffer {
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u32 tag;
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u32 size;
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u64 physical_address;
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u32 x_resolution;
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u32 y_resolution;
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u32 bytes_per_line;
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u8 bits_per_pixel;
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u8 red_pos;
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u8 red_size;
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u8 green_pos;
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u8 green_size;
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u8 blue_pos;
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u8 blue_size;
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u8 reserved_pos;
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u8 reserved_size;
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};
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static int find_framebuffer(u64 table, struct lb_framebuffer *fb)
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{
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void *base = (void *)(uintptr_t)table;
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u32 header_bytes, entries, i;
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void *rec;
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if (get_unaligned_le32(base) != 0x4f49424c) /* "LBIO" */
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return -ENOENT;
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header_bytes = get_unaligned_le32(base + 4);
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entries = get_unaligned_le32(base + 20);
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if (header_bytes < 24 || header_bytes > 4096 ||
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entries == 0 || entries > 4096)
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return -EINVAL;
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rec = base + header_bytes;
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for (i = 0; i < entries; i++) {
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u32 tag = get_unaligned_le32(rec);
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u32 rsize = get_unaligned_le32(rec + 4);
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if (rsize < 8)
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return -EINVAL;
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if (tag == LB_TAG_FRAMEBUFFER) {
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if (rsize < sizeof(*fb))
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return -EINVAL;
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memcpy(fb, rec, sizeof(*fb));
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fb->physical_address =
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get_unaligned_le64(rec + 8);
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return 0;
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}
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rec += rsize;
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}
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return -ENOENT;
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}
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static int mt8183_scanout_probe(struct udevice *dev)
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{
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struct video_uc_plat *plat = dev_get_uclass_plat(dev);
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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struct lb_framebuffer fb;
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fdt_addr_t ovl;
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u64 addr;
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int ret;
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ovl = dev_read_addr(dev);
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if (ovl == FDT_ADDR_T_NONE)
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return log_msg_ret("ovl", -EINVAL);
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/*
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* Revive the pipeline: undo depthcharge's display_cleanup() by
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* re-enabling the overlay engines and driving the backlight GPIOs
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* high. No panel or DSI re-initialization is needed: the panel is
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* powered and the DSI link stays up through the handoff.
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*/
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writel(1, ovl + DISP_REG_OVL_EN);
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writel(1, ovl + DISP_REG_OVL0_2L_EN);
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writel(MTK_GPIO_DOUT_BIT(PAD_DISP_PWM),
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(void __iomem *)MTK_GPIO_DOUT_SET(PAD_DISP_PWM));
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writel(MTK_GPIO_DOUT_BIT(PAD_EN_LCD_BL),
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(void __iomem *)MTK_GPIO_DOUT_SET(PAD_EN_LCD_BL));
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/*
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* The coreboot table sits above the DRAM window described by the
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* control DTB; map it before parsing.
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*/
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mmu_map_region(COREBOOT_TABLE_ADDR, SZ_4K, false);
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ret = find_framebuffer(COREBOOT_TABLE_ADDR, &fb);
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if (ret)
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return log_msg_ret("lbio", ret);
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if (fb.bits_per_pixel != 32 || fb.red_pos != 16 || fb.red_size != 8 ||
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fb.green_pos != 8 || fb.green_size != 8 ||
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fb.blue_pos != 0 || fb.blue_size != 8)
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return log_msg_ret("fmt", -ENOTSUPP);
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/*
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* Use the address from the coreboot table when it is a plausible
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* DRAM address (>= 1 GiB), otherwise fall back to the address the
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* firmware actually programmed into the overlay, which it left in
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* place across the handoff.
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*/
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addr = fb.physical_address;
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if (addr < SZ_1G)
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addr = readl(ovl + DISP_REG_OVL_L0_ADDR);
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if (addr < SZ_1G)
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return log_msg_ret("scanout", -ENODEV);
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plat->base = addr;
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plat->size = fb.bytes_per_line * fb.y_resolution;
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/* The scanout surface is above the DTB DRAM window: map it. */
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mmu_map_region(plat->base, ALIGN(plat->size, SZ_4K), false);
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video_set_flush_dcache(dev, true);
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uc_priv->bpix = VIDEO_BPP32;
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uc_priv->xsize = fb.x_resolution;
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uc_priv->ysize = fb.y_resolution;
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uc_priv->line_length = fb.bytes_per_line;
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printf("Video: MT8183 scanout %dx%d@32bpp at %llx\n",
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uc_priv->xsize, uc_priv->ysize, (unsigned long long)plat->base);
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return 0;
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}
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static const struct udevice_id mt8183_scanout_ids[] = {
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{ .compatible = "mediatek,mt8183-disp-ovl" },
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{ }
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};
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U_BOOT_DRIVER(mt8183_scanout) = {
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.name = "mt8183_scanout",
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.id = UCLASS_VIDEO,
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.of_match = mt8183_scanout_ids,
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.probe = mt8183_scanout_probe,
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};
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