arm: dts: agilex5: Enabled cdns-nand dts setting

Enable cdns-nand dts setting for the socfpga_agilex5
family device.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>

arch/arm/dts/socfpga_agilex5.dtsi

@@ -330,6 +330,20 @@
 			status = "disabled";
 		};
 
+		nand: nand@10b80000 {
+			compatible = "cdns,nand";
+			reg = <0x10b80000 0x10000>,
+				<0x10840000 0x1000>;
+			reg-names = "reg", "sdma";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 97 4>;
+			clocks = <&clkmgr AGILEX5_NAND_CLK>;
+			resets = <&rst NAND_RESET>, <&rst COMBOPHY_RESET>;
+			cdns,board-delay-ps = <4830>;
+			status = "disabled";
+		};
+
 		ocram: sram@00000000 {
 			compatible = "mmio-sram";
 			reg = <0x00000000 0x200000>;

arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi

@@ -41,6 +41,10 @@
 	/delete-property/ cdns,read-delay;
 };
 
+&flash1 {
+	bootph-all;
+};
+
 &i3c0 {
 	bootph-all;
 };
@@ -102,6 +106,10 @@
 	status = "okay";
 };
 
+&nand {
+	bootph-all;
+};
+
 &timer0 {
 	bootph-all;
 };
@@ -121,4 +129,3 @@
 &watchdog0 {
 	bootph-all;
 };
-

arch/arm/dts/socfpga_agilex5_socdk.dts

@@ -161,3 +161,22 @@
 		};
 	};
 };
+
+&nand {
+	status = "okay";
+
+	flash1: flash@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "u-boot";
+			reg = <0 0x200000>;
+		};
+		partition@200000 {
+			label = "root";
+			reg = <0x200000 0x3fe00000>;
+		};
+	};
+};