Revert "arm64: Use level-2 for largest block mappings when FEAT_HAFDBS is present"

This reverts commit 836b8d4b20. This is
part of a series trying to make use of the arm64 hardware features for
tracking dirty pages. Unfortunately this series causes problems for the
AC5/AC5X SoCs. Having exhausted other options the consensus seems to be
reverting this series is the best course of action.

Signed-off-by: Chris Packham <judge.packham@gmail.com>

arch/arm/cpu/armv8/cache_v8.c

@@ -314,7 +314,7 @@ static void map_range(u64 virt, u64 phys, u64 size, int level,
 	for (i = idx; size; i++) {
 		u64 next_size, *next_table;
 
-		if (level >= gd->arch.first_block_level &&
+		if (level >= 1 &&
 		    size >= map_size && !(virt & (map_size - 1))) {
 			if (level == 3)
 				table[i] = phys | attrs | PTE_TYPE_PAGE;
@@ -353,9 +353,6 @@ static void add_map(struct mm_region *map)
 	if (va_bits < 39)
 		level = 1;
 
-	if (!gd->arch.first_block_level)
-		gd->arch.first_block_level = 1;
-
 	if (gd->arch.has_hafdbs)
 		attrs |= PTE_DBM | PTE_RDONLY;
 
@@ -372,7 +369,7 @@ static void count_range(u64 virt, u64 size, int level, int *cntp)
 	for (i = idx; size; i++) {
 		u64 next_size;
 
-		if (level >= gd->arch.first_block_level &&
+		if (level >= 1 &&
 		    size >= map_size && !(virt & (map_size - 1))) {
 			virt += map_size;
 			size -= map_size;
@@ -413,13 +410,10 @@ __weak u64 get_page_table_size(void)
 	u64 size, mmfr1;
 
 	asm volatile("mrs %0, id_aa64mmfr1_el1" : "=r" (mmfr1));
-	if ((mmfr1 & 0xf) == 2) {
+	if ((mmfr1 & 0xf) == 2)
 		gd->arch.has_hafdbs = true;
-		gd->arch.first_block_level = 2;
-	} else {
+	else
 		gd->arch.has_hafdbs = false;
-		gd->arch.first_block_level = 1;
-	}
 
 	/* Account for all page tables we would need to cover our memory map */
 	size = one_pt * count_ranges();

arch/arm/include/asm/global_data.h

@@ -52,7 +52,6 @@ struct arch_global_data {
 #if defined(CONFIG_ARM64)
 	unsigned long tlb_fillptr;
 	unsigned long tlb_emerg;
-	unsigned int first_block_level;
 	bool has_hafdbs;
 #endif
 #endif