Merge branch 'master-779h0-r2' of https://source.denx.de/u-boot/custodians/u-boot-sh
This commit is contained in:
Tom Rini
@@ -1172,7 +1172,8 @@ dtb-$(CONFIG_RCAR_GEN3) += \
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dtb-$(CONFIG_RCAR_GEN4) += \
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r8a779a0-falcon-u-boot.dtb \
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r8a779f0-spider-u-boot.dtb \
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r8a779g0-white-hawk-u-boot.dtb
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r8a779g0-white-hawk-u-boot.dtb \
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r8a779h0-gray-hawk-u-boot.dtb
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dtb-$(CONFIG_TARGET_RZG2L) += \
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r9a07g044l2-smarc.dts
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@@ -0,0 +1,166 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the Gray Hawk CPU board
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*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include "r8a779h0.dtsi"
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/ {
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model = "Renesas Gray Hawk CPU board";
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compatible = "renesas,grayhawk-cpu", "renesas,r8a779h0";
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aliases {
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ethernet0 = &avb0;
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serial0 = &hscif0;
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};
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chosen {
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bootargs = "ignore_loglevel";
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stdout-path = "serial0:921600n8";
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};
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0x78000000>;
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};
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memory@480000000 {
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device_type = "memory";
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reg = <0x4 0x80000000 0x1 0x80000000>;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&avb0 {
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pinctrl-0 = <&avb0_pins>;
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pinctrl-names = "default";
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phy-handle = <&phy0>;
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tx-internal-delay-ps = <2000>;
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status = "okay";
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phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-id0022.1622",
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"ethernet-phy-ieee802.3-c22";
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rxc-skew-ps = <1500>;
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reg = <0>;
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interrupt-parent = <&gpio7>;
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interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
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};
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};
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&extal_clk {
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clock-frequency = <16666666>;
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};
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&extalr_clk {
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clock-frequency = <32768>;
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};
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&hscif0 {
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uart-has-rtscts;
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status = "okay";
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};
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&i2c0 {
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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status = "okay";
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clock-frequency = <400000>;
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eeprom@50 {
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compatible = "rohm,br24g01", "atmel,24c01";
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label = "cpu-board";
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reg = <0x50>;
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pagesize = <8>;
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};
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};
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&mmc0 {
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pinctrl-0 = <&mmc_pins>;
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pinctrl-1 = <&mmc_pins>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_1p8v>;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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bus-width = <8>;
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no-sd;
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no-sdio;
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non-removable;
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full-pwr-cycle-in-suspend;
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status = "okay";
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};
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&pfc {
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pinctrl-0 = <&scif_clk_pins>;
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pinctrl-names = "default";
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avb0_pins: avb0 {
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mux {
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groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
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"avb0_txcrefclk";
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function = "avb0";
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};
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pins_mdio {
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groups = "avb0_mdio";
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drive-strength = <21>;
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};
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pins_mii {
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groups = "avb0_rgmii";
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drive-strength = <21>;
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};
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};
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hscif0_pins: hscif0 {
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groups = "hscif0_data", "hscif0_ctrl";
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function = "hscif0";
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};
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i2c0_pins: i2c0 {
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groups = "i2c0";
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function = "i2c0";
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};
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mmc_pins: mmc {
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groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
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function = "mmc";
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power-source = <1800>;
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};
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scif_clk_pins: scif_clk {
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groups = "scif_clk";
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function = "scif_clk";
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};
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};
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&scif_clk {
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clock-frequency = <24000000>;
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};
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@@ -0,0 +1,15 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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||||
/*
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* Device Tree Source for the R-Car V4M Gray Hawk CSI/DSI sub-board
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*
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||||
* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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&i2c0 {
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eeprom@52 {
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compatible = "rohm,br24g01", "atmel,24c01";
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label = "csi-dsi-sub-board-id";
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reg = <0x52>;
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pagesize = <8>;
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};
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};
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@@ -0,0 +1,15 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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||||
/*
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* Device Tree Source for the R-Car V4M Gray Hawk Ethernet sub-board
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*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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&i2c0 {
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eeprom@53 {
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compatible = "rohm,br24g01", "atmel,24c01";
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label = "ethernet-sub-board-id";
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reg = <0x53>;
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pagesize = <8>;
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};
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};
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@@ -0,0 +1,42 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source extras for U-Boot for the Gray Hawk board
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*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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#include "r8a779h0-gray-hawk.dts"
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#include "r8a779h0-u-boot.dtsi"
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/ {
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aliases {
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spi0 = &rpc;
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};
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};
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&pfc {
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qspi0_pins: qspi0 {
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groups = "qspi0_ctrl", "qspi0_data4";
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function = "qspi0";
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};
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};
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&rpc {
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pinctrl-0 = <&qspi0_pins>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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spi-max-frequency = <40000000>;
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status = "okay";
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "s25fs512s", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <40000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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};
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};
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@@ -0,0 +1,25 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the Gray Hawk CPU and BreakOut boards
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*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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/dts-v1/;
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#include "r8a779h0-gray-hawk-cpu.dtsi"
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#include "r8a779h0-gray-hawk-csi-dsi.dtsi"
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#include "r8a779h0-gray-hawk-ethernet.dtsi"
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/ {
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model = "Renesas Gray Hawk CPU and Breakout boards based on r8a779h0";
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compatible = "renesas,gray-hawk-breakout", "renesas,gray-hawk-cpu", "renesas,r8a779h0";
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};
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&i2c0 {
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eeprom@51 {
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compatible = "rohm,br24g01", "atmel,24c01";
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label = "breakout-board";
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reg = <0x51>;
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pagesize = <8>;
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};
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};
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@@ -0,0 +1,27 @@
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// SPDX-License-Identifier: GPL-2.0
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||||
/*
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* Device Tree Source extras for U-Boot on R-Car R8A779H0 SoC
|
||||
*
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||||
* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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||||
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#include "r8a779x-u-boot.dtsi"
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/ {
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soc {
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rpc: spi@ee200000 {
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compatible = "renesas,r8a779h0-rpc-if", "renesas,rcar-gen4-rpc-if";
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reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>;
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 629>;
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||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 629>;
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||||
bank-width = <2>;
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||||
num-cs = <1>;
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||||
status = "disabled";
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};
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};
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};
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&extalr_clk {
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bootph-all;
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};
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@@ -0,0 +1,460 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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||||
* Device Tree Source for the R-Car V4M (R8A779H0) SoC
|
||||
*
|
||||
* Copyright (C) 2023 Renesas Electronics Corp.
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||||
*/
|
||||
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||||
#include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/renesas,r8a779h0-sysc.h>
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||||
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||||
/ {
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||||
compatible = "renesas,r8a779h0";
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||||
#address-cells = <2>;
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||||
#size-cells = <2>;
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||||
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||||
cpus {
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||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
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||||
a76_0: cpu@0 {
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||||
compatible = "arm,cortex-a76";
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||||
reg = <0>;
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||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A779H0_PD_A1E0D0C0>;
|
||||
};
|
||||
};
|
||||
|
||||
extal_clk: extal-clk {
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||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
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||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
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||||
extalr_clk: extalr-clk {
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||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
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||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
pmu-a76 {
|
||||
compatible = "arm,cortex-a76-pmu";
|
||||
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
/* External SCIF clock - to be overridden by boards that provide it */
|
||||
scif_clk: scif-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
pfc: pinctrl@e6050000 {
|
||||
compatible = "renesas,pfc-r8a779h0";
|
||||
reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
|
||||
<0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
|
||||
<0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
|
||||
<0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>;
|
||||
};
|
||||
|
||||
gpio0: gpio@e6050180 {
|
||||
compatible = "renesas,gpio-r8a779h0",
|
||||
"renesas,rcar-gen4-gpio";
|
||||
reg = <0 0xe6050180 0 0x54>;
|
||||
interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 0 19>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 915>;
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 915>;
|
||||
};
|
||||
|
||||
gpio1: gpio@e6050980 {
|
||||
compatible = "renesas,gpio-r8a779h0",
|
||||
"renesas,rcar-gen4-gpio";
|
||||
reg = <0 0xe6050980 0 0x54>;
|
||||
interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 32 30>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 915>;
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 915>;
|
||||
};
|
||||
|
||||
gpio2: gpio@e6058180 {
|
||||
compatible = "renesas,gpio-r8a779h0",
|
||||
"renesas,rcar-gen4-gpio";
|
||||
reg = <0 0xe6058180 0 0x54>;
|
||||
interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 64 20>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 916>;
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 916>;
|
||||
};
|
||||
|
||||
gpio3: gpio@e6058980 {
|
||||
compatible = "renesas,gpio-r8a779h0",
|
||||
"renesas,rcar-gen4-gpio";
|
||||
reg = <0 0xe6058980 0 0x54>;
|
||||
interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 96 32>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 916>;
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 916>;
|
||||
};
|
||||
|
||||
gpio4: gpio@e6060180 {
|
||||
compatible = "renesas,gpio-r8a779h0",
|
||||
"renesas,rcar-gen4-gpio";
|
||||
reg = <0 0xe6060180 0 0x54>;
|
||||
interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 128 25>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
};
|
||||
|
||||
gpio5: gpio@e6060980 {
|
||||
compatible = "renesas,gpio-r8a779h0",
|
||||
"renesas,rcar-gen4-gpio";
|
||||
reg = <0 0xe6060980 0 0x54>;
|
||||
interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 160 21>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
};
|
||||
|
||||
gpio6: gpio@e6061180 {
|
||||
compatible = "renesas,gpio-r8a779h0",
|
||||
"renesas,rcar-gen4-gpio";
|
||||
reg = <0 0xe6061180 0 0x54>;
|
||||
interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 192 21>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
};
|
||||
|
||||
gpio7: gpio@e6061980 {
|
||||
compatible = "renesas,gpio-r8a779h0",
|
||||
"renesas,rcar-gen4-gpio";
|
||||
reg = <0 0xe6061980 0 0x54>;
|
||||
interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 224 21>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
};
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a779h0-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x4000>;
|
||||
clocks = <&extal_clk>, <&extalr_clk>;
|
||||
clock-names = "extal", "extalr";
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
compatible = "renesas,r8a779h0-rst";
|
||||
reg = <0 0xe6160000 0 0x4000>;
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,r8a779h0-sysc";
|
||||
reg = <0 0xe6180000 0 0x4000>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
compatible = "renesas,i2c-r8a779h0",
|
||||
"renesas,rcar-gen4-i2c";
|
||||
reg = <0 0xe6500000 0 0x40>;
|
||||
interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 518>;
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 518>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@e6508000 {
|
||||
compatible = "renesas,i2c-r8a779h0",
|
||||
"renesas,rcar-gen4-i2c";
|
||||
reg = <0 0xe6508000 0 0x40>;
|
||||
interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 519>;
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 519>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@e6510000 {
|
||||
compatible = "renesas,i2c-r8a779h0",
|
||||
"renesas,rcar-gen4-i2c";
|
||||
reg = <0 0xe6510000 0 0x40>;
|
||||
interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 520>;
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 520>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@e66d0000 {
|
||||
compatible = "renesas,i2c-r8a779h0",
|
||||
"renesas,rcar-gen4-i2c";
|
||||
reg = <0 0xe66d0000 0 0x40>;
|
||||
interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 521>;
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 521>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hscif0: serial@e6540000 {
|
||||
compatible = "renesas,hscif-r8a779h0",
|
||||
"renesas,rcar-gen4-hscif", "renesas,hscif";
|
||||
reg = <0 0xe6540000 0 0x60>;
|
||||
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 514>,
|
||||
<&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 514>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
avb0: ethernet@e6800000 {
|
||||
compatible = "renesas,etheravb-r8a779h0",
|
||||
"renesas,etheravb-rcar-gen4";
|
||||
reg = <0 0xe6800000 0 0x800>;
|
||||
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14", "ch15",
|
||||
"ch16", "ch17", "ch18", "ch19",
|
||||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 211>;
|
||||
power-domains = <&sysc R8A779H0_PD_C4>;
|
||||
resets = <&cpg 211>;
|
||||
phy-mode = "rgmii";
|
||||
rx-internal-delay-ps = <0>;
|
||||
tx-internal-delay-ps = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
avb1: ethernet@e6810000 {
|
||||
compatible = "renesas,etheravb-r8a779h0",
|
||||
"renesas,etheravb-rcar-gen4";
|
||||
reg = <0 0xe6810000 0 0x800>;
|
||||
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14", "ch15",
|
||||
"ch16", "ch17", "ch18", "ch19",
|
||||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 212>;
|
||||
power-domains = <&sysc R8A779H0_PD_C4>;
|
||||
resets = <&cpg 212>;
|
||||
phy-mode = "rgmii";
|
||||
rx-internal-delay-ps = <0>;
|
||||
tx-internal-delay-ps = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
avb2: ethernet@e6820000 {
|
||||
compatible = "renesas,etheravb-r8a779h0",
|
||||
"renesas,etheravb-rcar-gen4";
|
||||
reg = <0 0xe6820000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14", "ch15",
|
||||
"ch16", "ch17", "ch18", "ch19",
|
||||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 213>;
|
||||
power-domains = <&sysc R8A779H0_PD_C4>;
|
||||
resets = <&cpg 213>;
|
||||
phy-mode = "rgmii";
|
||||
rx-internal-delay-ps = <0>;
|
||||
tx-internal-delay-ps = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc0: mmc@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a779h0",
|
||||
"renesas,rcar-gen4-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 706>,
|
||||
<&cpg CPG_CORE R8A779H0_CLK_SD0H>;
|
||||
clock-names = "core", "clkh";
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 706>;
|
||||
max-frequency = <200000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1000000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0xf1000000 0 0x20000>,
|
||||
<0x0 0xf1060000 0 0x110000>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
prr: chipid@fff00044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xfff00044 0 4>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
|
||||
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
@@ -20,6 +20,12 @@ config R8A779G0
|
||||
imply CLK_R8A779G0
|
||||
imply PINCTRL_PFC_R8A779G0
|
||||
|
||||
config R8A779H0
|
||||
bool "Renesas SoC R8A779H0"
|
||||
select GICV3
|
||||
imply CLK_R8A779H0
|
||||
imply PINCTRL_PFC_R8A779H0
|
||||
|
||||
endmenu
|
||||
|
||||
choice
|
||||
@@ -44,10 +50,17 @@ config TARGET_WHITEHAWK
|
||||
help
|
||||
Support for Renesas R-Car Gen4 White Hawk platform
|
||||
|
||||
config TARGET_GRAYHAWK
|
||||
bool "Gray Hawk board"
|
||||
imply R8A779H0
|
||||
help
|
||||
Support for Renesas R-Car Gen4 Gray Hawk platform
|
||||
|
||||
endchoice
|
||||
|
||||
source "board/renesas/falcon/Kconfig"
|
||||
source "board/renesas/spider/Kconfig"
|
||||
source "board/renesas/whitehawk/Kconfig"
|
||||
source "board/renesas/grayhawk/Kconfig"
|
||||
|
||||
endif
|
||||
|
||||
@@ -78,6 +78,7 @@ static const struct {
|
||||
{ RMOBILE_CPU_TYPE_R8A779A0, "R8A779A0" },
|
||||
{ RMOBILE_CPU_TYPE_R8A779F0, "R8A779F0" },
|
||||
{ RMOBILE_CPU_TYPE_R8A779G0, "R8A779G0" },
|
||||
{ RMOBILE_CPU_TYPE_R8A779H0, "R8A779H0" },
|
||||
{ 0x0, "CPU" },
|
||||
};
|
||||
|
||||
|
||||
@@ -43,6 +43,7 @@
|
||||
#define RMOBILE_CPU_TYPE_R8A779A0 0x59
|
||||
#define RMOBILE_CPU_TYPE_R8A779F0 0x5A
|
||||
#define RMOBILE_CPU_TYPE_R8A779G0 0x5C
|
||||
#define RMOBILE_CPU_TYPE_R8A779H0 0x5D
|
||||
#define RMOBILE_CPU_TYPE_R9A07G044L 0x9A070440
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
@@ -0,0 +1,15 @@
|
||||
if TARGET_GRAYHAWK
|
||||
|
||||
config SYS_SOC
|
||||
default "rmobile"
|
||||
|
||||
config SYS_BOARD
|
||||
default "grayhawk"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "renesas"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "grayhawk"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,5 @@
|
||||
GRAYHAWK BOARD
|
||||
M: Marek Vasut <marek.vasut+renesas@mailbox.org>
|
||||
S: Maintained
|
||||
N: grayhawk
|
||||
N: r8a779h0
|
||||
@@ -0,0 +1,9 @@
|
||||
#
|
||||
# board/renesas/grayhawk/Makefile
|
||||
#
|
||||
# Copyright (C) 2023 Renesas Electronics Corp.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := grayhawk.o ../rcar-common/common.o
|
||||
@@ -0,0 +1,66 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* board/renesas/grayhawk/grayhawk.c
|
||||
* This file is Gray Hawk board support.
|
||||
*
|
||||
* Copyright (C) 2023 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <asm/arch/rmobile.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/processor.h>
|
||||
#include <linux/errno.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static void init_generic_timer(void)
|
||||
{
|
||||
const u32 freq = CONFIG_SYS_CLK_FREQ;
|
||||
|
||||
/* Update memory mapped and register based freqency */
|
||||
asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
|
||||
writel(freq, CNTFID0);
|
||||
|
||||
/* Enable counter */
|
||||
setbits_le32(CNTCR_BASE, CNTCR_EN);
|
||||
}
|
||||
|
||||
static void init_gic_v3(void)
|
||||
{
|
||||
/* GIC v3 power on */
|
||||
writel(BIT(1), GICR_LPI_PWRR);
|
||||
|
||||
/* Wait till the WAKER_CA_BIT changes to 0 */
|
||||
clrbits_le32(GICR_LPI_WAKER, BIT(1));
|
||||
while (readl(GICR_LPI_WAKER) & BIT(2))
|
||||
;
|
||||
|
||||
writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
|
||||
}
|
||||
|
||||
void s_init(void)
|
||||
{
|
||||
if (current_el() == 3)
|
||||
init_generic_timer();
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* Unlock CPG access */
|
||||
writel(0x5A5AFFFF, CPGWPR);
|
||||
writel(0xA5A50000, CPGWPCR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
if (current_el() == 3)
|
||||
init_gic_v3();
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,75 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_RMOBILE=y
|
||||
CONFIG_SYS_MALLOC_LEN=0x4000000
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_ENV_OFFSET=0xFFFE0000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a779h0-gray-hawk-u-boot"
|
||||
CONFIG_RCAR_GEN4=y
|
||||
CONFIG_TARGET_GRAYHAWK=y
|
||||
CONFIG_SYS_MONITOR_LEN=1048576
|
||||
CONFIG_SYS_CLK_FREQ=16666666
|
||||
# CONFIG_PSCI_RESET is not set
|
||||
CONFIG_SYS_LOAD_ADDR=0x58000000
|
||||
CONFIG_SYS_BOOT_GET_CMDLINE=y
|
||||
CONFIG_SYS_BARGSIZE=2048
|
||||
CONFIG_REMAKE_ELF=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="tftp 0x48080000 Image && tftp 0x48000000 Image-r8a779h0-gray-hawk.dtb && booti 0x48080000 - 0x48000000"
|
||||
CONFIG_DEFAULT_FDT_FILE="r8a779h0-gray-hawk.dtb"
|
||||
CONFIG_SYS_CBSIZE=2048
|
||||
CONFIG_SYS_MALLOC_BOOTPARAMS=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_MAXARGS=64
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SYS_MMC_ENV_PART=2
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_CLK_RENESAS=y
|
||||
CONFIG_RCAR_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_RCAR_I2C=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_RENESAS_SDHI=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_BITBANGMII=y
|
||||
CONFIG_BITBANGMII_MULTI=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_RENESAS_RAVB=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_BAUDRATE=921600
|
||||
CONFIG_SCIF_CONSOLE=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_RENESAS_RPC_SPI=y
|
||||
@@ -151,6 +151,12 @@ config CLK_R8A779G0
|
||||
help
|
||||
Enable this to support the clocks on Renesas R8A779G0 SoC.
|
||||
|
||||
config CLK_R8A779H0
|
||||
bool "Renesas R8A779H0 clock driver"
|
||||
depends on CLK_RCAR_GEN3
|
||||
help
|
||||
Enable this to support the clocks on Renesas R8A779H0 SoC.
|
||||
|
||||
config CLK_R9A06G032
|
||||
bool "Renesas R9A06G032 clock driver"
|
||||
depends on CLK_RENESAS
|
||||
|
||||
@@ -22,6 +22,7 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A779H0) += r8a779h0-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
|
||||
obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o
|
||||
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
|
||||
|
||||
@@ -306,6 +306,12 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
|
||||
gen4_pll_config->pll6_div,
|
||||
"PLL6");
|
||||
|
||||
case CLK_TYPE_GEN4_PLL7:
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
|
||||
0, gen4_pll_config->pll7_mult,
|
||||
gen4_pll_config->pll7_div,
|
||||
"PLL7");
|
||||
|
||||
case CLK_TYPE_FF:
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
|
||||
0, core->mult, core->div,
|
||||
|
||||
@@ -0,0 +1,293 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a779h0 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2023 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on r8a779g0-cpg-mssr.c
|
||||
*/
|
||||
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A779H0_CLK_R,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_EXTALR,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL1,
|
||||
CLK_PLL2,
|
||||
CLK_PLL3,
|
||||
CLK_PLL4,
|
||||
CLK_PLL5,
|
||||
CLK_PLL6,
|
||||
CLK_PLL7,
|
||||
CLK_PLL1_DIV2,
|
||||
CLK_PLL2_DIV2,
|
||||
CLK_PLL3_DIV2,
|
||||
CLK_PLL4_DIV2,
|
||||
CLK_PLL4_DIV5,
|
||||
CLK_PLL5_DIV2,
|
||||
CLK_PLL5_DIV4,
|
||||
CLK_PLL6_DIV2,
|
||||
CLK_PLL7_DIV2,
|
||||
CLK_S0,
|
||||
CLK_S0_VIO,
|
||||
CLK_S0_VC,
|
||||
CLK_S0_HSC,
|
||||
CLK_SASYNCPER,
|
||||
CLK_SV_VIP,
|
||||
CLK_SV_IR,
|
||||
CLK_IMPASRC,
|
||||
CLK_IMPBSRC,
|
||||
CLK_VIOSRC,
|
||||
CLK_VCSRC,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_OCO,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a779h0_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("extalr", CLK_EXTALR),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
|
||||
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN),
|
||||
DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
|
||||
DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
|
||||
DEF_BASE(".pll7", CLK_PLL7, CLK_TYPE_GEN4_PLL7, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1),
|
||||
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1),
|
||||
DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1),
|
||||
DEF_FIXED(".pll4_div5", CLK_PLL4_DIV5, CLK_PLL4, 5, 1),
|
||||
DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
|
||||
DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
|
||||
DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1),
|
||||
DEF_FIXED(".pll7_div2", CLK_PLL7_DIV2, CLK_PLL7, 2, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s0_vio", CLK_S0_VIO, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s0_vc", CLK_S0_VC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s0_hsc", CLK_S0_HSC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".sasyncper", CLK_SASYNCPER, CLK_PLL5_DIV4, 3, 1),
|
||||
DEF_FIXED(".sv_vip", CLK_SV_VIP, CLK_PLL1, 5, 1),
|
||||
DEF_FIXED(".sv_ir", CLK_SV_IR, CLK_PLL1, 5, 1),
|
||||
DEF_FIXED(".impasrc", CLK_IMPASRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".impbsrc", CLK_IMPBSRC, CLK_PLL1, 4, 1),
|
||||
DEF_FIXED(".viosrc", CLK_VIOSRC, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED(".vcsrc", CLK_VCSRC, CLK_PLL1, 6, 1),
|
||||
DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
|
||||
DEF_RATE(".oco", CLK_OCO, 32768),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 0),
|
||||
DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 8),
|
||||
DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 32),
|
||||
DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 40),
|
||||
DEF_FIXED("s0d2", R8A779H0_CLK_S0D2, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3", R8A779H0_CLK_S0D3, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4", R8A779H0_CLK_S0D4, CLK_S0, 4, 1),
|
||||
DEF_FIXED("cl16m", R8A779H0_CLK_CL16M, CLK_S0, 48, 1),
|
||||
DEF_FIXED("s0d2_rt", R8A779H0_CLK_S0D2_RT, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3_rt", R8A779H0_CLK_S0D3_RT, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4_rt", R8A779H0_CLK_S0D4_RT, CLK_S0, 4, 1),
|
||||
DEF_FIXED("s0d6_rt", R8A779H0_CLK_S0D6_RT, CLK_S0, 6, 1),
|
||||
DEF_FIXED("cl16m_rt", R8A779H0_CLK_CL16M_RT, CLK_S0, 48, 1),
|
||||
DEF_FIXED("s0d2_per", R8A779H0_CLK_S0D2_PER, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3_per", R8A779H0_CLK_S0D3_PER, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4_per", R8A779H0_CLK_S0D4_PER, CLK_S0, 4, 1),
|
||||
DEF_FIXED("s0d6_per", R8A779H0_CLK_S0D6_PER, CLK_S0, 6, 1),
|
||||
DEF_FIXED("s0d12_per", R8A779H0_CLK_S0D12_PER, CLK_S0, 12, 1),
|
||||
DEF_FIXED("s0d24_per", R8A779H0_CLK_S0D24_PER, CLK_S0, 24, 1),
|
||||
DEF_FIXED("cl16m_per", R8A779H0_CLK_CL16M_PER, CLK_S0, 48, 1),
|
||||
DEF_FIXED("s0d2_mm", R8A779H0_CLK_S0D2_MM, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d4_mm", R8A779H0_CLK_S0D4_MM, CLK_S0, 4, 1),
|
||||
DEF_FIXED("cl16m_mm", R8A779H0_CLK_CL16M_MM, CLK_S0, 48, 1),
|
||||
DEF_FIXED("s0d2_u3dg", R8A779H0_CLK_S0D2_U3DG, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d4_u3dg", R8A779H0_CLK_S0D4_U3DG, CLK_S0, 4, 1),
|
||||
DEF_FIXED("s0d1_vio", R8A779H0_CLK_S0D1_VIO, CLK_S0_VIO, 1, 1),
|
||||
DEF_FIXED("s0d2_vio", R8A779H0_CLK_S0D2_VIO, CLK_S0_VIO, 2, 1),
|
||||
DEF_FIXED("s0d4_vio", R8A779H0_CLK_S0D4_VIO, CLK_S0_VIO, 4, 1),
|
||||
DEF_FIXED("s0d8_vio", R8A779H0_CLK_S0D8_VIO, CLK_S0_VIO, 8, 1),
|
||||
DEF_FIXED("s0d1_vc", R8A779H0_CLK_S0D1_VC, CLK_S0_VC, 1, 1),
|
||||
DEF_FIXED("s0d2_vc", R8A779H0_CLK_S0D2_VC, CLK_S0_VC, 2, 1),
|
||||
DEF_FIXED("s0d4_vc", R8A779H0_CLK_S0D4_VC, CLK_S0_VC, 4, 1),
|
||||
DEF_FIXED("s0d1_hsc", R8A779H0_CLK_S0D1_HSC, CLK_S0_HSC, 1, 1),
|
||||
DEF_FIXED("s0d2_hsc", R8A779H0_CLK_S0D2_HSC, CLK_S0_HSC, 2, 1),
|
||||
DEF_FIXED("s0d4_hsc", R8A779H0_CLK_S0D4_HSC, CLK_S0_HSC, 4, 1),
|
||||
DEF_FIXED("s0d8_hsc", R8A779H0_CLK_S0D8_HSC, CLK_S0_HSC, 8, 1),
|
||||
DEF_FIXED("cl16m_hsc", R8A779H0_CLK_CL16M_HSC, CLK_S0_HSC, 48, 1),
|
||||
DEF_FIXED("sasyncrt", R8A779H0_CLK_SASYNCRT, CLK_PLL5_DIV4, 48, 1),
|
||||
DEF_FIXED("sasyncperd1", R8A779H0_CLK_SASYNCPERD1, CLK_SASYNCPER, 1, 1),
|
||||
DEF_FIXED("sasyncperd2", R8A779H0_CLK_SASYNCPERD2, CLK_SASYNCPER, 2, 1),
|
||||
DEF_FIXED("sasyncperd4", R8A779H0_CLK_SASYNCPERD4, CLK_SASYNCPER, 4, 1),
|
||||
DEF_FIXED("svd1_vip", R8A779H0_CLK_SVD1_VIP, CLK_SV_VIP, 1, 1),
|
||||
DEF_FIXED("svd2_vip", R8A779H0_CLK_SVD2_VIP, CLK_SV_VIP, 2, 1),
|
||||
DEF_FIXED("svd1_ir", R8A779H0_CLK_SVD1_IR, CLK_SV_IR, 1, 1),
|
||||
DEF_FIXED("svd2_ir", R8A779H0_CLK_SVD2_IR, CLK_SV_IR, 2, 1),
|
||||
DEF_FIXED("cbfusa", R8A779H0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A779H0_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cp", R8A779H0_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("impad1", R8A779H0_CLK_IMPAD1, CLK_IMPASRC, 1, 1),
|
||||
DEF_FIXED("impad4", R8A779H0_CLK_IMPAD4, CLK_IMPASRC, 4, 1),
|
||||
DEF_FIXED("impb", R8A779H0_CLK_IMPB, CLK_IMPBSRC, 1, 1),
|
||||
DEF_FIXED("viobusd1", R8A779H0_CLK_VIOBUSD1, CLK_VIOSRC, 1, 1),
|
||||
DEF_FIXED("viobusd2", R8A779H0_CLK_VIOBUSD2, CLK_VIOSRC, 2, 1),
|
||||
DEF_FIXED("vcbusd1", R8A779H0_CLK_VCBUSD1, CLK_VCSRC, 1, 1),
|
||||
DEF_FIXED("vcbusd2", R8A779H0_CLK_VCBUSD2, CLK_VCSRC, 2, 1),
|
||||
DEF_DIV6P1("canfd", R8A779H0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
|
||||
DEF_DIV6P1("csi", R8A779H0_CLK_CSI, CLK_PLL5_DIV4, 0x880),
|
||||
DEF_FIXED("dsiref", R8A779H0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1),
|
||||
DEF_DIV6P1("dsiext", R8A779H0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884),
|
||||
DEF_DIV6P1("mso", R8A779H0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
|
||||
|
||||
DEF_GEN4_SDH("sd0h", R8A779H0_CLK_SD0H, CLK_SDSRC, 0x870),
|
||||
DEF_GEN4_SD("sd0", R8A779H0_CLK_SD0, R8A779H0_CLK_SD0H, 0x870),
|
||||
|
||||
DEF_BASE("rpc", R8A779H0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A779H0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779H0_CLK_RPC),
|
||||
|
||||
DEF_GEN4_OSC("osc", R8A779H0_CLK_OSC, CLK_EXTAL, 8),
|
||||
DEF_GEN4_MDSEL("r", R8A779H0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
|
||||
DEF_MOD("avb0-rgmii0", 211, R8A779H0_CLK_S0D8_HSC),
|
||||
DEF_MOD("avb1-rgmii1", 212, R8A779H0_CLK_S0D8_HSC),
|
||||
DEF_MOD("avb2-rgmii2", 213, R8A779H0_CLK_S0D8_HSC),
|
||||
DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1),
|
||||
DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1),
|
||||
DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1),
|
||||
DEF_MOD("hscif3", 517, R8A779H0_CLK_SASYNCPERD1),
|
||||
DEF_MOD("i2c0", 518, R8A779H0_CLK_S0D6_PER),
|
||||
DEF_MOD("i2c1", 519, R8A779H0_CLK_S0D6_PER),
|
||||
DEF_MOD("i2c2", 520, R8A779H0_CLK_S0D6_PER),
|
||||
DEF_MOD("i2c3", 521, R8A779H0_CLK_S0D6_PER),
|
||||
DEF_MOD("rpc-if", 629, R8A779H0_CLK_RPCD2),
|
||||
DEF_MOD("sdhi0", 706, R8A779H0_CLK_SD0),
|
||||
DEF_MOD("pfc0", 915, R8A779H0_CLK_CL16M),
|
||||
DEF_MOD("pfc1", 916, R8A779H0_CLK_CL16M),
|
||||
DEF_MOD("pfc2", 917, R8A779H0_CLK_CL16M),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
/*
|
||||
* MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
|
||||
* 14 13 (MHz)
|
||||
* ------------------------------------------------------------------------
|
||||
* 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /16
|
||||
* 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19
|
||||
* 1 0 Prohibited setting
|
||||
* 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /32
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
|
||||
(((md) & BIT(13)) >> 13))
|
||||
|
||||
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
|
||||
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv PLL7 mult/div */
|
||||
{ 1, 192, 1, 240, 1, 192, 1, 240, 1, 192, 1, 168, 1, 16, 120, 1, },
|
||||
{ 1, 160, 1, 200, 1, 160, 1, 200, 1, 160, 1, 140, 1, 19, 100, 1, },
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
|
||||
{ 2, 192, 1, 240, 1, 192, 1, 240, 1, 192, 1, 168, 1, 32, 120, 1, },
|
||||
};
|
||||
|
||||
/*
|
||||
* Note that the only clock left running before booting Linux are now
|
||||
* MFIS, INTC-AP, INTC-EX, SCIF0, HSCIF0 on V4M
|
||||
*/
|
||||
#define MSTPCR5_INTCAP BIT(11)
|
||||
#define MSTPCR5_HSCIF0 BIT(14)
|
||||
#define MSTPCR6_INTCEX BIT(11)
|
||||
#define MSTPCR7_SCIF0 BIT(2)
|
||||
|
||||
static const struct mstp_stop_table r8a779h0_mstp_table[] = {
|
||||
{ 0x0FC102A1, 0x0, 0x0, 0x0 },
|
||||
{ 0x00D50020, 0x0, 0x0, 0x0 },
|
||||
{ 0x00003800, 0x0, 0x0, 0x0 },
|
||||
{ 0xF0000000, 0x0, 0x0, 0x0 },
|
||||
{ 0x0000CA01, 0x0, 0x0, 0x0 },
|
||||
{ 0xE63FE100, MSTPCR5_HSCIF0 | MSTPCR5_INTCAP, 0x0, 0x0 },
|
||||
{ 0xF1FF3900, MSTPCR6_INTCEX, 0x0, 0x0 },
|
||||
{ 0xDFF7E6FC, MSTPCR7_SCIF0, 0x0, 0x0 },
|
||||
{ 0x40003FFF, 0x0, 0x0, 0x0 },
|
||||
{ 0x001BBCF8, 0x0, 0x0, 0x0 },
|
||||
{ 0x10000000, 0x0, 0x0, 0x0 },
|
||||
{ 0x00000001, 0x0, 0x0, 0x0 },
|
||||
{ 0xDE000000, 0x0, 0x0, 0x0 },
|
||||
{ 0x00000017, 0x0, 0x0, 0x0 },
|
||||
{ 0x00000000, 0x0, 0x0, 0x0 },
|
||||
{ 0x00000000, 0x0, 0x0, 0x0 },
|
||||
{ 0x00000000, 0x0, 0x0, 0x0 },
|
||||
{ 0x00000000, 0x0, 0x0, 0x0 },
|
||||
{ 0x00000000, 0x0, 0x0, 0x0 },
|
||||
{ 0x00000000, 0x0, 0x0, 0x0 },
|
||||
{ 0x00000000, 0x0, 0x0, 0x0 },
|
||||
{ 0x00000000, 0x0, 0x0, 0x0 },
|
||||
{ 0x00000000, 0x0, 0x0, 0x0 },
|
||||
{ 0x00000000, 0x0, 0x0, 0x0 },
|
||||
{ 0x00000000, 0x0, 0x0, 0x0 },
|
||||
{ 0x00000000, 0x0, 0x0, 0x0 },
|
||||
{ 0x00000000, 0x0, 0x0, 0x0 },
|
||||
{ 0x308003C0, 0x0, 0x0, 0x0 },
|
||||
{ 0x402200E6, 0x0, 0x0, 0x0 },
|
||||
{ 0x0C000000, 0x0, 0x0, 0x0 },
|
||||
};
|
||||
|
||||
static const void *r8a779h0_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a779h0_cpg_mssr_info = {
|
||||
.core_clk = r8a779h0_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a779h0_core_clks),
|
||||
.mod_clk = r8a779h0_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a779h0_mod_clks),
|
||||
.mstp_table = r8a779h0_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a779h0_mstp_table),
|
||||
.reset_node = "renesas,r8a779h0-rst",
|
||||
.reset_modemr_offset = CPG_RST_MODEMR0,
|
||||
.extalr_node = "extalr",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extalr_id = CLK_EXTALR,
|
||||
.get_pll_config = r8a779h0_get_pll_config,
|
||||
.reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a779h0_cpg_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a779h0-cpg-mssr",
|
||||
.data = (ulong)&r8a779h0_cpg_mssr_info
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a779h0) = {
|
||||
.name = "cpg_r8a779h0",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = r8a779h0_cpg_ids,
|
||||
.bind = gen3_cpg_bind,
|
||||
};
|
||||
@@ -41,6 +41,7 @@ enum rcar_gen3_clk_types {
|
||||
CLK_TYPE_GEN4_PLL5,
|
||||
CLK_TYPE_GEN4_PLL4,
|
||||
CLK_TYPE_GEN4_PLL6,
|
||||
CLK_TYPE_GEN4_PLL7,
|
||||
CLK_TYPE_GEN4_SDSRC,
|
||||
CLK_TYPE_GEN4_SDH,
|
||||
CLK_TYPE_GEN4_SD,
|
||||
@@ -130,6 +131,8 @@ struct rcar_gen4_cpg_pll_config {
|
||||
u8 pll6_mult;
|
||||
u8 pll6_div;
|
||||
u8 osc_prediv;
|
||||
u8 pll7_mult;
|
||||
u8 pll7_div;
|
||||
};
|
||||
|
||||
#define CPG_RST_MODEMR 0x060
|
||||
|
||||
@@ -131,6 +131,12 @@ config PINCTRL_PFC_R8A779G0
|
||||
help
|
||||
Support pin multiplexing control on Renesas RCar Gen4 R8A779G0 SoCs.
|
||||
|
||||
config PINCTRL_PFC_R8A779H0
|
||||
bool "Renesas RCar Gen4 R8A779H0 pin control driver"
|
||||
depends on PINCTRL_PFC
|
||||
help
|
||||
Support pin multiplexing control on Renesas RCar Gen4 R8A779H0 SoCs.
|
||||
|
||||
config PINCTRL_RZA1
|
||||
bool "Renesas RZ/A1 R7S72100 pin control driver"
|
||||
depends on CPU_RZA1
|
||||
|
||||
@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A779G0) += pfc-r8a779g0.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A779H0) += pfc-r8a779h0.o
|
||||
obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
|
||||
obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
|
||||
obj-$(CONFIG_PINCTRL_RZG2L) += rzg2l-pfc.o
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -44,6 +44,7 @@ enum sh_pfc_model {
|
||||
SH_PFC_R8A779A0,
|
||||
SH_PFC_R8A779F0,
|
||||
SH_PFC_R8A779G0,
|
||||
SH_PFC_R8A779H0,
|
||||
};
|
||||
|
||||
struct sh_pfc_pin_config {
|
||||
@@ -1041,6 +1042,10 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev)
|
||||
if (model == SH_PFC_R8A779G0)
|
||||
priv->pfc.info = &r8a779g0_pinmux_info;
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A779H0
|
||||
if (model == SH_PFC_R8A779H0)
|
||||
priv->pfc.info = &r8a779h0_pinmux_info;
|
||||
#endif
|
||||
|
||||
priv->pmx.pfc = &priv->pfc;
|
||||
sh_pfc_init_ranges(&priv->pfc);
|
||||
@@ -1170,6 +1175,12 @@ static const struct udevice_id sh_pfc_pinctrl_ids[] = {
|
||||
.data = SH_PFC_R8A779G0,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A779H0
|
||||
{
|
||||
.compatible = "renesas,pfc-r8a779h0",
|
||||
.data = SH_PFC_R8A779H0,
|
||||
},
|
||||
#endif
|
||||
|
||||
{ },
|
||||
};
|
||||
|
||||
@@ -307,6 +307,7 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a779a0_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a779f0_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a779g0_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a779h0_pinmux_info;
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
* Helper macros to create pin and port lists
|
||||
|
||||
@@ -215,7 +215,8 @@ static u32 rpc_spi_get_strobe_delay(void)
|
||||
if (cpu_type == RMOBILE_CPU_TYPE_R8A7796 && rmobile_get_cpu_rev_integer() == 1)
|
||||
return RPC_PHYCNT_STRTIM(6);
|
||||
else if (cpu_type == RMOBILE_CPU_TYPE_R8A779F0 ||
|
||||
cpu_type == RMOBILE_CPU_TYPE_R8A779G0)
|
||||
cpu_type == RMOBILE_CPU_TYPE_R8A779G0 ||
|
||||
cpu_type == RMOBILE_CPU_TYPE_R8A779H0)
|
||||
return RPC_PHYCNT_STRTIM2(15);
|
||||
else
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* include/configs/grayhawk.h
|
||||
* This file is Gray Hawk board configuration.
|
||||
*
|
||||
* Copyright (C) 2023 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#ifndef __GRAYHAWK_H
|
||||
#define __GRAYHAWK_H
|
||||
|
||||
#include "rcar-gen4-common.h"
|
||||
|
||||
#endif /* __GRAYHAWK_H */
|
||||
@@ -0,0 +1,96 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (C) 2023 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a779h0 CPG Core Clocks */
|
||||
|
||||
#define R8A779H0_CLK_ZX 0
|
||||
#define R8A779H0_CLK_ZD 1
|
||||
#define R8A779H0_CLK_ZS 2
|
||||
#define R8A779H0_CLK_ZT 3
|
||||
#define R8A779H0_CLK_ZTR 4
|
||||
#define R8A779H0_CLK_S0D2 5
|
||||
#define R8A779H0_CLK_S0D3 6
|
||||
#define R8A779H0_CLK_S0D4 7
|
||||
#define R8A779H0_CLK_S0D1_VIO 8
|
||||
#define R8A779H0_CLK_S0D2_VIO 9
|
||||
#define R8A779H0_CLK_S0D4_VIO 10
|
||||
#define R8A779H0_CLK_S0D8_VIO 11
|
||||
#define R8A779H0_CLK_VIOBUSD1 12
|
||||
#define R8A779H0_CLK_VIOBUSD2 13
|
||||
#define R8A779H0_CLK_S0D1_VC 14
|
||||
#define R8A779H0_CLK_S0D2_VC 15
|
||||
#define R8A779H0_CLK_S0D4_VC 16
|
||||
#define R8A779H0_CLK_VCBUSD1 17
|
||||
#define R8A779H0_CLK_VCBUSD2 18
|
||||
#define R8A779H0_CLK_S0D2_MM 19
|
||||
#define R8A779H0_CLK_S0D4_MM 20
|
||||
#define R8A779H0_CLK_S0D2_U3DG 21
|
||||
#define R8A779H0_CLK_S0D4_U3DG 22
|
||||
#define R8A779H0_CLK_S0D2_RT 23
|
||||
#define R8A779H0_CLK_S0D3_RT 24
|
||||
#define R8A779H0_CLK_S0D4_RT 25
|
||||
#define R8A779H0_CLK_S0D6_RT 26
|
||||
#define R8A779H0_CLK_S0D2_PER 27
|
||||
#define R8A779H0_CLK_S0D3_PER 28
|
||||
#define R8A779H0_CLK_S0D4_PER 29
|
||||
#define R8A779H0_CLK_S0D6_PER 30
|
||||
#define R8A779H0_CLK_S0D12_PER 31
|
||||
#define R8A779H0_CLK_S0D24_PER 32
|
||||
#define R8A779H0_CLK_S0D1_HSC 33
|
||||
#define R8A779H0_CLK_S0D2_HSC 34
|
||||
#define R8A779H0_CLK_S0D4_HSC 35
|
||||
#define R8A779H0_CLK_S0D8_HSC 36
|
||||
#define R8A779H0_CLK_SVD1_IR 37
|
||||
#define R8A779H0_CLK_SVD2_IR 38
|
||||
#define R8A779H0_CLK_IMPAD1 39
|
||||
#define R8A779H0_CLK_IMPAD4 40
|
||||
#define R8A779H0_CLK_IMPB 41
|
||||
#define R8A779H0_CLK_SVD1_VIP 42
|
||||
#define R8A779H0_CLK_SVD2_VIP 43
|
||||
#define R8A779H0_CLK_CL 44
|
||||
#define R8A779H0_CLK_CL16M 45
|
||||
#define R8A779H0_CLK_CL16M_MM 46
|
||||
#define R8A779H0_CLK_CL16M_RT 47
|
||||
#define R8A779H0_CLK_CL16M_PER 48
|
||||
#define R8A779H0_CLK_CL16M_HSC 49
|
||||
#define R8A779H0_CLK_ZC0 50
|
||||
#define R8A779H0_CLK_ZC1 51
|
||||
#define R8A779H0_CLK_ZC2 52
|
||||
#define R8A779H0_CLK_ZC3 53
|
||||
#define R8A779H0_CLK_ZB3 54
|
||||
#define R8A779H0_CLK_ZB3D2 55
|
||||
#define R8A779H0_CLK_ZB3D4 56
|
||||
#define R8A779H0_CLK_ZG 57
|
||||
#define R8A779H0_CLK_SD0H 58
|
||||
#define R8A779H0_CLK_SD0 59
|
||||
#define R8A779H0_CLK_RPC 60
|
||||
#define R8A779H0_CLK_RPCD2 61
|
||||
#define R8A779H0_CLK_MSO 62
|
||||
#define R8A779H0_CLK_CANFD 63
|
||||
#define R8A779H0_CLK_CSI 64
|
||||
#define R8A779H0_CLK_FRAY 65
|
||||
#define R8A779H0_CLK_IPC 66
|
||||
#define R8A779H0_CLK_SASYNCRT 67
|
||||
#define R8A779H0_CLK_SASYNCPERD1 68
|
||||
#define R8A779H0_CLK_SASYNCPERD2 69
|
||||
#define R8A779H0_CLK_SASYNCPERD4 70
|
||||
#define R8A779H0_CLK_DSIEXT 71
|
||||
#define R8A779H0_CLK_DSIREF 72
|
||||
#define R8A779H0_CLK_ADGH 73
|
||||
#define R8A779H0_CLK_OSC 74
|
||||
#define R8A779H0_CLK_ZR0 75
|
||||
#define R8A779H0_CLK_ZR1 76
|
||||
#define R8A779H0_CLK_ZR2 77
|
||||
#define R8A779H0_CLK_RGMII 78
|
||||
#define R8A779H0_CLK_CPEX 79
|
||||
#define R8A779H0_CLK_CP 80
|
||||
#define R8A779H0_CLK_CBFUSA 81
|
||||
#define R8A779H0_CLK_R 82
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ */
|
||||
@@ -0,0 +1,49 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (C) 2023 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the Power Domain Register Numbers (PDR)
|
||||
*/
|
||||
|
||||
#define R8A779H0_PD_A1E0D0C0 0
|
||||
#define R8A779H0_PD_A1E0D0C1 1
|
||||
#define R8A779H0_PD_A1E0D0C2 2
|
||||
#define R8A779H0_PD_A1E0D0C3 3
|
||||
#define R8A779H0_PD_A2E0D0 16
|
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#define R8A779H0_PD_A3CR0 21
|
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#define R8A779H0_PD_A3CR1 22
|
||||
#define R8A779H0_PD_A3CR2 23
|
||||
#define R8A779H0_PD_A33DGA 24
|
||||
#define R8A779H0_PD_A23DGB 25
|
||||
#define R8A779H0_PD_C4 31
|
||||
#define R8A779H0_PD_A1DSP0 33
|
||||
#define R8A779H0_PD_A2IMP01 34
|
||||
#define R8A779H0_PD_A2PSC 35
|
||||
#define R8A779H0_PD_A2CV0 36
|
||||
#define R8A779H0_PD_A2CV1 37
|
||||
#define R8A779H0_PD_A3IMR0 38
|
||||
#define R8A779H0_PD_A3IMR1 39
|
||||
#define R8A779H0_PD_A3VC 40
|
||||
#define R8A779H0_PD_A2CN0 42
|
||||
#define R8A779H0_PD_A1CN0 44
|
||||
#define R8A779H0_PD_A1DSP1 45
|
||||
#define R8A779H0_PD_A2DMA 47
|
||||
#define R8A779H0_PD_A2CV2 48
|
||||
#define R8A779H0_PD_A2CV3 49
|
||||
#define R8A779H0_PD_A3IMR2 50
|
||||
#define R8A779H0_PD_A3IMR3 51
|
||||
#define R8A779H0_PD_A3PCI 52
|
||||
#define R8A779H0_PD_A2PCIPHY 53
|
||||
#define R8A779H0_PD_A3VIP0 56
|
||||
#define R8A779H0_PD_A3VIP2 58
|
||||
#define R8A779H0_PD_A3ISP0 60
|
||||
#define R8A779H0_PD_A3DUL 62
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A779H0_PD_ALWAYS_ON 64
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ */
|
||||
Reference in New Issue
Block a user