Revert "riscv: Add a Zalrsc-only alternative for synchronization in start.S"

This reverts commit a681cfecb4.

It has been reported that the commit causes boot regression for SPL on
StarFive VisionFive 2 or compatible boards. Inspecting the code, I did
spot one logic error for deciding whether Zaamo or Zalrsc is used, and
it's still unclear what exactly causes the regression, let's revert it
for now.

Reported-by: E Shattow <e@freeshell.de>
Link: https://lore.kernel.org/u-boot/1871663e-b918-4351-9e9e-97f9a4c73733@freeshell.de/
Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: E Shattow <e@freeshell.de>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>

arch/riscv/cpu/start.S

@@ -151,15 +151,8 @@ call_harts_early_init:
 	 */
 	la	t0, hart_lottery
 	li	t1, 1
-#if CONFIG_IS_ENABLED(RISCV_ISA_ZAAMO)
 	amoswap.w s2, t1, 0(t0)
 	bnez	s2, wait_for_gd_init
-#else
-	lr.w	s2, (t0)
-	bnez	s2, wait_for_gd_init
-	sc.w	s2, t1, (t0)
-	bnez	s2, wait_for_gd_init
-#endif
 #else
 	/*
 	 * FIXME: gp is set before it is initialized. If an XIP U-Boot ever
@@ -184,12 +177,7 @@ call_harts_early_init:
 #if !CONFIG_IS_ENABLED(XIP)
 #ifdef CONFIG_AVAILABLE_HARTS
 	la	t0, available_harts_lock
-#if CONFIG_IS_ENABLED(RISCV_ISA_ZAAMO)
 	amoswap.w.rl zero, zero, 0(t0)
-#else
-	fence	rw, w
-	sw	zero, 0(t0)
-#endif
 #endif
 
 wait_for_gd_init:
@@ -202,14 +190,7 @@ wait_for_gd_init:
 #ifdef CONFIG_AVAILABLE_HARTS
 	la	t0, available_harts_lock
 	li	t1, 1
-1:
-#if CONFIG_IS_ENABLED(RISCV_ISA_ZAAMO)
-	amoswap.w.aq t1, t1, 0(t0)
-#else
-	lr.w.aq	t1, 0(t0)
-	bnez	t1, 1b
-	sc.w.rl t1, t1, 0(t0)
-#endif
+1:	amoswap.w.aq t1, t1, 0(t0)
 	bnez	t1, 1b
 
 	/* register available harts in the available_harts mask */
@@ -219,12 +200,7 @@ wait_for_gd_init:
 	or	t2, t2, t1
 	SREG	t2, GD_AVAILABLE_HARTS(gp)
 
-#if CONFIG_IS_ENABLED(RISCV_ISA_ZAAMO)
 	amoswap.w.rl zero, zero, 0(t0)
-#else
-	fence	rw, w
-	sw	zero, 0(t0)
-#endif
 #endif
 
 	/*