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rockchip: veyron: Enable Winbond SPI flash

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Some veyron boards seem to have Winbond SPI flash chips instead of
GigaDevice ones. At the very least, coreboot builds for veyron boards
have them enabled [1]. Enable support for them here as well.

[1] https://review.coreboot.org/c/coreboot/+/9719

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Alper Nebi Yasak
2023-07-28 18:45:03 +08:00
committed by Kever Yang
parent 0022461ba6
commit e5b33200f8
4 changed files with 4 additions and 0 deletions
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configs/chromebit_mickey_defconfig
+1
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@@ -81,6 +81,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_BUS=2
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y
configs/chromebook_jerry_defconfig
+1
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@@ -84,6 +84,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_BUS=2
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y
configs/chromebook_minnie_defconfig
+1
View File
@@ -83,6 +83,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_BUS=2
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y
configs/chromebook_speedy_defconfig
+1
View File
@@ -82,6 +82,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_BUS=2
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y