imx: Support i.MX91 11x11 FRDM board
Add i.MX91 11x11 FRDM Board support. - Four ddr scripts included w/o inline ecc feature. Support both 1gb and 2gb DDR - SDHC/EQOS/I2C/UART supported - PCA9451 supported, default nominal drive mode - Documentation added. Signed-off-by: Joseph Guo <qijian.guo@nxp.com>
This commit is contained in:
Joseph Guo
committed by
Fabio Estevam
Fabio Estevam
parent
e71d109e7b
commit
e4eccb860a
@@ -0,0 +1,34 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2025 NXP
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*/
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#include "imx91-u-boot.dtsi"
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/ {
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog3>;
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bootph-pre-ram;
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bootph-some-ram;
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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};
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&s4muap {
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bootph-pre-ram;
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bootph-some-ram;
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status = "okay";
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};
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&clk {
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-rates;
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/delete-property/ assigned-clock-parents;
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};
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@@ -61,6 +61,14 @@ config TARGET_IMX91_11X11_EVK
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imply BOOTSTD_FULL
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imply BOOTSTD_BOOTCOMMAND
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config TARGET_IMX91_11X11_FRDM
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bool "imx91_11x11_frdm"
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select OF_BOARD_FIXUP
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select IMX91
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select IMX9_LPDDR4X
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imply BOOTSTD_FULL
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imply BOOTSTD_BOOTCOMMAND
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config TARGET_IMX93_9X9_QSB
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bool "imx93_qsb"
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select OF_BOARD_FIXUP
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@@ -148,6 +156,7 @@ config TARGET_TORADEX_SMARC_IMX95
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endchoice
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source "board/freescale/imx91_evk/Kconfig"
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source "board/freescale/imx91_frdm/Kconfig"
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source "board/freescale/imx93_evk/Kconfig"
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source "board/freescale/imx93_frdm/Kconfig"
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source "board/freescale/imx93_qsb/Kconfig"
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@@ -0,0 +1,12 @@
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if TARGET_IMX91_11X11_FRDM
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config SYS_BOARD
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default "imx91_frdm"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "imx91_frdm"
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endif
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@@ -0,0 +1,7 @@
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FRDM-IMX91 BOARD
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M: Joseph Guo <qijian.guo@nxp.com>
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S: Maintained
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F: board/freescale/imx91_frdm/
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F: include/configs/imx91_frdm.h
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F: configs/imx91_11x11_frdm_defconfig
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F: configs/imx91_11x11_frdm_inline_ecc_defconfig
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@@ -0,0 +1,16 @@
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#
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# Copyright 2025 NXP
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += imx91_frdm.o
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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ifdef CONFIG_IMX9_DRAM_INLINE_ECC
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obj-y += lpddr4_2400mts_ecc_1gb_timing.o lpddr4_2400mts_ecc_2gb_timing.o
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else
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obj-y += lpddr4_2400mts_1gb_timing.o lpddr4_2400mts_2gb_timing.o
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endif
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endif
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@@ -0,0 +1,84 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2025 NXP
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*/
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#include <env.h>
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#include <asm/arch/sys_proto.h>
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#include <i2c.h>
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#include <dm.h>
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#define TCPC_ALERT 0x10
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#define TCPC_ALERT_MASK 0x12
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#define TCPC_FAULT_STATUS_MASK 0x15
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#define USB_I2C_BUS 2
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#define USB_I2C_ADDR 0x50
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/*
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* Since tcpc driver is not upstream. PTN5110 interrupt will cause
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* kernel panic because nobody cares the interrupt. So add workaround here.
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* Clear PTN5110 USB Power Delivery controller alert status by
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* masking interrupts and clearing pending alerts via I2C communication.
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* This is typically called during board initialization to ensure the USB PD
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* controller starts in a clean state without any stale alert conditions.
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*/
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static int clear_pd_alert(void)
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{
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struct udevice *bus;
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struct udevice *i2c_dev = NULL;
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int ret;
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u8 buffer_0[2] = {0, 0};
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u8 buffer_1[2] = {0xff, 0xff};
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ret = uclass_get_device_by_seq(UCLASS_I2C, USB_I2C_BUS, &bus);
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if (ret) {
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printf("Failed to get I2C bus %d\n", USB_I2C_BUS);
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return ret;
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}
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ret = dm_i2c_probe(bus, USB_I2C_ADDR, 0, &i2c_dev);
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if (ret) {
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printf("Can't find USB PD device at 0x%02x\n", USB_I2C_ADDR);
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return ret;
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}
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/* Mask all alert status*/
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ret = dm_i2c_write(i2c_dev, TCPC_ALERT_MASK, buffer_0, 2);
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if (ret) {
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printf("%s dm_i2c_write failed: %d\n", __func__, ret);
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return ret;
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}
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ret = dm_i2c_write(i2c_dev, TCPC_FAULT_STATUS_MASK, buffer_0, 2);
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if (ret) {
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printf("%s dm_i2c_write failed: %d\n", __func__, ret);
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return ret;
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}
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ret = dm_i2c_write(i2c_dev, TCPC_ALERT, buffer_1, 2);
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if (ret) {
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printf("%s dm_i2c_write failed: %d\n", __func__, ret);
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return ret;
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}
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return 0;
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}
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int board_late_init(void)
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{
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if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
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board_late_mmc_env_init();
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env_set("sec_boot", "no");
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if (IS_ENABLED(CONFIG_AHAB_BOOT))
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env_set("sec_boot", "yes");
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if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
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env_set("board_name", "11X11_FRDM");
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env_set("board_rev", "iMX91");
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}
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clear_pd_alert();
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return 0;
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}
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@@ -0,0 +1,89 @@
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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boot_targets=mmc0 mmc1
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boot_fit=no
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bootm_size=0x10000000
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cntr_addr=0x98000000
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cntr_file=os_cntr_signed.bin
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console=ttyLP0,115200 earlycon
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fdt_addr_r=0x83000000
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fdt_addr=0x83000000
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fdtfile=CONFIG_DEFAULT_FDT_FILE
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image=Image
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mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
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mmcpart=1
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mmcroot=/dev/mmcblk1p2 rootwait rw
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mmcautodetect=yes
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mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot}
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loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
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loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};
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bootscript=echo Running bootscript from mmc ...; source
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loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
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loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}
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auth_os=auth_cntr ${cntr_addr}
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sec_boot=no
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boot_os=booti ${loadaddr} - ${fdt_addr_r}
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mmcboot=
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echo Booting from mmc ...;
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run mmcargs;
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if test ${sec_boot} = yes; then
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if run true; then
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run boot_os;
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else
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echo ERR: failed to authenticate;
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fi;
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else
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if run loadfdt; then
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run boot_os;
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else
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echo WARN: Cannot load the DT;
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fi;
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fi;
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netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs
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ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
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netboot=
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echo Booting from net ...;
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run netargs;
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if test ${ip_dyn} = yes; then
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setenv get_cmd dhcp;
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else
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setenv get_cmd tftp;
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fi;
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if test ${sec_boot} = yes; then
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${get_cmd} ${cntr_addr} ${cntr_file};
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if true; then
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run boot_os;
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else
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echo ERR: failed to authenticate;
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fi;
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else
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${get_cmd} ${loadaddr} ${image};
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if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then
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run boot_os;
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else
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echo WARN: Cannot load the DT;
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fi;
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fi;
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bsp_bootcmd=
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echo Running BSP bootcmd ...;
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mmc dev ${mmcdev};
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if mmc rescan; then
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if run loadbootscript; then
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run bootscript;
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else
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if test ${sec_boot} = yes; then
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if run loadcntr; then
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run mmcboot;
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else
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run netboot;
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fi;
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else
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if run loadimage; then
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run mmcboot;
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else
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run netboot;
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fi;
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fi;
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fi;
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fi;
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scriptaddr=0x83500000
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,12 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2025 NXP
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*/
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#ifndef __LPDDR4_TIMING_H__
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#define __LPDDR4_TIMING_H__
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extern struct dram_timing_info dram_timing_1GB;
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extern struct dram_timing_info dram_timing_2GB;
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#endif /* __LPDDR4_TIMING_H__ */
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@@ -0,0 +1,193 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2025 NXP
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*/
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#include "lpddr4_timing.h"
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#include <init.h>
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#include <spl.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/mu.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/trdc.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/ele_api.h>
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#include <asm/global_data.h>
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#include <asm/sections.h>
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#include <dm/device.h>
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#include <dm/device-internal.h>
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#include <dm/uclass.h>
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#include <dm/uclass-internal.h>
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#include <linux/delay.h>
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#include <power/pca9450.h>
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#include <power/pmic.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define SRC_DDRC_SW_CTRL (0x44461020)
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#define SRC_DDRPHY_SINGLE_RESET_SW_CTRL (0x44461424)
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static struct _drams {
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u8 mr8;
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struct dram_timing_info *pdram_timing;
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char *name;
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} frdm_drams[2] = {
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{0x10, &dram_timing_1GB, "1GB DRAM" },
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{0x18, &dram_timing_2GB, "2GB DRAM" },
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};
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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return BOOT_DEVICE_BOOTROM;
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}
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void spl_board_init(void)
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{
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int ret;
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ret = ele_start_rng();
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if (ret)
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printf("Fail to start RNG: %d\n", ret);
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puts("Normal Boot\n");
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}
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void spl_dram_init(void)
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{
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int i;
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int ret;
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for (i = 0; i < ARRAY_SIZE(frdm_drams); i++) {
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struct dram_timing_info *ptiming = frdm_drams[i].pdram_timing;
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printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate);
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ret = ddr_init(ptiming);
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if (ret == 0) {
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if (lpddr4_mr_read(1, 8) == frdm_drams[i].mr8) {
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printf("found DRAM %s matched\n", frdm_drams[i].name);
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break;
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}
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/* Power down and Power up DDR Mixer */
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/* Clear PwrOkIn via DDRMIX register */
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setbits_32(SRC_DDRPHY_SINGLE_RESET_SW_CTRL, BIT(0));
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/* Power off the DDRMIX */
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setbits_32(SRC_DDRC_SW_CTRL, BIT(31));
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udelay(50);
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/* Power up the DDRMIX */
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clrbits_32(SRC_DDRC_SW_CTRL, BIT(31));
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setbits_32(SRC_DDRC_SW_CTRL, BIT(0));
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udelay(10);
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clrbits_32(SRC_DDRC_SW_CTRL, BIT(0));
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udelay(10);
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}
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}
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}
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#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
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int power_init_board(void)
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{
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struct udevice *dev;
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int ret;
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unsigned int val = 0, buck_val;
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ret = pmic_get("pmic@25", &dev);
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if (ret == -ENODEV) {
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puts("ERROR: Get PMIC PCA9451A failed!\n");
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return ret;
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}
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if (ret != 0)
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return ret;
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/* BUCKxOUT_DVS0/1 control BUCK123 output */
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pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
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/* enable DVS control through PMIC_STBY_REQ */
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pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
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ret = pmic_reg_read(dev, PCA9450_PWR_CTRL);
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if (ret < 0)
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return ret;
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val = ret;
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if (is_voltage_mode(VOLT_LOW_DRIVE)) {
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buck_val = 0x0c; /* 0.8V for Low drive mode */
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printf("PMIC: Low Drive Voltage Mode\n");
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} else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) {
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buck_val = 0x10; /* 0.85V for Nominal drive mode */
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printf("PMIC: Nominal Voltage Mode\n");
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} else {
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buck_val = 0x14; /* 0.9V for Over drive mode */
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printf("PMIC: Over Drive Voltage Mode\n");
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}
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if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) {
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val);
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pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val);
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} else {
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4);
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pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4);
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}
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/* Set VDDQ to 1.1V from buck2 (buck2 not used for iMX91 EVK) */
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pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28);
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/* set standby voltage to 0.65V */
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if (val & PCA9450_REG_PWRCTRL_TOFF_DEB)
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0);
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else
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
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/* I2C_LT_EN*/
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pmic_reg_write(dev, 0xa, 0x3);
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return 0;
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}
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#endif
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void board_init_f(ulong dummy)
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{
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int ret;
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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timer_init();
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arch_cpu_init();
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spl_early_init();
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preloader_console_init();
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ret = imx9_probe_mu();
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if (ret) {
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printf("Fail to init ELE API\n");
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} else {
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debug("SOC: 0x%x\n", gd->arch.soc_rev);
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debug("LC: 0x%x\n", gd->arch.lifecycle);
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}
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clock_init_late();
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power_init_board();
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if (!is_voltage_mode(VOLT_LOW_DRIVE))
|
||||
set_arm_clk(get_cpu_speed_grade_hz());
|
||||
|
||||
/* Init power of mix */
|
||||
soc_power_init();
|
||||
|
||||
/* Setup TRDC for DDR access */
|
||||
trdc_init();
|
||||
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
@@ -0,0 +1,138 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_IMX9=y
|
||||
CONFIG_TEXT_BASE=0x80200000
|
||||
CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x18000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_SF_DEFAULT_SPEED=40000000
|
||||
CONFIG_ENV_SIZE=0x4000
|
||||
CONFIG_ENV_OFFSET=0x700000
|
||||
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx91-11x11-frdm"
|
||||
CONFIG_TARGET_IMX91_11X11_FRDM=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_SYS_MONITOR_LEN=524288
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL_STACK=0x204E0000
|
||||
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_SPL_TEXT_BASE=0x204A0000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x20498000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
||||
CONFIG_SYS_LOAD_ADDR=0x80400000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_CMD_DEKBLOB=y
|
||||
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
|
||||
CONFIG_SYS_MEMTEST_START=0x80000000
|
||||
CONFIG_SYS_MEMTEST_END=0x90000000
|
||||
CONFIG_REMAKE_ELF=y
|
||||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd"
|
||||
CONFIG_DEFAULT_FDT_FILE="imx91-11x11-frdm.dtb"
|
||||
CONFIG_SYS_CBSIZE=2048
|
||||
CONFIG_SYS_PBSIZE=2074
|
||||
# CONFIG_BOARD_INIT is not set
|
||||
CONFIG_BOARD_LATE_INIT=y
|
||||
CONFIG_SPL_MAX_SIZE=0x26000
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_BOOTROM_SUPPORT=y
|
||||
CONFIG_SPL_LOAD_IMX_CONTAINER=y
|
||||
CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_HAVE_INIT_STACK=y
|
||||
CONFIG_SPL_SYS_MALLOC=y
|
||||
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
|
||||
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
|
||||
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_POWER=y
|
||||
CONFIG_SPL_WATCHDOG=y
|
||||
CONFIG_SYS_PROMPT="u-boot=> "
|
||||
CONFIG_CMD_CPU=y
|
||||
CONFIG_CMD_ERASEENV=y
|
||||
CONFIG_CMD_NVEDIT_EFI=y
|
||||
CONFIG_CRC32_VERIFY=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_FUSE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_POWEROFF=y
|
||||
CONFIG_CMD_SNTP=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EFIDEBUG=y
|
||||
CONFIG_CMD_RTC=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_GETTIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_HASH=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_NOWHERE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_ENV_MMC_DEVICE_INDEX=1
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_USE_ETHPRIME=y
|
||||
CONFIG_ETHPRIME="eth1"
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_ADC=y
|
||||
CONFIG_ADC_IMX93=y
|
||||
CONFIG_CLK_IMX93=y
|
||||
CONFIG_SAVED_DRAM_TIMING_BASE=0x2049C000
|
||||
CONFIG_IMX_RGPIO2P=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_ADP5585_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_IMX_LPI2C=y
|
||||
CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_PHY_ANEG_TIMEOUT=20000
|
||||
CONFIG_PHY_MOTORCOMM=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_IMX=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX93=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_DM_PMIC_PCA9450=y
|
||||
CONFIG_SPL_DM_PMIC_PCA9450=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_PCA9450=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_DM_RTC=y
|
||||
CONFIG_RTC_EMULATION=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_FSL_LPUART=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SYSRESET_CMD_POWEROFF=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_ULP_WATCHDOG=y
|
||||
CONFIG_WDT=y
|
||||
CONFIG_SHA384=y
|
||||
CONFIG_LZO=y
|
||||
CONFIG_BZIP2=y
|
||||
@@ -0,0 +1,3 @@
|
||||
#include <configs/imx91_11x11_frdm_defconfig>
|
||||
|
||||
CONFIG_IMX9_DRAM_INLINE_ECC=y
|
||||
@@ -0,0 +1,100 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
imx91_frdm
|
||||
=======================
|
||||
|
||||
U-Boot for the NXP i.MX91 11x11 FRDM Board
|
||||
|
||||
Quick Start
|
||||
-----------
|
||||
|
||||
- Get and Build the ARM Trusted firmware
|
||||
- Get the DDR firmware
|
||||
- Get ahab-container.img
|
||||
- Build U-Boot
|
||||
- Boot from the SD card
|
||||
- Boot using USB serial download (uuu)
|
||||
|
||||
Get and Build the ARM Trusted firmware
|
||||
--------------------------------------
|
||||
|
||||
Note: srctree is U-Boot source directory
|
||||
Get ATF from: https://github.com/nxp-imx/imx-atf/
|
||||
branch: lf_v2.10
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ unset LDFLAGS
|
||||
$ make PLAT=imx91 bl31
|
||||
$ cp build/imx91/release/bl31.bin $(srctree)
|
||||
|
||||
Get the DDR firmware
|
||||
--------------------
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.21.bin
|
||||
$ chmod +x firmware-imx-8.21.bin
|
||||
$ ./firmware-imx-8.21.bin
|
||||
$ cp firmware-imx-8.21/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
|
||||
|
||||
Get ahab-container.img
|
||||
---------------------------------------
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-1.3.0-17945fc.bin
|
||||
$ chmod +x firmware-ele-imx-1.3.0-17945fc.bin
|
||||
$ ./firmware-ele-imx-1.3.0-17945fc.bin
|
||||
$ cp firmware-ele-imx-1.3.0-17945fc/mx91a0-ahab-container.img $(srctree)
|
||||
|
||||
Build U-Boot
|
||||
------------
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ export CROSS_COMPILE=aarch64-poky-linux-
|
||||
$ make imx91_11x11_frdm_defconfig or imx91_11x11_frdm_inline_ecc_defconfig
|
||||
$ make
|
||||
|
||||
- Inline ECC is to enable DDR ECC feature with imx91_11x11_frdm_inline_ecc_defconfig
|
||||
Enable ECC will reduce DDR size by 1/8. For 1GB DRAM, available size will be 896MB.
|
||||
|
||||
Burn the flash.bin to MicroSD card offset 32KB:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ dd if=flash.bin of=/dev/sd[x] bs=1k seek=32; sync
|
||||
|
||||
Boot from the SD card
|
||||
---------------------
|
||||
|
||||
- Configure SW1 boot switches to SD boot mode:
|
||||
0011 SW1[3:0] - ("USDHC2 4-bit SD3.0" Boot Mode)
|
||||
- Insert the SD card in the SD slot (P13) of the board.
|
||||
- Connect a USB Type-C cable into the P16 Debug USB Port and connect
|
||||
using a terminal emulator at 115200 bps, 8n1. The console will show up
|
||||
at /dev/ttyACM0.
|
||||
- Power on the board by connecting a USB Type-C cable into the P1
|
||||
Power USB Port.
|
||||
|
||||
Boot using USB serial download (uuu)
|
||||
------------------------------------
|
||||
|
||||
- Configure SW1 boot switches to serial download boot mode:
|
||||
0001 SW1[3:0] - ("Serial downloader (USB)" Boot Mode)
|
||||
- Plug USB Type-C cable into the P2 device port.
|
||||
- Connect a USB Type-C cable into the P16 Debug USB Port and connect
|
||||
using a terminal emulator at 115200 bps, 8n1. The console will show up
|
||||
at /dev/ttyACM0.
|
||||
- Power on the board by connecting a USB Type-C cable into the P1
|
||||
Power USB Port.
|
||||
- Use NXP Universal Update Utility `NXP Universal Update Utility`_ to boot or
|
||||
flash the device. E.g. following command can be used to flash an image onto
|
||||
the eMMC storage:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ uuu -V -b emmc_all <image file>
|
||||
|
||||
.. _`NXP Universal Update Utility`: https://github.com/nxp-imx/mfgtools
|
||||
@@ -13,6 +13,7 @@ NXP Semiconductors
|
||||
imx8qxp_mek
|
||||
imx8ulp_evk
|
||||
imx91_11x11_evk
|
||||
imx91_11x11_frdm
|
||||
imx93_9x9_qsb
|
||||
imx93_11x11_evk
|
||||
imx93_frdm
|
||||
|
||||
@@ -0,0 +1,25 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2025 NXP
|
||||
*/
|
||||
|
||||
#ifndef __IMX91_FRDM_H
|
||||
#define __IMX91_FRDM_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/stringify.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#define CFG_SYS_UBOOT_BASE \
|
||||
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
|
||||
|
||||
#define CFG_SYS_INIT_RAM_ADDR 0x80000000
|
||||
#define CFG_SYS_INIT_RAM_SIZE 0x200000
|
||||
|
||||
#define CFG_SYS_SDRAM_BASE 0x80000000
|
||||
#define PHYS_SDRAM 0x80000000
|
||||
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
|
||||
|
||||
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user