board: bsh: imx6ulz_smm_m2: Match SPL DDR settings to DCD table
When using SPL on i.mx6 we frequently notice some DDR initialization mismatches between the SPL code and the non-SPL code. As the non-SPL code have been tested for long time and proves to be reliable, let's configure the DDR in the exact same way as the non-SPL case. The idea is simple: just use the DCD table and write directly to the DDR registers. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
This commit is contained in:
Michael Trimarchi
committed by
Fabio Estevam
Fabio Estevam
parent
c1ccc4c0f3
commit
da6547acb8
+198
-62
@@ -31,69 +31,208 @@ static void setup_iomux_uart(void)
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imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
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}
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static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
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.grp_addds = 0x00000028,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_b0ds = 0x00000028,
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.grp_ctlds = 0x00000028,
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.grp_b1ds = 0x00000028,
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.grp_ddrpke = 0x00000000,
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.grp_ddrmode = 0x00020000,
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.grp_ddr_type = 0x000c0000,
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struct dram_cfg_param {
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unsigned int reg;
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unsigned int val;
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};
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static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_dqm0 = 0x00000028,
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.dram_dqm1 = 0x00000028,
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.dram_ras = 0x00000028,
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.dram_cas = 0x00000028,
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.dram_odt0 = 0x00000028,
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.dram_odt1 = 0x00000028,
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.dram_sdba2 = 0x00000000,
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.dram_sdclk_0 = 0x00000028,
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.dram_sdqs0 = 0x00000028,
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.dram_sdqs1 = 0x00000028,
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.dram_reset = 0x000c0028,
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struct dram_timing_info {
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const struct dram_cfg_param *ddrc_cfg;
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unsigned int ddrc_cfg_num;
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};
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static struct mx6_mmdc_calibration mx6_mmcd_calib = {
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.p0_mpwldectrl0 = 0x00000000,
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.p0_mpwldectrl1 = 0x00100010,
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.p0_mpdgctrl0 = 0x414c014c,
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.p0_mpdgctrl1 = 0x00000000,
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.p0_mprddlctl = 0x40403a42,
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.p0_mpwrdlctl = 0x4040342e,
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static const struct dram_cfg_param ddr_ddrc_cfg_128mb[] = {
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/* IOMUX */
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/* DDR IO Type: */
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{0x020e04b4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
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{0x020e04ac, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
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/* Clock: */
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{0x020e027c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
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/* Address: */
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{0x020e0250, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
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{0x020e024c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
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{0x020e0490, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
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/* Control: */
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{0x020e0288, 0x000C0028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
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{0x020e0270, 0x00000000}, /*
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* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured
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* using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
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*/
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{0x020e0260, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
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{0x020e0264, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
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{0x020e04a0, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
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/* Data Strobes: */
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{0x020e0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
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{0x020e0280, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
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{0x020e0284, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
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/* Data: */
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{0x020e04b0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
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{0x020e0498, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
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{0x020e04a4, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
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{0x020e0244, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
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{0x020e0248, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
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/*
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* =============================================================================
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* DDR Controller Registers
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* =============================================================================
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* Manufacturer:ISSI
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* Device Part Number:IS43TR16640BL-125JBLI
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* Clock Freq.: 400MHz
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* Density per CS in Gb: 1
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* Chip Selects used:1
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* Number of Banks:8
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* Row address: 13
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* Column address: 10
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* Data bus width16
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* =============================================================================
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*/
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{0x021b001c, 0x00008000}, /*
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* MMDC0_MDSCR, set the Configuration request bit during
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* MMDC set up
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*/
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/*
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* =============================================================================
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* Calibration setup
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* =============================================================================
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*/
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{0x021b0800, 0xA1390003}, /*
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* DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic
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* HW ZQ calibration.
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*/
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/*
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* For target board, may need to run write leveling calibration to fine tune these
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* settings.
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*/
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{0x021b080c, 0x00000000},
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/* Read DQS Gating calibration */
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{0x021b083c, 0x41480148}, /* MPDGCTRL0 PHY0 */
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/* Read calibration */
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{0x021b0848, 0x40403A3E}, /* MPRDDLCTL PHY0 */
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/* Write calibration */
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{0x021b0850, 0x4040362E}, /* MPWRDLCTL PHY0 */
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/*
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* Read data bit delay: 3 is the recommended default value, although out of reset
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* value is 0
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*/
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{0x021b081c, 0x33333333}, /* MMDC_MPRDDQBY0DL */
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{0x021b0820, 0x33333333}, /* MMDC_MPRDDQBY1DL */
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/* Write data bit delay: */
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{0x021b082c, 0xF3333333}, /* MMDC_MPWRDQBY0DL */
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{0x021b0830, 0xF3333333}, /* MMDC_MPWRDQBY1DL */
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/* DQS&CLK Duty Cycle */
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{0x021b08c0, 0x00944009}, /* [MMDC_MPDCCR] MMDC Duty Cycle Control Register */
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/* Complete calibration by forced measurement: */
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{0x021b08b8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */
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/*
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* =============================================================================
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* Calibration setup end
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* =============================================================================
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*/
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/* MMDC init: */
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{0x021b0004, 0x0002002D}, /* MMDC0_MDPDC */
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{0x021b0008, 0x1B333030}, /* MMDC0_MDOTC */
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{0x021b000c, 0x2B2F52F3}, /* MMDC0_MDCFG0 */
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{0x021b0010, 0xB66D0B63}, /* MMDC0_MDCFG1 */
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{0x021b0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */
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/*
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* MDMISC: RALAT kept to the high level of 5.
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* MDMISC: consider reducing RALAT if your 528MHz board design allow that.
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* Lower RALAT benefits:
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* a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
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* b. Small performance improvement
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*/
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{0x021b0018, 0x00211740}, /* MMDC0_MDMISC */
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{0x021b001c, 0x00008000}, /*
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* MMDC0_MDSCR, set the Configuration request
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* bit during MMDC set up
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*/
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{0x021b002c, 0x000026D2}, /* MMDC0_MDRWD */
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{0x021b0030, 0x002F1023}, /* MMDC0_MDOR */
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{0x021b0040, 0x00000043}, /* Chan0 CS0_END */
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{0x021b0000, 0x82180000}, /* MMDC0_MDCTL */
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{0x021b0890, 0x00400000}, /* MPPDCMPR2 */
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/* Mode register writes */
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{0x021b001c, 0x02808032}, /* MMDC0_MDSCR, MR2 write, CS0 */
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{0x021b001c, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */
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{0x021b001c, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */
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{0x021b001c, 0x15208030}, /* MMDC0_MDSCR, MR0write, CS0 */
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{0x021b001c, 0x04008040}, /*
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* MMDC0_MDSCR, ZQ calibration command sent to
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* device on CS0
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*/
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{0x021b0020, 0x00007800}, /* MMDC0_MDREF */
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{0x021b0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */
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{0x021b0004, 0x0002552D}, /* MMDC0_MDPDC now SDCTL power down enabled */
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{0x021b0404, 0x00011006}, /*
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* MMDC0_MAPSR ADOPT power down enabled,
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* MMDC will enter automatically to self-refresh
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* while the number of idle cycle reached.
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*/
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{0x021b001c, 0x00000000}, /*
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* MMDC0_MDSCR, clear this register
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* (especially the configuration bit as initialization
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* is complete)
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*/
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};
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static struct mx6_ddr_sysinfo ddr_sysinfo = {
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.dsize = 0,
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.cs1_mirror = 0,
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.cs_density = 32,
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.ncs = 1,
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.bi_on = 1,
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.rtt_nom = 1,
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.rtt_wr = 0,
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.ralat = 5,
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.walat = 1,
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.mif3_mode = 3,
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.rst_to_cke = 0x23, /* 33 cycles (JEDEC value for DDR3) - total of 500 us */
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.sde_to_rst = 0x10, /* 14 cycles (JEDEC value for DDR3) - total of 200 us */
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.refsel = 1,
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.refr = 3,
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static struct dram_timing_info dram_timing_128mb = {
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.ddrc_cfg = ddr_ddrc_cfg_128mb,
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.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_128mb),
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};
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static struct mx6_ddr3_cfg mem_ddr = {
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.mem_speed = 1333,
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.density = 2,
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.width = 16,
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.banks = 8,
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.rowaddr = 13,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1350,
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.trcmin = 4950,
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.trasmin = 3600,
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};
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static void ddr_cfg_write(const struct dram_timing_info *dram_timing_info)
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{
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int i;
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const struct dram_cfg_param *ddrc_cfg = dram_timing_info->ddrc_cfg;
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const int ddrc_cfg_num = dram_timing_info->ddrc_cfg_num;
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for (i = 0; i < ddrc_cfg_num; i++) {
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debug("Writing 0x%x to register 0x%x\n", ddrc_cfg->val,
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ddrc_cfg->reg);
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writel(ddrc_cfg->val, ddrc_cfg->reg);
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ddrc_cfg++;
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}
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}
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static void spl_dram_init(void)
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{
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struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
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clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */
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clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */
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ddr_cfg_write(&dram_timing_128mb);
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}
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static void ccgr_init(void)
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{
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@@ -108,20 +247,17 @@ static void ccgr_init(void)
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writel(0xFFFFFFFF, &ccm->CCGR6);
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}
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static void imx6ul_spl_dram_cfg(void)
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{
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mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
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mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
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}
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void board_init_f(ulong dummy)
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{
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ccgr_init();
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/* DDR initialization */
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spl_dram_init();
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arch_cpu_init();
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timer_init();
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setup_iomux_uart();
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preloader_console_init();
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imx6ul_spl_dram_cfg();
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}
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void reset_cpu(void)
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