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Merge in all changes from the next branch now that the release is out.
This commit is contained in:
Tom Rini
2024-04-02 07:03:25 -04:00
parent 25049ad560 bc39e06778
commit d312d9831f
12458 changed files with 2225742 additions and 12150 deletions
Download Patch File Download Diff File Expand all files Collapse all files
.azure-pipelines.yml
+6 -5
View File
@@ -2,7 +2,7 @@ variables:
windows_vm: windows-2019
ubuntu_vm: ubuntu-22.04
macos_vm: macOS-12
ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20240125-12Feb2024
ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20240227-14Mar2024
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root.
@@ -65,7 +65,8 @@ stages:
# have no matches.
- script: git grep -E '^#[[:blank:]]*(define|undef)[[:blank:]]*CONFIG_'
:^doc/ :^arch/arm/dts/ :^scripts/kconfig/lkc.h
:^include/linux/kconfig.h :^tools/ && exit 1 || exit 0
:^include/linux/kconfig.h :^tools/ :^dts/upstream/ &&
exit 1 || exit 0
- job: docs
displayName: 'Build documentation'
@@ -276,16 +277,16 @@ stages:
TEST_PY_TEST_SPEC: "version"
sandbox_clang:
TEST_PY_BD: "sandbox"
OVERRIDE: "-O clang-16"
OVERRIDE: "-O clang-17"
sandbox_clang_asan:
TEST_PY_BD: "sandbox"
OVERRIDE: "-O clang-16 -a ASAN"
OVERRIDE: "-O clang-17 -a ASAN"
TEST_PY_TEST_SPEC: "version"
sandbox64:
TEST_PY_BD: "sandbox64"
sandbox64_clang:
TEST_PY_BD: "sandbox64"
OVERRIDE: "-O clang-16"
OVERRIDE: "-O clang-17"
sandbox_spl:
TEST_PY_BD: "sandbox_spl"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
.gitignore
+1
View File
@@ -63,6 +63,7 @@ fit-dtb.blob*
/spl/
/tpl/
/defconfig
/generated_defconfig
#
# Generated include files
.gitlab-ci.yml
+5 -4
View File
@@ -10,7 +10,7 @@ default:
# Grab our configured image. The source for this is found
# in the u-boot tree at tools/docker/Dockerfile
image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20240125-12Feb2024
image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20240227-14Mar2024
# We run some tests in different order, to catch some failures quicker.
stages:
@@ -156,7 +156,8 @@ check for new CONFIG symbols outside Kconfig:
# have no matches.
- git grep -E '^#[[:blank:]]*(define|undef)[[:blank:]]*CONFIG_'
:^doc/ :^arch/arm/dts/ :^scripts/kconfig/lkc.h
:^include/linux/kconfig.h :^tools/ && exit 1 || exit 0
:^include/linux/kconfig.h :^tools/ :^dts/upstream/ &&
exit 1 || exit 0
# build documentation
docs:
@@ -250,7 +251,7 @@ sandbox test.py:
sandbox with clang test.py:
variables:
TEST_PY_BD: "sandbox"
OVERRIDE: "-O clang-16"
OVERRIDE: "-O clang-17"
<<: *buildman_and_testpy_dfn
sandbox64 test.py:
@@ -261,7 +262,7 @@ sandbox64 test.py:
sandbox64 with clang test.py:
variables:
TEST_PY_BD: "sandbox64"
OVERRIDE: "-O clang-16"
OVERRIDE: "-O clang-17"
<<: *buildman_and_testpy_dfn
sandbox_spl test.py:
Kconfig
+1 -1
View File
@@ -265,7 +265,7 @@ config SYS_MALLOC_F_LEN
hex "Size of malloc() pool before relocation"
depends on SYS_MALLOC_F
default 0x400 if M68K || PPC || ROCKCHIP_PX30 || ROCKCHIP_RK3036 || \
ROCKCHIP_RK3308 || ROCKCHIP_RV1108
ROCKCHIP_RV1108
default 0x600 if ARCH_ZYNQMP_R5 || ARCH_ZYNQMP
default 0x800 if ARCH_ZYNQ || ROCKCHIP_RK3128 || ROCKCHIP_RK3188 || \
ROCKCHIP_RK322X || X86
MAINTAINERS
+20 -11
View File
@@ -55,6 +55,7 @@ M: Simon Glass <sjg@chromium.org>
S: Maintained
F: board/emulation/configs/acpi.config
F: cmd/acpi.c
F: include/acpi/
F: lib/acpi/
ANDROID AB
@@ -603,18 +604,22 @@ M: Caleb Connolly <caleb.connolly@linaro.org>
M: Neil Armstrong <neil.armstrong@linaro.org>
R: Sumit Garg <sumit.garg@linaro.org>
S: Maintained
F: arch/arm/mach-snapdragon/
F: drivers/button/button-qcom-pmic.c
F: drivers/clk/qcom/
F: arch/arm/dts/msm8*.dtsi
F: arch/arm/dts/pm8???.dtsi
F: arch/arm/dts/pms405.dtsi
F: arch/arm/dts/sdm845.dtsi
F: drivers/*/*/pm8???-*
F: drivers/gpio/msm_gpio.c
F: drivers/mmc/msm_sdhci.c
F: drivers/phy/msm8916-usbh-phy.c
F: drivers/pinctrl/qcom/
F: drivers/serial/serial_msm.c
F: drivers/serial/serial_msm_geni.c
F: drivers/smem/msm_smem.c
F: drivers/spmi/spmi-msm.c
F: drivers/usb/host/ehci-msm.c
N: qcom
N: snapdragon
N: qualcomm
ARM STI
M: Patrice Chotard <patrice.chotard@foss.st.com>
@@ -679,13 +684,6 @@ F: tools/stm32image.c
N: stm
N: stm32
ARM STM STV0991
M: Vikas Manocha <vikas.manocha@st.com>
S: Maintained
F: arch/arm/cpu/armv7/stv0991/
F: arch/arm/include/asm/arch-stv0991/
ARM SUNXI
M: Jagan Teki <jagan@amarulasolutions.com>
M: Andre Przywara <andre.przywara@arm.com>
@@ -989,6 +987,11 @@ F: cmd/cyclic.c
F: common/cyclic.c
F: include/cyclic.h
DEVICETREE REBASING SUBTREE
M: Sumit Garg <sumit.garg@linaro.org>
S: Maintained
F: dts/upstream/
DFU
M: Lukasz Majewski <lukma@denx.de>
M: Mattijs Korpershoek <mkorpershoek@baylibre.com>
@@ -1369,6 +1372,12 @@ M: Simon Glass <sjg@chromium.org>
S: Maintained
F: tools/patman/
PCIe DWC IMX
M: Sumit Garg <sumit.garg@linaro.org>
S: Maintained
F: drivers/pci/pcie_dw_imx.c
F: drivers/phy/phy-imx8m-pcie.c
PCI Endpoint
M: Ramon Fried <rfried.dev@gmail.com>
S: Maintained
Makefile
+49 -15
View File
@@ -835,7 +835,8 @@ UBOOTINCLUDE := \
-I$(srctree)/arch/arm/thumb1/include), \
-I$(srctree)/arch/arm/thumb1/include)) \
-I$(srctree)/arch/$(ARCH)/include \
-include $(srctree)/include/linux/kconfig.h
-include $(srctree)/include/linux/kconfig.h \
-I$(srctree)/dts/upstream/include
NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
@@ -1158,15 +1159,41 @@ endif
@# disabling OF_BOARD.
$(call cmd,ofcheck,$(KCONFIG_CONFIG))
PHONY += dtbs
PHONY += dtbs dtbs_check
dtbs: dts/dt.dtb
@:
dts/dt.dtb: u-boot
dts/dt.dtb: dtbs_prepare u-boot
$(Q)$(MAKE) $(build)=dts dtbs
dtbs_prepare: prepare3
ifneq ($(filter dtbs_check, $(MAKECMDGOALS)),)
export CHECK_DTBS=y
endif
ifneq ($(CHECK_DTBS),)
dtbs_prepare: dt_binding_check
endif
dtbs_check: dt_binding_check dtbs
DT_BINDING_DIR := dts/upstream/Bindings
dt_binding_check: scripts_dtc
$(Q)$(MAKE) $(build)=$(DT_BINDING_DIR) $(DT_BINDING_DIR)/processed-schema.json
quiet_cmd_copy = COPY $@
cmd_copy = cp $< $@
ifeq ($(CONFIG_OF_UPSTREAM),y)
ifeq ($(CONFIG_ARM64),y)
dt_dir := dts/upstream/src/arm64
else
dt_dir := dts/upstream/src/$(ARCH)
endif
else
dt_dir := arch/$(ARCH)/dts
endif
ifeq ($(CONFIG_MULTI_DTB_FIT),y)
ifeq ($(CONFIG_MULTI_DTB_FIT_LZO),y)
@@ -1192,7 +1219,7 @@ endif
MKIMAGEFLAGS_fit-dtb.blob = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-a 0 -e 0 -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) -d /dev/null
$(patsubst %,-b $(dt_dir)/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) -d /dev/null
MKIMAGEFLAGS_fit-dtb.blob += -B 0x8
@@ -1273,12 +1300,17 @@ OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),$(if $(CONFIG_OF_SEPARATE),-R .bootpg -R .resetvec))
binary_size_check: u-boot-nodtb.bin FORCE
@file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
@file_size=$(shell wc -c u-boot-nodtb.bin | awk '{ print $$1 }') ; \
map_size=$(shell cat u-boot.map | \
awk '/_image_copy_start/ {start = $$1} /_image_binary_end/ {end = $$1} END {if (start != "" && end != "") print "ibase=16; " toupper(end) " - " toupper(start)}' \
| sed 's/0X//g' \
| bc); \
if [ "" != "$$map_size" ]; then \
awk ' \
/_image_copy_start/ { start = $$1 } \
/_image_binary_end/ { end = $$1 } \
END { \
if (start != "" && end != "") \
print end " " start; \
}' \
| sh -c 'read end start && echo $$((end - start))'); \
if [ -n "$$map_size" ]; then \
if test $$map_size -ne $$file_size; then \
echo "u-boot.map shows a binary size of $$map_size" >&2 ; \
echo " but u-boot-nodtb.bin shows $$file_size" >&2 ; \
@@ -1345,7 +1377,7 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
build -u -d u-boot.dtb -O . -m \
--allow-missing $(if $(BINMAN_ALLOW_MISSING),--ignore-missing) \
-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
-I arch/$(ARCH)/dts -a of-list=$(CONFIG_OF_LIST) \
-I $(dt_dir) -a of-list=$(CONFIG_OF_LIST) \
$(foreach f,$(BINMAN_INDIRS),-I $(f)) \
-a atf-bl31-path=${BL31} \
-a tee-os-path=${TEE} \
@@ -1381,7 +1413,7 @@ ifneq ($(CONFIG_USE_SPL_FIT_GENERATOR),)
U_BOOT_ITS := u-boot.its
$(U_BOOT_ITS): $(U_BOOT_ITS_DEPS) FORCE
$(srctree)/$(CONFIG_SPL_FIT_GENERATOR) \
$(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) > $@
$(patsubst %,$(dt_dir)/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) > $@
endif
endif
@@ -1390,9 +1422,9 @@ MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-p $(CONFIG_FIT_EXTERNAL_OFFSET) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(DEVICE_TREE))) \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST)))
$(patsubst %,-b $(dt_dir)/%.dtb,$(subst ",,$(DEVICE_TREE))) \
$(patsubst %,-b $(dt_dir)/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) \
$(patsubst %,-b $(dt_dir)/%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST)))
else
MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
@@ -1804,7 +1836,8 @@ ENV_FILE := $(if $(ENV_SOURCE_FILE),$(ENV_FILE_CFG),$(wildcard $(ENV_FILE_BOARD)
quiet_cmd_gen_envp = ENVP $@
cmd_gen_envp = \
if [ -s "$(ENV_FILE)" ]; then \
$(CPP) -P $(CFLAGS) -x assembler-with-cpp -D__ASSEMBLY__ \
$(CPP) -P $(CFLAGS) -x assembler-with-cpp -undef \
-D__ASSEMBLY__ \
-D__UBOOT_CONFIG__ \
-I . -I include -I $(srctree)/include \
-include linux/kconfig.h -include include/config.h \
@@ -2205,6 +2238,7 @@ clean: $(clean-dirs)
-o -name modules.builtin -o -name '.tmp_*.o.*' \
-o -name 'dsdt_generated.aml' -o -name 'dsdt_generated.asl.tmp' \
-o -name 'dsdt_generated.c' \
-o -name 'generated_defconfig' \
-o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \) \
-type f -print | xargs rm -f
arch/Kconfig
+16 -1
View File
@@ -20,6 +20,12 @@ config SYS_CACHE_SHIFT_6
config SYS_CACHE_SHIFT_7
bool
config 32BIT
bool
config 64BIT
bool
config SYS_CACHELINE_SIZE
int
default 128 if SYS_CACHE_SHIFT_7
@@ -361,7 +367,16 @@ config SYS_BOARD
leave this option empty.
config SYS_CONFIG_NAME
string
string "Board header file" if ARCH_MESON || ARCH_VERSAL || \
ARCH_VERSAL_NET || ARCH_ZYNQ || ARCH_ZYNQMP || \
ARCH_ZYNQMP_R5 || MICROBLAZE || NIOS2
default "meson64" if ARCH_MESON
default "microblaze-generic" if MICROBLAZE
default "xilinx_versal" if ARCH_VERSAL
default "xilinx_versal_net" if ARCH_VERSAL_NET
default "xilinx_zynqmp" if ARCH_ZYNQMP
default "xilinx_zynqmp_r5" if ARCH_ZYNQMP_R5
default "zynq-common" if ARCH_ZYNQ
help
This option should contain the base name of board header file.
The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
arch/arm/Kconfig
+19 -25
View File
@@ -6,6 +6,7 @@ config SYS_ARCH
config ARM64
bool
select 64BIT
select PHYS_64BIT
select SYS_CACHE_SHIFT_6
imply SPL_SEPARATE_BSS
@@ -28,6 +29,7 @@ config COUNTER_FREQUENCY
ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
default 100000000 if ARCH_ZYNQMP
default 200000000 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5
default 0
help
For platforms with ARMv8-A and ARMv7-A which features a system
@@ -122,6 +124,15 @@ config GIC_V3_ITS
ARM GICV3 has limitation, once the LPI table is enabled, LPI
configuration table can not be re-programmed, unless GICV3 reset.
config GICV3_SUPPORT_GIC600
bool "ARM GICV3 GIC600 SUPPORT"
help
ARM GIC-600 IP complies with ARM GICv3 architecture, but among others,
implements a power control register in the Redistributor frame.This
register must be programmed to mark the frame as powered on, before
accessing other registers in the frame. Rest of initialization sequence
remains the same.
config STATIC_RELA
bool
default y if ARM64
@@ -631,20 +642,6 @@ config ARCH_ORION5X
select SPL_SEPARATE_BSS if SPL
select TIMER
config TARGET_STV0991
bool "Support stv0991"
select CPU_V7A
select DM
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
select GPIO_EXTRA_HEADER
select PL01X_SERIAL
select MTD
select SPI
select SPI_FLASH
imply CMD_DM
config ARCH_BCM283X
bool "Broadcom BCM283X family"
select DM
@@ -699,15 +696,6 @@ config TARGET_BCMNS
ARMv7 Cortex-A9 SoC family including BCM4708, BCM47094,
BCM5301x etc.
config TARGET_BCMNS2
bool "Support Broadcom Northstar2"
select ARM64
select GPIO_EXTRA_HEADER
help
Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
ARMv8 Cortex-A57 processors targeting a broad range of networking
applications.
config TARGET_BCMNS3
bool "Support Broadcom NS3"
select ARM64
@@ -1096,6 +1084,10 @@ config ARCH_SNAPDRAGON
select OF_SEPARATE
select SMEM
select SPMI
select BOARD_LATE_INIT
select OF_BOARD
select SAVE_PREV_BL_FDT_ADDR
select LINUX_KERNEL_IMAGE_HEADER
imply CMD_DM
config ARCH_SOCFPGA
@@ -1116,6 +1108,8 @@ config ARCH_SOCFPGA
select SPL_LIBGENERIC_SUPPORT
select SPL_OF_CONTROL
select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64
select SPL_SOCFPGA_DT_REG if TARGET_SOCFPGA_SOC64
select SPL_SERIAL
select SPL_SYSRESET
select SPL_WATCHDOG
@@ -1124,7 +1118,8 @@ config ARCH_SOCFPGA
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET
select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \
TARGET_SOCFPGA_SOC64
imply CMD_DM
imply CMD_MTDPARTS
imply CRC32_VERIFY
@@ -2363,7 +2358,6 @@ source "board/samsung/common/Kconfig"
source "board/siemens/common/Kconfig"
source "board/seeed/npi_imx6ull/Kconfig"
source "board/socionext/developerbox/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/tcl/sl50/Kconfig"
source "board/traverse/ten64/Kconfig"
source "board/variscite/dart_6ul/Kconfig"
arch/arm/cpu/armv7/Makefile
-1
View File
@@ -37,7 +37,6 @@ obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_VF610) += vf610/
obj-$(CONFIG_ARCH_S5P4418) += s5p4418/
arch/arm/cpu/armv7/s5p4418/Makefile
+3
View File
@@ -2,5 +2,8 @@
#
# (C) Copyright 2016 Nexell
# Hyunseok, Jung <hsjung@nexell.co.kr>
#
# Copyright (C) 2023 Stefan Bosch <stefan_b@posteo.net>
obj-y += cpu.o
obj-y += relocate.o
arch/arm/cpu/armv7/s5p4418/relocate.S
+24
View File
@@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - S5P4418 specific relocation for ARM U-Boot
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
* Copyright (C) 2023 Stefan Bosch <stefan_b@posteo.net>
*/
#include <asm-offsets.h>
#include <asm/assembler.h>
#include <linux/linkage.h>
ENTRY(relocate_vectors)
/*
* The s5p4418 SoC has the security extensions, so use VBAR to relocate
* the exception vectors.
*/
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
add r0, #0x400 /* vectors are after NSIH + 0x200 */
mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
ret lr
ENDPROC(relocate_vectors)
arch/arm/cpu/armv7/start.S
+29
View File
@@ -152,9 +152,38 @@ ENDPROC(c_runtime_cpu_setup)
*
*************************************************************************/
WEAK(save_boot_params)
#if (IS_ENABLED(CONFIG_BLOBLIST))
/* Calculate the PC-relative address of saved_args */
adr r12, saved_args_offset
ldr r13, saved_args_offset
add r12, r12, r13
/*
* Intentionally swapping r0 with r2 in order to simplify the C
* function we use later.
*/
str r2, [r12]
str r1, [r12, #4]
str r0, [r12, #8]
str r3, [r12, #12]
#endif
b save_boot_params_ret @ back to my caller
ENDPROC(save_boot_params)
#if (IS_ENABLED(CONFIG_BLOBLIST))
saved_args_offset:
.long saved_args - . /* offset from current code to save_args */
.section .data
.align 2
.global saved_args
saved_args:
.rept 4
.word 0
.endr
END(saved_args)
#endif
#ifdef CONFIG_ARMV7_LPAE
WEAK(switch_to_hypervisor)
b switch_to_hypervisor_ret
arch/arm/cpu/armv7/stv0991/Makefile
-7
View File
@@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2014, STMicroelectronics - All Rights Reserved
# Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
obj-y := timer.o clock.o pinmux.o reset.o
obj-y += lowlevel.o
arch/arm/cpu/armv7/stv0991/clock.c
-42
View File
@@ -1,42 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/stv0991_cgu.h>
#include<asm/arch/stv0991_periph.h>
static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
void enable_pll1(void)
{
/* pll1 already configured for 1000Mhz, just need to enable it */
writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01),
&stv0991_cgu_regs->pll1_ctrl);
}
void clock_setup(int peripheral)
{
switch (peripheral) {
case UART_CLOCK_CFG:
writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq);
break;
case ETH_CLOCK_CFG:
enable_pll1();
writel(ETH_CLK_CFG, &stv0991_cgu_regs->eth_freq);
/* Clock selection for ethernet tx_clk & rx_clk*/
writel((readl(&stv0991_cgu_regs->eth_ctrl) & ETH_CLK_MASK)
| ETH_CLK_CTRL, &stv0991_cgu_regs->eth_ctrl);
break;
case QSPI_CLOCK_CFG:
writel(QSPI_CLK_CTRL, &stv0991_cgu_regs->qspi_freq);
break;
default:
break;
}
}
arch/arm/cpu/armv7/stv0991/lowlevel.S
-11
View File
@@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2014 STMicroelectronics
*/
#include <config.h>
#include <linux/linkage.h>
ENTRY(lowlevel_init)
mov pc, lr
ENDPROC(lowlevel_init)
arch/arm/cpu/armv7/stv0991/pinmux.c
-66
View File
@@ -1,66 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#include <asm/io.h>
#include <asm/arch/stv0991_creg.h>
#include <asm/arch/stv0991_periph.h>
#include <asm/arch/hardware.h>
static struct stv0991_creg *const stv0991_creg = \
(struct stv0991_creg *)CREG_BASE_ADDR;
int stv0991_pinmux_config(int peripheral)
{
switch (peripheral) {
case UART_GPIOC_30_31:
/* SSDA/SSCL pad muxing to UART Rx/Dx */
writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) |
CFG_GPIOC_31_UART_RX,
&stv0991_creg->mux12);
writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) |
CFG_GPIOC_30_UART_TX,
&stv0991_creg->mux12);
/* SSDA/SSCL pad config to push pull*/
writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) |
CFG_GPIOC_31_MODE_PP,
&stv0991_creg->cfg_pad6);
writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) |
CFG_GPIOC_30_MODE_HIGH,
&stv0991_creg->cfg_pad6);
break;
case UART_GPIOB_16_17:
/* ethernet rx_6/7 to UART Rx/Dx */
writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) |
CFG_GPIOB_17_UART_RX,
&stv0991_creg->mux7);
writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) |
CFG_GPIOB_16_UART_TX,
&stv0991_creg->mux7);
break;
case ETH_GPIOB_10_31_C_0_4:
writel(readl(&stv0991_creg->mux6) & 0x000000FF,
&stv0991_creg->mux6);
writel(0x00000000, &stv0991_creg->mux7);
writel(0x00000000, &stv0991_creg->mux8);
writel(readl(&stv0991_creg->mux9) & 0xFFF00000,
&stv0991_creg->mux9);
/* Ethernet Voltage configuration to 1.8V*/
writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
ETH_VDD_CFG, &stv0991_creg->vdd_pad1);
writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1);
break;
case QSPI_CS_CLK_PAD:
writel((readl(&stv0991_creg->mux13) & FLASH_CS_NC_MASK) |
CFG_FLASH_CS_NC, &stv0991_creg->mux13);
writel((readl(&stv0991_creg->mux13) & FLASH_CLK_MASK) |
CFG_FLASH_CLK, &stv0991_creg->mux13);
default:
break;
}
return 0;
}
arch/arm/cpu/armv7/stv0991/reset.c
-27
View File
@@ -1,27 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#include <common.h>
#include <cpu_func.h>
#include <asm/io.h>
#include <asm/arch/stv0991_wdru.h>
#include <linux/delay.h>
void reset_cpu(void)
{
puts("System is going to reboot ...\n");
/*
* This 1 second delay will allow the above message
* to be printed before reset
*/
udelay((1000 * 1000));
/* Setting bit 1 of the WDRU unit will reset the SoC */
writel(WDRU_RST_SYS, &stv0991_wd_ru_ptr->wdru_ctrl1);
/* system will restart */
while (1)
;
}
arch/arm/cpu/armv7/stv0991/timer.c
-114
View File
@@ -1,114 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
#include <common.h>
#include <init.h>
#include <time.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-stv0991/hardware.h>
#include <asm/arch-stv0991/stv0991_cgu.h>
#include <asm/arch-stv0991/stv0991_gpt.h>
#include <linux/delay.h>
static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
#define GPT_RESOLUTION (CFG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
DECLARE_GLOBAL_DATA_PTR;
#define timestamp gd->arch.tbl
#define lastdec gd->arch.lastinc
static ulong get_timer_masked(void);
int timer_init(void)
{
/* Timer1 clock configuration */
writel(TIMER1_CLK_CFG, &stv0991_cgu_regs->tim_freq);
writel(readl(&stv0991_cgu_regs->cgu_enable_2) |
TIMER1_CLK_EN, &stv0991_cgu_regs->cgu_enable_2);
/* Stop the timer */
writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1);
writel(GPT_PRESCALER_128, &gpt1_regs_ptr->psc);
/* Configure timer for auto-reload */
writel(readl(&gpt1_regs_ptr->cr1) | GPT_MODE_AUTO_RELOAD,
&gpt1_regs_ptr->cr1);
/* load value for free running */
writel(GPT_FREE_RUNNING, &gpt1_regs_ptr->arr);
/* start timer */
writel(readl(&gpt1_regs_ptr->cr1) | GPT_CR1_CEN,
&gpt1_regs_ptr->cr1);
/* Reset the timer */
lastdec = READ_TIMER();
timestamp = 0;
return 0;
}
/*
* timer without interrupts
*/
ulong get_timer(ulong base)
{
return (get_timer_masked() / GPT_RESOLUTION) - base;
}
void __udelay(unsigned long usec)
{
ulong tmo;
ulong start = get_timer_masked();
ulong tenudelcnt = CFG_SYS_HZ_CLOCK / (1000 * 100);
ulong rndoff;
rndoff = (usec % 10) ? 1 : 0;
/* tenudelcnt timer tick gives 10 microsecconds delay */
tmo = ((usec / 10) + rndoff) * tenudelcnt;
while ((ulong) (get_timer_masked() - start) < tmo)
;
}
static ulong get_timer_masked(void)
{
ulong now = READ_TIMER();
if (now >= lastdec) {
/* normal mode */
timestamp += now - lastdec;
} else {
/* we have an overflow ... */
timestamp += now + GPT_FREE_RUNNING - lastdec;
}
lastdec = now;
return timestamp;
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}
arch/arm/cpu/armv8/cache.S
+9
View File
@@ -20,6 +20,7 @@
*
* x0: cache level
* x1: 0 clean & invalidate, 1 invalidate only
* x16: FEAT_CCIDX
* x2~x9: clobbered
*/
.pushsection .text.__asm_dcache_level, "ax"
@@ -29,8 +30,14 @@ ENTRY(__asm_dcache_level)
isb /* sync change of cssidr_el1 */
mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
ubfx x2, x6, #0, #3 /* x2 <- log2(cache line size)-4 */
cbz x16, 3f /* check for FEAT_CCIDX */
ubfx x3, x6, #3, #21 /* x3 <- number of cache ways - 1 */
ubfx x4, x6, #32, #24 /* x4 <- number of cache sets - 1 */
b 4f
3:
ubfx x3, x6, #3, #10 /* x3 <- number of cache ways - 1 */
ubfx x4, x6, #13, #15 /* x4 <- number of cache sets - 1 */
4:
add x2, x2, #4 /* x2 <- log2(cache line size) */
clz w5, w3 /* bit position of #ways */
/* x12 <- cache level << 1 */
@@ -74,6 +81,8 @@ ENTRY(__asm_dcache_all)
ubfx x11, x10, #24, #3 /* x11 <- loc */
cbz x11, finished /* if loc is 0, exit */
mov x15, lr
mrs x16, s3_0_c0_c7_2 /* read value of id_aa64mmfr2_el1*/
ubfx x16, x16, #20, #4 /* save FEAT_CCIDX identifier in x16 */
mov x0, #0 /* start flush at cache level 0 */
/* x0 <- cache level */
/* x10 <- clidr_el1 */
arch/arm/cpu/armv8/start.S
+23
View File
@@ -370,5 +370,28 @@ ENTRY(c_runtime_cpu_setup)
ENDPROC(c_runtime_cpu_setup)
WEAK(save_boot_params)
#if (IS_ENABLED(CONFIG_BLOBLIST))
/* Calculate the PC-relative address of saved_args */
adr x9, saved_args_offset
ldr w10, saved_args_offset
add x9, x9, w10, sxtw
stp x0, x1, [x9]
stp x2, x3, [x9, #16]
#endif
b save_boot_params_ret /* back to my caller */
ENDPROC(save_boot_params)
#if (IS_ENABLED(CONFIG_BLOBLIST))
saved_args_offset:
.long saved_args - . /* offset from current code to save_args */
.section .data
.align 2
.global saved_args
saved_args:
.rept 4
.dword 0
.endr
END(saved_args)
#endif
arch/arm/cpu/armv8/u-boot-spl.lds
+10 -16
View File
@@ -21,9 +21,9 @@ OUTPUT_ARCH(aarch64)
ENTRY(_start)
SECTIONS
{
__image_copy_start = ADDR(.text);
.text : {
. = ALIGN(8);
__image_copy_start = .;
CPUDIR/start.o (.text*)
*(.text*)
} >.sram
@@ -51,10 +51,8 @@ SECTIONS
KEEP(*(SORT(__u_boot_list*)));
} >.sram
.image_copy_end : {
. = ALIGN(8);
*(.__image_copy_end)
} >.sram
. = ALIGN(8);
__image_copy_end = .;
.end : {
. = ALIGN(8);
@@ -63,18 +61,11 @@ SECTIONS
_image_binary_end = .;
.bss_start (NOLOAD) : {
. = ALIGN(8);
KEEP(*(.__bss_start));
} >.sdram
.bss (NOLOAD) : {
.bss : {
__bss_start = .;
*(.bss*)
. = ALIGN(8);
} >.sdram
.bss_end (NOLOAD) : {
KEEP(*(.__bss_end));
. = ALIGN(8);
__bss_end = .;
} >.sdram
/DISCARD/ : { *(.rela*) }
@@ -89,3 +80,6 @@ SECTIONS
#include "linux-kernel-image-header-vars.h"
#endif
}
ASSERT(ADDR(.bss) % 8 == 0, \
".bss must be 8-byte aligned");
arch/arm/cpu/armv8/u-boot.lds
+11 -32
View File
@@ -21,9 +21,9 @@ SECTIONS
. = 0x00000000;
. = ALIGN(8);
__image_copy_start = ADDR(.text);
.text :
{
*(.__image_copy_start)
CPUDIR/start.o (.text*)
}
@@ -115,8 +115,6 @@ SECTIONS
KEEP(*(SORT(__u_boot_list*)));
}
. = ALIGN(8);
.efi_runtime_rel : {
__efi_runtime_rel_start = .;
*(.rel*.efi_runtime)
@@ -125,43 +123,24 @@ SECTIONS
}
. = ALIGN(8);
.image_copy_end :
{
*(.__image_copy_end)
}
. = ALIGN(8);
.rel_dyn_start :
{
*(.__rel_dyn_start)
}
__image_copy_end = .;
.rela.dyn : {
__rel_dyn_start = .;
*(.rela*)
}
.rel_dyn_end :
{
*(.__rel_dyn_end)
__rel_dyn_end = .;
}
_end = .;
. = ALIGN(8);
.bss_start : {
KEEP(*(.__bss_start));
}
.bss : {
/*
* arch/arm/lib/crt0_64.S assumes __bss_start - __bss_end % 8 == 0
*/
.bss ALIGN(8) : {
__bss_start = .;
*(.bss*)
. = ALIGN(8);
}
.bss_end : {
KEEP(*(.__bss_end));
. = ALIGN(8);
__bss_end = .;
}
/DISCARD/ : { *(.dynsym) }
arch/arm/cpu/u-boot-spl.lds
+1 -1
View File
@@ -14,9 +14,9 @@ SECTIONS
. = 0x00000000;
. = ALIGN(4);
__image_copy_start = ADDR(.text);
.text :
{
__image_copy_start = .;
*(.vectors)
CPUDIR/start.o (.text*)
*(.text*)
arch/arm/cpu/u-boot.lds
+20 -52
View File
@@ -35,26 +35,20 @@ SECTIONS
. = 0x00000000;
. = ALIGN(4);
__image_copy_start = ADDR(.text);
.text :
{
*(.__image_copy_start)
*(.vectors)
CPUDIR/start.o (.text*)
}
/* This needs to come before *(.text*) */
.__efi_runtime_start : {
*(.__efi_runtime_start)
}
.efi_runtime : {
__efi_runtime_start = .;
*(.text.efi_runtime*)
*(.rodata.efi_runtime*)
*(.data.efi_runtime*)
}
.__efi_runtime_stop : {
*(.__efi_runtime_stop)
__efi_runtime_stop = .;
}
.text_rest :
@@ -152,42 +146,24 @@ SECTIONS
KEEP(*(SORT(__u_boot_list*)));
}
. = ALIGN(4);
.efi_runtime_rel_start :
{
*(.__efi_runtime_rel_start)
}
.efi_runtime_rel : {
__efi_runtime_rel_start = .;
*(.rel*.efi_runtime)
*(.rel*.efi_runtime.*)
}
.efi_runtime_rel_stop :
{
*(.__efi_runtime_rel_stop)
__efi_runtime_rel_stop = .;
}
. = ALIGN(4);
__image_copy_end = .;
.image_copy_end :
{
*(.__image_copy_end)
}
.rel_dyn_start :
{
*(.__rel_dyn_start)
}
.rel.dyn : {
/*
* if CONFIG_USE_ARCH_MEMSET is not selected __bss_end - __bss_start
* needs to be a multiple of 4 and we overlay .bss with .rel.dyn
*/
.rel.dyn ALIGN(4) : {
__rel_dyn_start = .;
*(.rel*)
}
.rel_dyn_end :
{
*(.__rel_dyn_end)
__rel_dyn_end = .;
}
.end :
@@ -207,23 +183,15 @@ SECTIONS
}
/*
* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
* __bss_base and __bss_limit are for linker only (overlay ordering)
* These sections occupy the same memory, but their lifetimes do
* not overlap: U-Boot initializes .bss only after applying dynamic
* relocations and therefore after it doesn't need .rel.dyn any more.
*/
.bss_start __rel_dyn_start (OVERLAY) : {
KEEP(*(.__bss_start));
__bss_base = .;
}
.bss __bss_base (OVERLAY) : {
.bss ADDR(.rel.dyn) (OVERLAY): {
__bss_start = .;
*(.bss*)
. = ALIGN(4);
__bss_limit = .;
}
.bss_end __bss_limit (OVERLAY) : {
KEEP(*(.__bss_end));
. = ALIGN(4);
__bss_end = .;
}
.dynsym _image_binary_end : { *(.dynsym) }
arch/arm/dts/Makefile
+30 -42
View File
@@ -174,6 +174,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-anbernic-rgxx3.dtb \
rk3566-pinetab2-v0.1.dtb \
rk3566-pinetab2-v2.0.dtb \
rk3566-quartz64-a.dtb \
rk3566-quartz64-b.dtb \
rk3566-radxa-cm3-io.dtb \
@@ -191,16 +193,20 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588s-coolpi-4b.dts \
rk3588-coolpi-cm5-evb.dts \
rk3588-edgeble-neu6a-io.dtb \
rk3588-edgeble-neu6b-io.dtb \
rk3588-evb1-v10.dtb \
rk3588-generic.dtb \
rk3588-jaguar.dtb \
rk3588-nanopc-t6.dtb \
rk3588s-orangepi-5.dtb \
rk3588-orangepi-5-plus.dtb \
rk3588-quartzpro64.dtb \
rk3588-turing-rk1.dtb \
rk3588s-rock-5a.dtb \
rk3588-rock-5b.dtb
rk3588-rock-5b.dtb \
rk3588-turing-rk1.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
@@ -216,14 +222,6 @@ dtb-$(CONFIG_ARCH_MESON) += \
meson-a1-ad401.dtb \
meson-axg-s400.dtb \
meson-axg-jethome-jethub-j100.dtb \
meson-gxbb-kii-pro.dtb \
meson-gxbb-nanopi-k2.dtb \
meson-gxbb-odroidc2.dtb \
meson-gxbb-nanopi-k2.dtb \
meson-gxbb-p200.dtb \
meson-gxbb-p201.dtb \
meson-gxbb-wetek-hub.dtb \
meson-gxbb-wetek-play2.dtb \
meson-gxl-s805x-libretech-ac.dtb \
meson-gxl-s905d-libretech-pc.dtb \
meson-gxl-s905w-jethome-jethub-j80.dtb \
@@ -548,6 +546,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_agilex_socdk.dtb \
socfpga_agilex5_socdk.dtb \
socfpga_arria5_secu1.dtb \
socfpga_arria5_socdk.dtb \
socfpga_arria10_chameleonv3_270_2.dtb \
@@ -577,7 +576,6 @@ dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
am574x-idk.dtb \
am572x-idk.dtb \
am571x-idk.dtb
dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
ls1021a-qds-lpuart.dtb \
@@ -632,10 +630,11 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \
dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb
dtb-$(CONFIG_TARGET_QCS404EVB) += qcs404-evb.dtb
dtb-$(CONFIG_ARCH_SNAPDRAGON) += apq8016-sbc.dtb \
apq8096-db820c.dtb \
sdm845-db845c.dtb \
sdm845-samsung-starqltechn.dtb \
qcs404-evb-4000.dtb
dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
@@ -1075,7 +1074,6 @@ dtb-$(CONFIG_ARCH_IMX8ULP) += \
dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-data-modul-edm-sbc.dtb \
imx8mm-evk.dtb \
imx8mm-icore-mx8mm-ctouch2.dtb \
imx8mm-icore-mx8mm-edimm2.2.dtb \
imx8mm-kontron-bl.dtb \
@@ -1084,25 +1082,11 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-phg.dtb \
imx8mm-phyboard-polis-rdk.dtb \
imx8mm-phygate-tauri-l.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw72xx-0x.dtb \
imx8mm-venice-gw73xx-0x.dtb \
imx8mm-venice-gw7901.dtb \
imx8mm-venice-gw7902.dtb \
imx8mm-venice-gw7903.dtb \
imx8mm-venice-gw7904.dtb \
imx8mm-venice-gw7905-0x.dtb \
imx8mm-verdin-wifi-dev.dtb \
imx8mn-bsh-smm-s2.dtb \
imx8mn-bsh-smm-s2pro.dtb \
imx8mn-ddr4-evk.dtb \
imx8mq-cm.dtb \
imx8mn-evk.dtb \
imx8mn-var-som-symphony.dtb \
imx8mn-venice.dtb \
imx8mn-venice-gw7902.dtb \
imx8mq-evk.dtb \
imx8mm-beacon-kit.dtb \
imx8mn-beacon-kit.dtb \
imx8mq-mnt-reform2.dtb \
@@ -1117,16 +1101,9 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mp-dhcom-pdk2.dtb \
imx8mp-dhcom-pdk3.dtb \
imx8mp-dhcom-pdk3-overlay-rev100.dtbo \
imx8mp-evk.dtb \
imx8mp-icore-mx8mp-edimm2.2.dtb \
imx8mp-msc-sm2s.dtb \
imx8mp-phyboard-pollux-rdk.dtb \
imx8mp-venice.dtb \
imx8mp-venice-gw71xx-2x.dtb \
imx8mp-venice-gw72xx-2x.dtb \
imx8mp-venice-gw73xx-2x.dtb \
imx8mp-venice-gw74xx.dtb \
imx8mp-venice-gw7905-2x.dtb \
imx8mp-verdin-wifi-dev.dtb \
imx8mq-pico-pi.dtb \
imx8mq-kontron-pitx-imx8m.dtb \
@@ -1267,6 +1244,9 @@ dtb-$(CONFIG_TARGET_OMAP4_SDP4430) += \
dtb-$(CONFIG_TARGET_SAMA7G5EK) += \
at91-sama7g5ek.dtb
dtb-$(CONFIG_TARGET_SAMA7G54_CURIOSITY) += \
at91-sama7g54_curiosity.dtb
dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \
at91-sama5d2_ptc_ek.dtb
@@ -1366,7 +1346,9 @@ dtb-$(CONFIG_BCM6878) += \
bcm96878.dtb
dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
dtb-$(CONFIG_ASPEED_AST2600) += \
ast2600-evb.dtb \
ast2600-x4tf.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
@@ -1421,10 +1403,14 @@ dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\
k3-am68-sk-r5-base-board.dtb\
k3-j721s2-common-proc-board.dtb\
k3-j721s2-r5-common-proc-board.dtb
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
k3-am642-r5-evm.dtb \
k3-am642-sk.dtb \
k3-am642-r5-sk.dtb
dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \
k3-j784s4-r5-evm.dtb
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-r5-evm.dtb \
k3-am642-r5-sk.dtb \
k3-am642-phyboard-electra-rdk.dtb \
k3-am642-r5-phycore-som-2gb.dtb
dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
k3-am625-r5-sk.dtb \
@@ -1438,6 +1424,8 @@ dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-sk.dtb \
k3-am62a7-r5-sk.dtb
dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \
mt7623a-unielec-u7623-02-emmc.dtb \
arch/arm/dts/apq8016-sbc-u-boot.dtsi
+20
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@@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2024, Linaro Ltd.
*/
/ {
/* When running as a first-stage bootloader this isn't filled in automatically */
memory@80000000 {
reg = <0 0x80000000 0 0x3da00000>;
};
};
/*
* When running as a first-stage bootloader, we need to re-configure the UART pins
* because SBL de-initialises them. Indicate that the UART pins should be configured
* during all boot stages.
*/
&blsp_uart2_default {
bootph-all;
};
arch/arm/dts/apq8016-sbc.dts
+729
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@@ -0,0 +1,729 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*/
/dts-v1/;
#include "msm8916-pm8916.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
#include <dt-bindings/sound/apq8016-lpass.h>
/ {
model = "Qualcomm Technologies, Inc. APQ 8016 SBC";
compatible = "qcom,apq8016-sbc", "qcom,apq8016";
aliases {
mmc0 = &sdhc_1; /* eMMC */
mmc1 = &sdhc_2; /* SD card */
serial0 = &blsp_uart2;
serial1 = &blsp_uart1;
usid0 = &pm8916_0;
i2c0 = &blsp_i2c2;
i2c1 = &blsp_i2c6;
i2c3 = &blsp_i2c4;
spi0 = &blsp_spi5;
spi1 = &blsp_spi3;
};
chosen {
stdout-path = "serial0";
};
reserved-memory {
ramoops@bff00000 {
compatible = "ramoops";
reg = <0x0 0xbff00000 0x0 0x100000>;
record-size = <0x20000>;
console-size = <0x20000>;
ftrace-size = <0x20000>;
};
};
usb2513 {
compatible = "smsc,usb3503";
reset-gpios = <&pm8916_gpios 3 GPIO_ACTIVE_LOW>;
initial-mode = <1>;
};
usb_id: usb-id {
compatible = "linux,extcon-usb-gpio";
id-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_id_default>;
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7533_out>;
};
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&msm_key_volp_n_default>;
button {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
};
};
leds {
pinctrl-names = "default";
pinctrl-0 = <&tlmm_leds>,
<&pm8916_gpios_leds>,
<&pm8916_mpps_leds>;
compatible = "gpio-leds";
led@1 {
label = "apq8016-sbc:green:user1";
function = LED_FUNCTION_HEARTBEAT;
color = <LED_COLOR_ID_GREEN>;
gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
led@2 {
label = "apq8016-sbc:green:user2";
function = LED_FUNCTION_DISK_ACTIVITY;
color = <LED_COLOR_ID_GREEN>;
gpios = <&tlmm 120 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
default-state = "off";
};
led@3 {
label = "apq8016-sbc:green:user3";
function = LED_FUNCTION_DISK_ACTIVITY;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pm8916_gpios 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc1";
default-state = "off";
};
led@4 {
label = "apq8016-sbc:green:user4";
color = <LED_COLOR_ID_GREEN>;
gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
panic-indicator;
default-state = "off";
};
led@5 {
label = "apq8016-sbc:yellow:wlan";
function = LED_FUNCTION_WLAN;
color = <LED_COLOR_ID_YELLOW>;
gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tx";
default-state = "off";
};
led@6 {
label = "apq8016-sbc:blue:bt";
function = LED_FUNCTION_BLUETOOTH;
color = <LED_COLOR_ID_BLUE>;
gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "bluetooth-power";
default-state = "off";
};
};
};
&blsp_i2c2 {
/* On Low speed expansion: LS-I2C0 */
status = "okay";
};
&blsp_i2c4 {
/* On High speed expansion: HS-I2C2 */
status = "okay";
adv_bridge: bridge@39 {
status = "okay";
compatible = "adi,adv7533";
reg = <0x39>;
interrupt-parent = <&tlmm>;
interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
adi,dsi-lanes = <4>;
clocks = <&rpmcc RPM_SMD_BB_CLK2>;
clock-names = "cec";
pd-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
avdd-supply = <&pm8916_l6>;
a2vdd-supply = <&pm8916_l6>;
dvdd-supply = <&pm8916_l6>;
pvdd-supply = <&pm8916_l6>;
v1p2-supply = <&pm8916_l6>;
v3p3-supply = <&pm8916_l17>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>;
pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>;
#sound-dai-cells = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7533_in: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
port@1 {
reg = <1>;
adv7533_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
&blsp_i2c6 {
/* On Low speed expansion: LS-I2C1 */
status = "okay";
};
&blsp_spi3 {
/* On High speed expansion: HS-SPI1 */
status = "okay";
};
&blsp_spi5 {
/* On Low speed expansion: LS-SPI0 */
status = "okay";
};
&blsp_uart1 {
status = "okay";
label = "LS-UART0";
};
&blsp_uart2 {
status = "okay";
label = "LS-UART1";
};
&camss {
status = "okay";
};
&gpu {
status = "okay";
};
&lpass {
status = "okay";
};
&lpass_codec {
status = "okay";
};
&mba_mem {
status = "okay";
};
&mdss {
status = "okay";
};
&mdss_dsi0_out {
data-lanes = <0 1 2 3>;
remote-endpoint = <&adv7533_in>;
};
&mpss {
status = "okay";
firmware-name = "qcom/apq8016/mba.mbn", "qcom/apq8016/modem.mbn";
};
&mpss_mem {
status = "okay";
reg = <0x0 0x86800000 0x0 0x2b00000>;
};
&pm8916_codec {
status = "okay";
qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
};
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
};
&pm8916_rpm_regulators {
/*
* The 96Boards specification expects a 1.8V power rail on the low-speed
* expansion connector that is able to provide at least 0.18W / 100 mA.
* L15/L16 are connected in parallel to provide 55 mA each. A minimum load
* must be specified to ensure the regulators are not put in LPM where they
* would only provide 5 mA.
*/
pm8916_l15: l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-system-load = <50000>;
regulator-allow-set-load;
regulator-always-on;
};
pm8916_l16: l16 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-system-load = <50000>;
regulator-allow-set-load;
regulator-always-on;
};
pm8916_l17: l17 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&sdhc_1 {
status = "okay";
};
&sdhc_2 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
};
&sound {
status = "okay";
pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default>;
pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep>;
pinctrl-names = "default", "sleep";
model = "DB410c";
audio-routing =
"AMIC2", "MIC BIAS Internal2",
"AMIC3", "MIC BIAS External1";
quaternary-dai-link {
link-name = "ADV7533";
cpu {
sound-dai = <&lpass MI2S_QUATERNARY>;
};
codec {
sound-dai = <&adv_bridge 0>;
};
};
primary-dai-link {
link-name = "WCD";
cpu {
sound-dai = <&lpass MI2S_PRIMARY>;
};
codec {
sound-dai = <&lpass_codec 0>, <&pm8916_codec 0>;
};
};
tertiary-dai-link {
link-name = "WCD-Capture";
cpu {
sound-dai = <&lpass MI2S_TERTIARY>;
};
codec {
sound-dai = <&lpass_codec 1>, <&pm8916_codec 1>;
};
};
};
&usb {
status = "okay";
extcon = <&usb_id>, <&usb_id>;
pinctrl-names = "default", "device";
pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>;
pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>;
};
&usb_hs_phy {
extcon = <&usb_id>;
};
&venus {
status = "okay";
};
&venus_mem {
status = "okay";
};
&wcnss {
status = "okay";
firmware-name = "qcom/apq8016/wcnss.mbn";
};
&wcnss_ctrl {
firmware-name = "qcom/apq8016/WCNSS_qcom_wlan_nv_sbc.bin";
};
&wcnss_iris {
compatible = "qcom,wcn3620";
};
&wcnss_mem {
status = "okay";
};
/* Enable CoreSight */
&cti0 { status = "okay"; };
&cti1 { status = "okay"; };
&cti12 { status = "okay"; };
&cti13 { status = "okay"; };
&cti14 { status = "okay"; };
&cti15 { status = "okay"; };
&debug0 { status = "okay"; };
&debug1 { status = "okay"; };
&debug2 { status = "okay"; };
&debug3 { status = "okay"; };
&etf { status = "okay"; };
&etm0 { status = "okay"; };
&etm1 { status = "okay"; };
&etm2 { status = "okay"; };
&etm3 { status = "okay"; };
&etr { status = "okay"; };
&funnel0 { status = "okay"; };
&funnel1 { status = "okay"; };
&replicator { status = "okay"; };
&stm { status = "okay"; };
&tpiu { status = "okay"; };
/*
* 2mA drive strength is not enough when connecting multiple
* I2C devices with different pull up resistors.
*/
&blsp_i2c2_default {
drive-strength = <16>;
};
&blsp_i2c4_default {
drive-strength = <16>;
};
&blsp_i2c6_default {
drive-strength = <16>;
};
/*
* GPIO name legend: proper name = the GPIO line is used as GPIO
* NC = not connected (pin out but not routed from the chip to
* anything the board)
* "[PER]" = pin is muxed for [peripheral] (not GPIO)
* LSEC = Low Speed External Connector
* HSEC = High Speed External Connector
*
* Line names are taken from the schematic "DragonBoard410c"
* dated monday, august 31, 2015. Page 5 in particular.
*
* For the lines routed to the external connectors the
* lines are named after the 96Boards CE Specification 1.0,
* Appendix "Expansion Connector Signal Description".
*
* When the 96Board naming of a line and the schematic name of
* the same line are in conflict, the 96Board specification
* takes precedence, which means that the external UART on the
* LSEC is named UART0 while the schematic and SoC names this
* UART3. This is only for the informational lines i.e. "[FOO]",
* the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
* ones actually used for GPIO.
*/
&tlmm {
gpio-line-names =
"[UART0_TX]", /* GPIO_0, LSEC pin 5 */
"[UART0_RX]", /* GPIO_1, LSEC pin 7 */
"[UART0_CTS_N]", /* GPIO_2, LSEC pin 3 */
"[UART0_RTS_N]", /* GPIO_3, LSEC pin 9 */
"[UART1_TX]", /* GPIO_4, LSEC pin 11 */
"[UART1_RX]", /* GPIO_5, LSEC pin 13 */
"[I2C0_SDA]", /* GPIO_8, LSEC pin 17 */
"[I2C0_SCL]", /* GPIO_7, LSEC pin 15 */
"[SPI1_DOUT]", /* SPI1_MOSI, HSEC pin 1 */
"[SPI1_DIN]", /* SPI1_MISO, HSEC pin 11 */
"[SPI1_CS]", /* SPI1_CS_N, HSEC pin 7 */
"[SPI1_SCLK]", /* SPI1_CLK, HSEC pin 9 */
"GPIO-B", /* LS_EXP_GPIO_B, LSEC pin 24 */
"GPIO-C", /* LS_EXP_GPIO_C, LSEC pin 25 */
"[I2C3_SDA]", /* HSEC pin 38 */
"[I2C3_SCL]", /* HSEC pin 36 */
"[SPI0_MOSI]", /* LSEC pin 14 */
"[SPI0_MISO]", /* LSEC pin 10 */
"[SPI0_CS_N]", /* LSEC pin 12 */
"[SPI0_CLK]", /* LSEC pin 8 */
"HDMI_HPD_N", /* GPIO 20 */
"USR_LED_1_CTRL",
"[I2C1_SDA]", /* GPIO_22, LSEC pin 21 */
"[I2C1_SCL]", /* GPIO_23, LSEC pin 19 */
"GPIO-G", /* LS_EXP_GPIO_G, LSEC pin 29 */
"GPIO-H", /* LS_EXP_GPIO_H, LSEC pin 30 */
"[CSI0_MCLK]", /* HSEC pin 15 */
"[CSI1_MCLK]", /* HSEC pin 17 */
"GPIO-K", /* LS_EXP_GPIO_K, LSEC pin 33 */
"[I2C2_SDA]", /* HSEC pin 34 */
"[I2C2_SCL]", /* HSEC pin 32 */
"DSI2HDMI_INT_N",
"DSI_SW_SEL_APQ",
"GPIO-L", /* LS_EXP_GPIO_L, LSEC pin 34 */
"GPIO-J", /* LS_EXP_GPIO_J, LSEC pin 32 */
"GPIO-I", /* LS_EXP_GPIO_I, LSEC pin 31 */
"GPIO-A", /* LS_EXP_GPIO_A, LSEC pin 23 */
"FORCED_USB_BOOT",
"SD_CARD_DET_N",
"[WCSS_BT_SSBI]",
"[WCSS_WLAN_DATA_2]", /* GPIO 40 */
"[WCSS_WLAN_DATA_1]",
"[WCSS_WLAN_DATA_0]",
"[WCSS_WLAN_SET]",
"[WCSS_WLAN_CLK]",
"[WCSS_FM_SSBI]",
"[WCSS_FM_SDI]",
"[WCSS_BT_DAT_CTL]",
"[WCSS_BT_DAT_STB]",
"NC",
"NC", /* GPIO 50 */
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC", /* GPIO 60 */
"NC",
"NC",
"[CDC_PDM0_CLK]",
"[CDC_PDM0_SYNC]",
"[CDC_PDM0_TX0]",
"[CDC_PDM0_RX0]",
"[CDC_PDM0_RX1]",
"[CDC_PDM0_RX2]",
"GPIO-D", /* LS_EXP_GPIO_D, LSEC pin 26 */
"NC", /* GPIO 70 */
"NC",
"NC",
"NC",
"NC", /* GPIO 74 */
"NC",
"NC",
"NC",
"NC",
"NC",
"BOOT_CONFIG_0", /* GPIO 80 */
"BOOT_CONFIG_1",
"BOOT_CONFIG_2",
"BOOT_CONFIG_3",
"NC",
"NC",
"BOOT_CONFIG_5",
"NC",
"NC",
"NC",
"NC", /* GPIO 90 */
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC", /* GPIO 100 */
"NC",
"NC",
"NC",
"SSBI_GPS",
"NC",
"NC",
"KEY_VOLP_N",
"NC",
"NC",
"[LS_EXP_MI2S_WS]", /* GPIO 110 */
"NC",
"NC",
"[LS_EXP_MI2S_SCK]",
"[LS_EXP_MI2S_DATA0]",
"GPIO-E", /* LS_EXP_GPIO_E, LSEC pin 27 */
"NC",
"[DSI2HDMI_MI2S_WS]",
"[DSI2HDMI_MI2S_SCK]",
"[DSI2HDMI_MI2S_DATA0]",
"USR_LED_2_CTRL", /* GPIO 120 */
"SB_HS_ID";
sdc2_cd_default: sdc2-cd-default-state {
pins = "gpio38";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
tlmm_leds: tlmm-leds-state {
pins = "gpio21", "gpio120";
function = "gpio";
output-low;
};
usb_id_default: usb-id-default-state {
pins = "gpio121";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
adv7533_int_active: adv533-int-active-state {
pins = "gpio31";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
adv7533_int_suspend: adv7533-int-suspend-state {
pins = "gpio31";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
adv7533_switch_active: adv7533-switch-active-state {
pins = "gpio32";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
adv7533_switch_suspend: adv7533-switch-suspend-state {
pins = "gpio32";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
msm_key_volp_n_default: msm-key-volp-n-default-state {
pins = "gpio107";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
&pm8916_gpios {
gpio-line-names =
"USR_LED_3_CTRL",
"USR_LED_4_CTRL",
"USB_HUB_RESET_N_PM",
"USB_SW_SEL_PM";
usb_hub_reset_pm: usb-hub-reset-pm-state {
pins = "gpio3";
function = PMIC_GPIO_FUNC_NORMAL;
input-disable;
output-high;
};
usb_hub_reset_pm_device: usb-hub-reset-pm-device-state {
pins = "gpio3";
function = PMIC_GPIO_FUNC_NORMAL;
output-low;
};
usb_sw_sel_pm: usb-sw-sel-pm-state {
pins = "gpio4";
function = PMIC_GPIO_FUNC_NORMAL;
power-source = <PM8916_GPIO_VPH>;
input-disable;
output-high;
};
usb_sw_sel_pm_device: usb-sw-sel-pm-device-state {
pins = "gpio4";
function = PMIC_GPIO_FUNC_NORMAL;
power-source = <PM8916_GPIO_VPH>;
input-disable;
output-low;
};
pm8916_gpios_leds: pm8916-gpios-leds-state {
pins = "gpio1", "gpio2";
function = PMIC_GPIO_FUNC_NORMAL;
output-low;
};
};
&pm8916_mpps {
gpio-line-names =
"VDD_PX_BIAS",
"WLAN_LED_CTRL",
"BT_LED_CTRL",
"GPIO-F"; /* LS_EXP_GPIO_F, LSEC pin 28 */
pinctrl-names = "default";
pinctrl-0 = <&ls_exp_gpio_f>;
ls_exp_gpio_f: pm8916-mpp4-state {
pins = "mpp4";
function = "digital";
output-low;
power-source = <PM8916_MPP_L5>; /* 1.8V */
};
pm8916_mpps_leds: pm8916-mpps-state {
pins = "mpp2", "mpp3";
function = "digital";
output-low;
};
};
arch/arm/dts/apq8096-db820c-u-boot.dtsi
+14
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@@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2024, Linaro Ltd.
*/
/ {
/* Ensure that the fdtfile variable is generated properly */
compatible = "qcom,apq8096-db820c", "qcom,apq8096";
};
&sdhc2 {
status = "okay";
clock-frequency = <100000000>;
};
arch/arm/dts/apq8096-db820c.dts
+1137
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arch/arm/dts/ast2600-x4tf.dts
+161
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@@ -0,0 +1,161 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright 2024 ASUS Corp.
/dts-v1/;
#include "ast2600-u-boot.dtsi"
/ {
model = "AST2600 ASUS X4TF";
compatible = "aspeed,ast2600-asus", "aspeed,ast2600";
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
chosen {
stdout-path = &uart5;
};
aliases {
spi0 = &fmc;
ethernet0 = &mac2;
ethernet1 = &mac3;
};
cpus {
cpu@0 {
clock-frequency = <800000000>;
};
cpu@1 {
clock-frequency = <800000000>;
};
};
};
&uart5 {
status = "okay";
};
&sdrammc {
clock-frequency = <400000000>;
};
&wdt1 {
status = "okay";
};
&wdt2 {
status = "okay";
};
&wdt3 {
status = "okay";
};
&mac2 {
status = "okay";
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii3_default>;
};
&mac3 {
status = "okay";
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii4_default>;
};
&fmc {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor", "macronix,mx66l2g45g";
status = "okay";
spi-max-frequency = <25000000>;
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};
flash@1 {
compatible = "spi-flash", "sst,w25q256";
status = "okay";
spi-max-frequency = <25000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};
&hace {
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
};
&i2c7 {
status = "okay";
};
&i2c8 {
status = "okay";
};
&i2c9 {
status = "okay";
};
&i2c10 {
status = "okay";
};
&i2c11 {
status = "okay";
};
&i2c12 {
status = "disabled";
};
&i2c13 {
status = "disabled";
};
&i2c14 {
status = "okay";
};
&i2c15 {
status = "okay";
};
&display_port {
status = "okay";
};
arch/arm/dts/ast2600.dtsi
+20
View File
@@ -2028,6 +2028,26 @@
groups = "SPI2MOSI";
};
pinctrl_thru0_default: thru0_default {
function = "THRU0";
groups = "THRU0";
};
pinctrl_thru1_default: thru1_default {
function = "THRU1";
groups = "THRU1";
};
pinctrl_thru2_default: thru2_default {
function = "THRU2";
groups = "THRU2";
};
pinctrl_thru3_default: thru3_default {
function = "THRU3";
groups = "THRU3";
};
pinctrl_timer3_default: timer3_default {
function = "TIMER3";
groups = "TIMER3";
arch/arm/dts/at91-sama7g54_curiosity-u-boot.dtsi
+59
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@@ -0,0 +1,59 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* at91-sama7g54_curiosity-u-boot.dtsi - Device Tree file for SAMA7G5 SoC u-boot properties.
*
* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
*
* Author: Mihai Sain <mihai.sain@microchip.com>
*
*/
/ {
chosen {
bootph-all;
};
};
&main_rc {
bootph-all;
};
&main_xtal {
bootph-all;
};
&pioA {
bootph-all;
};
&pinctrl_flx3_default {
bootph-all;
};
&pinctrl_sdmmc1_default {
bootph-all;
};
&pit64b0 {
bootph-all;
};
&pmc {
bootph-all;
};
&sdmmc1 {
bootph-all;
};
&slow_rc_osc {
bootph-all;
};
&slow_xtal {
bootph-all;
};
&uart3 {
bootph-all;
};
arch/arm/dts/at91-sama7g54_curiosity.dts
+242
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@@ -0,0 +1,242 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* at91-sama7g54_curiosity.dts - Device Tree file for SAMA7G54 CURIOSITY board
*
* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
*
* Author: Mihai Sain <mihai.sain@microchip.com>
*
*/
/dts-v1/;
#include "sama7g5-pinfunc.h"
#include "sama7g5.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/mfd/atmel-flexcom.h>
#include <dt-bindings/pinctrl/at91.h>
/ {
model = "Microchip SAMA7G54 Curiosity";
compatible = "microchip,sama7g54-curiosity", "microchip,sama7g5", "microchip,sama7";
aliases {
serial0 = &uart3;
i2c0 = &i2c10;
};
chosen {
bootargs = "console=ttyS0,115200 root=/dev/mmcblk1p2 rw rootwait";
stdout-path = "serial0:115200n8";
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <24000000>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led_gpio_default>;
led-red {
label = "red";
gpios = <&pioA PIN_PD13 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-green {
label = "green";
gpios = <&pioA PIN_PD14 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-blue {
label = "blue";
gpios = <&pioA PIN_PB15 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
memory {
device_type = "memory";
reg = <0x60000000 0x10000000>; // 256 MiB DDR3L-1066 16-bit
};
};
&ebi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand_default>;
status = "okay";
nand_controller: nand-controller {
status = "okay";
nand@3 {
reg = <0x3 0x0 0x800000>;
atmel,rb = <0>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
};
};
};
&flx3 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
status = "okay";
uart3: serial@200 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx3_default>;
status = "okay";
};
};
&flx10 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
i2c10: i2c@600 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx10_default>;
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "okay";
adc@1f {
compatible = "microchip,pac1934";
reg = <0x1f>;
};
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
size = <256>;
};
pmic@5b {
compatible = "microchip,mcp16502";
reg = <0x5b>;
};
};
};
&pioA {
pinctrl_flx3_default: flx3-default {
pinmux = <PIN_PD16__FLEXCOM3_IO0>,
<PIN_PD17__FLEXCOM3_IO1>;
bias-pull-up;
};
pinctrl_flx10_default: flx10-default {
pinmux = <PIN_PC30__FLEXCOM10_IO0>,
<PIN_PC31__FLEXCOM10_IO1>;
bias-pull-up;
};
pinctrl_led_gpio_default: led-gpio-default {
pinmux = <PIN_PD13__GPIO>,
<PIN_PD14__GPIO>,
<PIN_PB15__GPIO>;
bias-pull-up;
};
pinctrl_nand_default: nand-default {
pinmux = <PIN_PD9__D0>,
<PIN_PD10__D1>,
<PIN_PD11__D2>,
<PIN_PC21__D3>,
<PIN_PC22__D4>,
<PIN_PC23__D5>,
<PIN_PC24__D6>,
<PIN_PD2__D7>,
<PIN_PD3__NANDRDY>,
<PIN_PD4__NCS3_NANDCS>,
<PIN_PD5__NWE_NWR0_NANDWE>,
<PIN_PD6__NRD_NANDOE>,
<PIN_PD7__A21_NANDALE>,
<PIN_PD8__A22_NANDCLE>;
bias-disable;
slew-rate = <0>;
};
pinctrl_qspi1_default: qspi1-default {
pinmux = <PIN_PB22__QSPI1_IO3>,
<PIN_PB23__QSPI1_IO2>,
<PIN_PB24__QSPI1_IO1>,
<PIN_PB25__QSPI1_IO0>,
<PIN_PB26__QSPI1_CS>,
<PIN_PB27__QSPI1_SCK>;
bias-pull-up;
slew-rate = <0>;
};
pinctrl_sdmmc0_default: sdmmc0-default {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA1__SDMMC0_CMD>,
<PIN_PA2__SDMMC0_RSTN>,
<PIN_PA3__SDMMC0_DAT0>,
<PIN_PA4__SDMMC0_DAT1>,
<PIN_PA5__SDMMC0_DAT2>,
<PIN_PA6__SDMMC0_DAT3>;
bias-pull-up;
slew-rate = <0>;
};
pinctrl_sdmmc1_default: sdmmc1-default {
pinmux = <PIN_PB29__SDMMC1_CMD>,
<PIN_PB30__SDMMC1_CK>,
<PIN_PB31__SDMMC1_DAT0>,
<PIN_PC0__SDMMC1_DAT1>,
<PIN_PC1__SDMMC1_DAT2>,
<PIN_PC2__SDMMC1_DAT3>,
<PIN_PC4__SDMMC1_CD>;
bias-pull-up;
slew-rate = <0>;
};
};
&qspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi1_default>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <100000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
m25p,fast-read;
};
};
// M.2 slot for wireless card
&sdmmc0 {
bus-width = <4>;
cd-gpios = <&pioA 31 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <50000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_default>;
status = "okay";
};
// micro SD socket
&sdmmc1 {
bus-width = <4>;
disable-wp;
max-frequency = <50000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc1_default>;
status = "okay";
};
arch/arm/dts/dragonboard410c-uboot.dtsi
-44
View File
@@ -1,44 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot addition to handle Dragonboard 410c pins
*
* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
*/
/ {
smem {
bootph-all;
};
soc {
bootph-all;
pinctrl@1000000 {
bootph-all;
uart {
bootph-all;
};
};
qcom,gcc@1800000 {
bootph-all;
};
serial@78b0000 {
bootph-all;
};
};
};
&pm8916_gpios {
usb_hub_reset_pm {
gpios = <&pm8916_gpios 2 0>;
};
usb_sw_sel_pm {
gpios = <&pm8916_gpios 3 0>;
};
};
arch/arm/dts/dragonboard410c.dts
-209
View File
@@ -1,209 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Qualcomm APQ8016 based Dragonboard 410C board device tree source
*
* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
*/
/dts-v1/;
#include "skeleton64.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Qualcomm Technologies, Inc. Dragonboard 410c";
compatible = "qcom,dragonboard", "qcom,apq8016-sbc";
qcom,msm-id = <0xce 0x0 0xf8 0x0 0xf9 0x0 0xfa 0x0 0xf7 0x0>;
qcom,board-id = <0x10018 0x0>;
#address-cells = <0x2>;
#size-cells = <0x2>;
aliases {
usb0 = "/soc/ehci@78d9000";
};
memory {
device_type = "memory";
reg = <0 0x80000000 0 0x3da00000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
smem_mem: smem_region@86300000 {
reg = <0x0 0x86300000 0x0 0x100000>;
no-map;
};
};
chosen {
stdout-path = "/soc/serial@78b0000";
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
};
soc {
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges = <0x0 0x0 0x0 0xffffffff>;
compatible = "simple-bus";
rpm_msg_ram: memory@60000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x60000 0x8000>;
};
soc_gpios: pinctrl@1000000 {
compatible = "qcom,msm8916-pinctrl";
reg = <0x1000000 0x400000>;
gpio-controller;
gpio-count = <122>;
gpio-bank-name="soc";
#gpio-cells = <2>;
blsp1_uart: uart {
function = "blsp1_uart";
pins = "GPIO_4", "GPIO_5";
drive-strength = <8>;
bias-disable;
};
};
clkc: qcom,gcc@1800000 {
compatible = "qcom,gcc-apq8016";
reg = <0x1800000 0x80000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
serial@78b0000 {
compatible = "qcom,msm-uartdm-v1.4";
reg = <0x78b0000 0x200>;
clock = <&clkc 4>;
pinctrl-names = "uart";
pinctrl-0 = <&blsp1_uart>;
};
ehci@78d9000 {
compatible = "qcom,ehci-host";
reg = <0x78d9000 0x400>;
phys = <&ehci_phy>;
};
ehci_phy: ehci_phy@78d9000 {
compatible = "qcom,apq8016-usbphy";
reg = <0x78d9000 0x400>;
#phy-cells = <0>;
};
sdhci@07824000 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x11c 0x7824000 0x800>;
bus-width = <0x8>;
index = <0x0>;
non-removable;
clock = <&clkc 0>;
clock-frequency = <100000000>;
};
sdhci@07864000 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7864900 0x11c 0x7864000 0x800>;
index = <0x1>;
bus-width = <0x4>;
clock = <&clkc 1>;
clock-frequency = <200000000>;
cd-gpios = <&soc_gpios 38 GPIO_ACTIVE_LOW>;
};
wcnss {
bt {
compatible="qcom,wcnss-bt";
};
wifi {
compatible="qcom,wcnss-wlan";
};
};
spmi_bus: spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0200f000 0x001000>,
<0x02400000 0x400000>,
<0x02c00000 0x400000>,
<0x03800000 0x200000>,
<0x0200a000 0x002100>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
#address-cells = <0x1>;
#size-cells = <0x1>;
pmic0: pm8916@0 {
compatible = "qcom,spmi-pmic";
reg = <0x0 0x1>;
#address-cells = <0x1>;
#size-cells = <0x1>;
pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x800 0x100>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
debounce = <15625>;
bias-pull-up;
};
pm8916_resin: resin {
compatible = "qcom,pm8941-resin";
debounce = <15625>;
bias-pull-up;
};
};
pm8916_gpios: pm8916_gpios@c000 {
compatible = "qcom,pm8916-gpio";
reg = <0xc000 0x400>;
gpio-controller;
gpio-ranges = <&pm8916_gpios 0 0 4>;
#gpio-cells = <2>;
};
};
pmic1: pm8916@1 {
compatible = "qcom,spmi-pmic";
reg = <0x1 0x1>;
};
};
};
leds {
compatible = "gpio-leds";
user1 {
label = "green:user1";
gpios = <&soc_gpios 21 0>;
};
user2 {
label = "green:user2";
gpios = <&soc_gpios 120 0>;
};
user3 {
label = "green:user3";
gpios = <&pm8916_gpios 0 0>;
};
user4 {
label = "green:user4";
gpios = <&pm8916_gpios 1 0>;
};
};
};
#include "dragonboard410c-uboot.dtsi"
arch/arm/dts/dragonboard820c-uboot.dtsi
-32
View File
@@ -1,32 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot addition to handle Dragonboard 820c pins
*
* (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
*/
/ {
smem {
bootph-all;
};
soc {
bootph-all;
pinctrl@1010000 {
bootph-all;
uart {
bootph-all;
};
};
clock-controller@300000 {
bootph-all;
};
serial@75b0000 {
bootph-all;
};
};
};
arch/arm/dts/dragonboard820c.dts
-151
View File
@@ -1,151 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Qualcomm APQ8096 based Dragonboard 820C board device tree source
*
* (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
*/
/dts-v1/;
#include "skeleton64.dtsi"
/ {
model = "Qualcomm Technologies, Inc. DB820c";
compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc";
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &blsp2_uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0 0x80000000 0 0xc0000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
smem_mem: smem_region@86300000 {
reg = <0x0 0x86300000 0x0 0x200000>;
no-map;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
gcc: clock-controller@300000 {
compatible = "qcom,gcc-msm8996";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0x300000 0x90000>;
};
pinctrl: pinctrl@1010000 {
compatible = "qcom,msm8996-pinctrl";
reg = <0x1010000 0x400000>;
blsp8_uart: uart {
function = "blsp_uart8";
pins = "GPIO_4", "GPIO_5";
drive-strength = <8>;
bias-disable;
};
};
blsp2_uart2: serial@75b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x75b0000 0x1000>;
clock = <&gcc 4>;
pinctrl-names = "uart";
pinctrl-0 = <&blsp8_uart>;
};
sdhc2: sdhci@74a4900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
index = <0x0>;
bus-width = <4>;
clock = <&gcc 0>;
clock-frequency = <200000000>;
};
spmi_bus: spmi@400f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0400f000 0x1000>,
<0x04400000 0x800000>,
<0x04c00000 0x800000>,
<0x05800000 0x200000>,
<0x0400a000 0x002100>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
#address-cells = <0x1>;
#size-cells = <0x1>;
pmic0: pm8994@0 {
compatible = "qcom,spmi-pmic";
reg = <0x0 0x1>;
#address-cells = <0x1>;
#size-cells = <0x1>;
pm8994_pon: pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x800 0x100>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
debounce = <15625>;
bias-pull-up;
};
pm8994_resin: resin {
compatible = "qcom,pm8941-resin";
debounce = <15625>;
bias-pull-up;
};
};
pm8994_gpios: pm8994_gpios@c000 {
compatible = "qcom,pm8994-gpio";
reg = <0xc000 0x400>;
gpio-controller;
gpio-ranges = <&pm8994_gpios 0 0 22>;
#gpio-cells = <2>;
};
};
pmic1: pm8994@1 {
compatible = "qcom,spmi-pmic";
reg = <0x1 0x1>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
};
};
};
#include "dragonboard820c-uboot.dtsi"
arch/arm/dts/dragonboard845c-uboot.dtsi
-26
View File
@@ -1,26 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot addition to handle Qualcomm Robotics RB3 Development Platform
* (dragonboard845c) pins
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
/
{
soc {
bootph-all;
serial@a84000 {
bootph-all;
};
clock-controller@100000 {
bootph-all;
};
pinctrl@3400000 {
bootph-all;
};
};
};
arch/arm/dts/dragonboard845c.dts
-48
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@@ -1,48 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Qualcomm Robotics RB3 Development (dragonboard845c) board device
* tree source
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
/dts-v1/;
#include "sdm845.dtsi"
/ {
model = "Thundercomm Dragonboard 845c";
compatible = "thundercomm,db845c", "qcom,sdm845";
#address-cells = <2>;
#size-cells = <2>;
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &uart9;
};
memory {
device_type = "memory";
reg = <0 0x80000000 0 0xfdfa0000>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
soc: soc {
serial@a84000 {
status = "okay";
};
};
};
&pm8998_resin {
status = "okay";
};
#include "dragonboard845c-uboot.dtsi"
arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi
+4
View File
@@ -51,3 +51,7 @@
};
};
};
&wdog1 {
bootph-pre-ram;
};
arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi
+7
View File
@@ -25,6 +25,13 @@
gpios = <9 GPIO_ACTIVE_HIGH>;
line-name = "dio1";
};
tpm_rst {
gpio-hog;
output-high;
gpios = <11 GPIO_ACTIVE_HIGH>;
line-name = "tpm_rst#";
};
};
&gpio4 {
arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi
+14
View File
@@ -43,6 +43,20 @@
};
&gpio4 {
dig1ctl {
gpio-hog;
output-low;
gpios = <4 GPIO_ACTIVE_HIGH>;
line-name = "dig1_ctl";
};
dig2ctl {
gpio-hog;
output-low;
gpios = <5 GPIO_ACTIVE_HIGH>;
line-name = "dig2_ctl";
};
uart3_rs232 {
gpio-hog;
output-high;
arch/arm/dts/imx8mm-venice.dts
-169
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Gateworks Corporation
*/
/dts-v1/;
#include "imx8mm.dtsi"
/ {
model = "Gateworks Venice i.MX8MM board";
compatible = "gw,imx8mm-venice", "fsl,imx8mm";
chosen {
stdout-path = &uart2;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
};
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
eeprom@52 {
compatible = "atmel,24c32";
reg = <0x52>;
pagesize = <32>;
};
};
/* console */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
/* eMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c1_gpio: i2c1grp-gpio-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};
arch/arm/dts/imx8mn-venice.dts
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 Gateworks Corporation
*/
/dts-v1/;
#include "imx8mn.dtsi"
/ {
model = "Gateworks Venice i.MX8MM board";
compatible = "gw,imx8mn-venice", "fsl,imx8mn";
chosen {
stdout-path = &uart2;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
};
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
eeprom@52 {
compatible = "atmel,24c32";
reg = <0x52>;
pagesize = <32>;
};
};
/* console */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
/* eMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c1_gpio: i2c1grp-gpio-grp {
fsl,pins = <
MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};
arch/arm/dts/imx8mp-evk.dts
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
*/
/dts-v1/;
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mp.dtsi"
/ {
model = "NXP i.MX8MPlus EVK board";
compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
chosen {
stdout-path = &uart2;
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
status {
label = "yellow:status";
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0xc0000000>,
<0x1 0x00000000 0 0xc0000000>;
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_can1_stby: regulator-can1-stby {
compatible = "regulator-fixed";
regulator-name = "can1-stby";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1_reg>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_can2_stby: regulator-can2-stby {
compatible = "regulator-fixed";
regulator-name = "can2-stby";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2_reg>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_pcie0: regulator-pcie {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0_reg>;
regulator-name = "MPCIE_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&A53_0 {
cpu-supply = <&reg_arm>;
};
&A53_1 {
cpu-supply = <&reg_arm>;
};
&A53_2 {
cpu-supply = <&reg_arm>;
};
&A53_3 {
cpu-supply = <&reg_arm>;
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
snps,force_thresh_dma_mode;
snps,mtl-tx-config = <&mtl_tx_setup>;
snps,mtl-rx-config = <&mtl_rx_setup>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
eee-broken-1000t;
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
realtek,clkout-disable;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <5>;
snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,priority = <0x2>;
};
queue2 {
snps,dcb-algorithm;
snps,priority = <0x4>;
};
queue3 {
snps,dcb-algorithm;
snps,priority = <0x8>;
};
queue4 {
snps,dcb-algorithm;
snps,priority = <0xf0>;
};
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <5>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,priority = <0x1>;
snps,map-to-dma-channel = <0>;
};
queue1 {
snps,dcb-algorithm;
snps,priority = <0x2>;
snps,map-to-dma-channel = <1>;
};
queue2 {
snps,dcb-algorithm;
snps,priority = <0x4>;
snps,map-to-dma-channel = <2>;
};
queue3 {
snps,dcb-algorithm;
snps,priority = <0x8>;
snps,map-to-dma-channel = <3>;
};
queue4 {
snps,dcb-algorithm;
snps,priority = <0xf0>;
snps,map-to-dma-channel = <4>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
eee-broken-1000t;
reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
realtek,clkout-disable;
};
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_can1_stby>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_can2_stby>;
status = "disabled";/* can2 pin conflict with pdm */
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
regulators {
BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
reg_arm: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <1025000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
regulator-always-on;
};
BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1950000>;
regulator-boot-on;
regulator-always-on;
};
BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <1045000>;
regulator-max-microvolt = <1155000>;
regulator-boot-on;
regulator-always-on;
};
LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1950000>;
regulator-boot-on;
regulator-always-on;
};
LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <1710000>;
regulator-max-microvolt = <1890000>;
regulator-boot-on;
regulator-always-on;
};
LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
pca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca6416_int>;
interrupt-parent = <&gpio1>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
gpio-line-names = "EXT_PWREN1",
"EXT_PWREN2",
"CAN1/I2C5_SEL",
"PDM/CAN2_SEL",
"FAN_EN",
"PWR_MEAS_IO1",
"PWR_MEAS_IO2",
"EXP_P0_7",
"EXP_P1_0",
"EXP_P1_1",
"EXP_P1_2",
"EXP_P1_3",
"EXP_P1_4",
"EXP_P1_5",
"EXP_P1_6",
"EXP_P1_7";
};
};
/* I2C on expansion connector J22. */
&i2c5 {
clock-frequency = <100000>; /* Lower clock speed for external bus. */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c5>;
status = "disabled"; /* can1 pins conflict with i2c5 */
/* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions:
* LOW: CAN1 (default, pull-down)
* HIGH: I2C5
* You need to set it to high to enable I2C5 (for example, add gpio-hog
* in pca6416 node).
*/
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
clocks = <&pcie0_refclk>;
clock-names = "ref";
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_PCIE_ROOT>,
<&clk IMX8MP_CLK_HSIO_AXI>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
assigned-clock-rates = <10000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
vpcie-supply = <&reg_pcie0>;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&uart2 {
/* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb_dwc3_1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_vbus>;
dr_mode = "host";
status = "okay";
};
&usdhc2 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
&usdhc3 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
>;
};
pinctrl_flexcan1_reg: flexcan1reggrp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */
>;
};
pinctrl_flexcan2_reg: flexcan2reggrp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c5: i2c5grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2
MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */
MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41
>;
};
pinctrl_pcie0_reg: pcie0reggrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
>;
};
pinctrl_pca6416_int: pca6416_int_grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
>;
};
pinctrl_usb1_vbus: usb1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
>;
};
};
arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi
+9
View File
@@ -4,6 +4,15 @@
*/
#include "imx8mp-venice-gw702x-u-boot.dtsi"
&gpio1 {
tpm_rst {
gpio-hog;
output-high;
gpios = <11 GPIO_ACTIVE_HIGH>;
line-name = "tpm_rst#";
};
};
&gpio4 {
dio_1 {
gpio-hog;
arch/arm/dts/imx8mp-venice.dts
-183
View File
@@ -1,183 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Gateworks Corporation
*/
/dts-v1/;
#include "imx8mp.dtsi"
/ {
model = "Gateworks Venice i.MX8MP board";
compatible = "gateworks,imx8mp-venice", "fsl,imx8mp";
chosen {
stdout-path = &uart2;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
};
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
eeprom@52 {
compatible = "atmel,24c32";
reg = <0x52>;
pagesize = <32>;
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
/* console */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
/* eMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c1_gpio: i2c1grp-gpio-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
>;
};
};
arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
+15
View File
@@ -121,6 +121,21 @@
bootph-some-ram;
};
/*
* Remove once USB support is added to imx93-phyboard-segin.dts upstream.
*/
&usbotg1 {
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
status = "okay";
};
&usdhc1 {
bootph-pre-ram;
bootph-some-ram;
arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
+2 -2
View File
@@ -105,8 +105,8 @@
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
load = <CONFIG_K3_OPTEE_LOAD_ADDR>;
entry = <CONFIG_K3_OPTEE_LOAD_ADDR>;
tee-os {
filename = "tee-raw.bin";
};
arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi
+2800
View File
File diff suppressed because it is too large Load Diff
arch/arm/dts/k3-am62p-sk-binman.dtsi
+173
View File
@@ -0,0 +1,173 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-binman.dtsi"
#if IS_ENABLED(CONFIG_TARGET_AM62P5_R5_EVM)
&binman {
tiboot3-am62px-hs-fs-evm.bin {
filename = "tiboot3-am62px-hs-fs-evm.bin";
symlink = "tiboot3.bin";
ti-secure-rom {
content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
<&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
combined;
dm-data;
sysfw-inner-cert;
keyfile = "custMpk.pem";
sw-rev = <1>;
content-sbl = <&u_boot_spl_fs>;
content-sysfw = <&ti_fs_enc_fs>;
content-sysfw-data = <&combined_tifs_cfg_fs>;
content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
content-dm-data = <&combined_dm_cfg_fs>;
load = <0x43c00000>;
load-sysfw = <0x40000>;
load-sysfw-data = <0x67000>;
load-dm-data = <0x43c4a800>;
};
u_boot_spl_fs: u-boot-spl {
no-expanded;
};
ti_fs_enc_fs: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-am62px-hs-fs-enc.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg_fs: combined-tifs-cfg.bin {
filename = "combined-tifs-cfg.bin";
type = "blob-ext";
};
sysfw_inner_cert_fs: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-am62px-hs-fs-cert.bin";
type = "blob-ext";
optional;
};
combined_dm_cfg_fs: combined-dm-cfg.bin {
filename = "combined-dm-cfg.bin";
type = "blob-ext";
};
};
};
#endif /* CONFIG_TARGET_AM62P5_R5_EVM */
#if IS_ENABLED(CONFIG_TARGET_AM62P5_A53_EVM)
#define SPL_AM62PX_SK_DTB "spl/dts/ti/k3-am62p5-sk.dtb"
#define AM62PX_SK_DTB "u-boot.dtb"
&binman {
ti-dm {
filename = "ti-dm.bin";
blob-ext {
filename = "ti-dm/am62pxx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
};
};
ti-spl {
insert-template = <&ti_spl_template>;
fit {
images {
dm {
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
};
dm: ti-dm {
filename = "ti-dm.bin";
};
};
fdt-0 {
description = "k3-am62p5-sk";
type = "flat_dt";
arch = "arm";
compression = "none";
ti-secure {
content = <&spl_am62p5_sk_dtb>;
keyfile = "custMpk.pem";
};
spl_am62p5_sk_dtb: blob-ext {
filename = SPL_AM62PX_SK_DTB;
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am62px-sk";
firmware = "atf";
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
};
};
};
};
&binman {
u-boot {
insert-template = <&u_boot_template>;
fit {
images {
uboot {
description = "U-Boot for AM62P5 Boards";
};
fdt-0 {
description = "k3-am62px-sk";
type = "flat_dt";
arch = "arm";
compression = "none";
ti-secure {
content = <&am62px_sk_dtb>;
keyfile = "custMpk.pem";
};
am62px_sk_dtb: blob-ext {
filename = AM62PX_SK_DTB;
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am62px-sk";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
#endif /* CONFIG_TARGET_AM62P5_A53_EVM */
arch/arm/dts/k3-am62p5-r5-sk.dts
+101
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@@ -0,0 +1,101 @@
// SPDX-License-Identifier: GPL-2.0
/*
* AM62P5 SK dts file for R5 SPL
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-am62p5-sk.dts"
#include "k3-am62p5-sk-u-boot.dtsi"
#include "k3-am62p-ddr-lp4-50-1600.dtsi"
#include "k3-am62a-ddr.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
serial2 = &main_uart0;
serial3 = &main_uart1;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-all;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 20>,
<&secure_proxy_main 21>;
bootph-all;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&cbass_main {
sa3_secproxy: secproxy@44880000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg = <0x00 0x44880000 0x00 0x20000>,
<0x00 0x44860000 0x00 0x20000>,
<0x00 0x43600000 0x00 0x10000>;
reg-names = "rt", "scfg", "target_data";
bootph-all;
};
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&sa3_secproxy 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-all;
};
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
status = "okay";
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
status = "okay";
};
&main_pktdma {
ti,sci = <&dm_tifs>;
};
&main_bcdma {
ti,sci = <&dm_tifs>;
};
&ospi0 {
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x00 0x60000000 0x00 0x08000000>;
};
arch/arm/dts/k3-am62p5-sk-u-boot.dtsi
+23
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@@ -0,0 +1,23 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Common AM62Px EVM dts file for SPLs
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-am62p-sk-binman.dtsi"
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &main_timer0;
};
};
&dmsc {
bootph-pre-ram;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-pre-ram;
};
};
arch/arm/dts/k3-am64-phycore-som-ddr4-2gb.dtsi
+2189
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File diff suppressed because it is too large Load Diff
arch/arm/dts/k3-am64-phycore-som.dtsi
+320
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@@ -0,0 +1,320 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
* Author: Matt McKee <mmckee@phytec.com>
*
* Copyright (C) 2022 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*
* Product homepage:
* https://www.phytec.com/product/phycore-am64x
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
/ {
model = "PHYTEC phyCORE-AM64x";
compatible = "phytec,am64-phycore-som", "ti,am642";
aliases {
ethernet0 = &cpsw_port1;
mmc0 = &sdhci0;
rtc0 = &i2c_som_rtc;
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&leds_pins_default>;
led-0 {
color = <LED_COLOR_ID_GREEN>;
gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
function = LED_FUNCTION_HEARTBEAT;
};
};
vcc_5v0_som: regulator-vcc-5v0-som {
/* VIN / VCC_5V0_SOM */
compatible = "regulator-fixed";
regulator-name = "VCC_5V0_SOM";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
};
&main_pmx0 {
cpsw_mdio_pins_default: cpsw-mdio-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
AM64X_IOPAD(0x0100, PIN_OUTPUT, 7) /* (V7) PRG1_PRU0_GPO18.GPIO0_63 */
>;
};
cpsw_rgmii1_pins_default: cpsw-rgmii1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
AM64X_IOPAD(0x0154, PIN_INPUT, 7) /* (V12) PRG1_PRU1_GPO19.GPIO0_84 */
>;
};
eeprom_wp_pins_default: eeprom-wp-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0208, PIN_OUTPUT, 7) /* (D12) SPI0_CS0.GPIO1_42 */
>;
};
leds_pins_default: leds-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0030, PIN_OUTPUT, 7) /* (L18) OSPI0_CSn1.GPIO0_12 */
>;
};
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* (A18) I2C0_SCL */
AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* (B18) I2C0_SDA */
>;
};
ospi0_pins_default: ospi0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
>;
};
rtc_pins_default: rtc-defaults-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* (C19) EXTINTn.GPIO1_70 */
>;
};
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&cpsw_rgmii1_pins_default>;
};
&cpsw3g_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cpsw_mdio_pins_default>;
cpsw3g_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&main_gpio0>;
interrupts = <84 IRQ_TYPE_EDGE_FALLING>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
reset-gpios = <&main_gpio0 63 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
};
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy1>;
};
&cpsw_port2 {
status = "disabled";
};
&mailbox0_cluster2 {
status = "okay";
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster4 {
status = "okay";
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&main_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@50 {
compatible = "atmel,24c32";
pinctrl-names = "default";
pinctrl-0 = <&eeprom_wp_pins_default>;
pagesize = <32>;
reg = <0x50>;
};
i2c_som_rtc: rtc@52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
pinctrl-names = "default";
pinctrl-0 = <&rtc_pins_default>;
interrupt-parent = <&main_gpio1>;
interrupts = <70 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
};
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <0>;
};
};
&sdhci0 {
status = "okay";
bus-width = <8>;
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
keep-power-in-suspend;
};
arch/arm/dts/k3-am642-evm-u-boot.dtsi
+16 -110
View File
@@ -9,97 +9,27 @@
chosen {
tick-timer = &main_timer0;
};
memory@80000000 {
bootph-all;
};
};
&cbass_main {
bootph-all;
};
&main_timer0 {
bootph-all;
clock-frequency = <200000000>;
};
&main_conf {
bootph-all;
chipid@14 {
bootph-all;
};
};
&main_pmx0 {
bootph-all;
};
&main_i2c0_pins_default {
bootph-all;
};
&main_i2c0 {
bootph-all;
};
&main_uart0_pins_default {
bootph-all;
};
&main_uart0 {
bootph-all;
};
&main_usb0_pins_default {
bootph-all;
};
&usb0 {
dr_mode="peripheral";
bootph-all;
};
&usbss0 {
bootph-all;
};
&main_mmc1_pins_default {
bootph-all;
};
&main_usb0_pins_default {
bootph-all;
};
&dmss {
bootph-all;
};
&secure_proxy_main {
bootph-all;
};
&dmsc {
bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-all;
};
};
&k3_pds {
bootph-all;
};
&k3_clks {
bootph-all;
};
&k3_reset {
bootph-all;
};
&sdhci0 {
bootph-all;
};
@@ -108,10 +38,6 @@
bootph-all;
};
&sdhci1 {
bootph-all;
};
&inta_main_dmss {
bootph-all;
};
@@ -143,42 +69,22 @@
bootph-all;
};
&mdio1_pins_default {
bootph-all;
};
&cpsw3g_mdio {
bootph-all;
};
&cpsw3g_phy0 {
bootph-all;
};
&rgmii1_pins_default {
bootph-all;
};
&rgmii2_pins_default {
bootph-all;
};
&cpsw3g {
bootph-all;
ethernet-ports {
bootph-all;
};
};
&phy_gmii_sel {
bootph-all;
};
&cpsw_port1 {
bootph-all;
};
&cpsw_port2 {
status = "disabled";
};
&ospi0_pins_default {
bootph-all;
};
&fss {
bootph-all;
};
&ospi0 {
bootph-all;
flash@0 {
bootph-all;
};
};
arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi
+147
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@@ -0,0 +1,147 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
* Author: Matt McKee <mmckee@phytec.com>
*
* Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*
* Product homepage:
* https://www.phytec.com/product/phycore-am64x
*/
#include "k3-am642-phycore-som-binman.dtsi"
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &main_timer0;
};
memory@80000000 {
bootph-all;
};
};
&cbass_main {
bootph-all;
};
&dmsc {
bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-all;
};
};
&dmss {
bootph-all;
};
&k3_clks {
bootph-all;
};
&k3_pds {
bootph-all;
};
&k3_reset {
bootph-all;
};
&main_bcdma {
bootph-all;
reg = <0x00 0x485c0100 0x00 0x100>,
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
<0x00 0x4bc00000 0x00 0x100000>,
<0x00 0x48600000 0x00 0x8000>,
<0x00 0x484a4000 0x00 0x2000>,
<0x00 0x484c2000 0x00 0x2000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
"cfg", "tchan", "rchan";
};
&main_conf {
bootph-all;
chipid@14 {
bootph-all;
};
};
&main_gpio0 {
bootph-all;
};
&main_mmc1_pins_default {
bootph-all;
};
&main_pktdma {
bootph-all;
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
<0x00 0x4b800000 0x00 0x400000>,
<0x00 0x485e0000 0x00 0x20000>,
<0x00 0x484a0000 0x00 0x4000>,
<0x00 0x484c0000 0x00 0x2000>,
<0x00 0x48430000 0x00 0x4000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg",
"tchan", "rchan", "rflow";
};
&main_pmx0 {
bootph-all;
};
&main_timer0 {
bootph-all;
clock-frequency = <200000000>;
};
&main_uart0 {
bootph-all;
};
&main_uart0_pins_default {
bootph-all;
};
&main_usb0_pins_default {
bootph-all;
};
&ospi0 {
bootph-all;
flash@0 {
bootph-all;
};
};
&ospi0_pins_default {
bootph-all;
};
&sdhci0 {
bootph-all;
};
&sdhci1 {
bootph-all;
};
&secure_proxy_main {
bootph-all;
};
&usbss0 {
bootph-all;
};
&usb0 {
bootph-all;
};
arch/arm/dts/k3-am642-phyboard-electra-rdk.dts
+302
View File
@@ -0,0 +1,302 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
* Author: Matt McKee <mmckee@phytec.com>
*
* Copyright (C) 2022 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*
* Product homepage:
* https://www.phytec.com/product/phyboard-am64x
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/leds/leds-pca9532.h>
#include <dt-bindings/phy/phy.h>
#include "k3-am642.dtsi"
#include "k3-am64-phycore-som.dtsi"
#include "k3-serdes.h"
/ {
compatible = "phytec,am642-phyboard-electra-rdk",
"phytec,am64-phycore-som", "ti,am642";
model = "PHYTEC phyBOARD-Electra-AM64x RDK";
aliases {
mmc1 = &sdhci1;
serial2 = &main_uart0;
serial3 = &main_uart1;
};
chosen {
stdout-path = &main_uart0;
};
can_tc1: can-phy0 {
compatible = "ti,tcan1042";
pinctrl-names = "default";
pinctrl-0 = <&can_tc1_pins_default>;
#phy-cells = <0>;
max-bitrate = <5000000>;
standby-gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>;
};
can_tc2: can-phy1 {
compatible = "ti,tcan1042";
pinctrl-names = "default";
pinctrl-0 = <&can_tc2_pins_default>;
#phy-cells = <0>;
max-bitrate = <5000000>;
standby-gpios = <&main_gpio0 35 GPIO_ACTIVE_HIGH>;
};
keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pins_default>;
key-home {
label = "home";
linux,code = <KEY_HOME>;
gpios = <&main_gpio0 17 GPIO_ACTIVE_HIGH>;
};
key-menu {
label = "menu";
linux,code = <KEY_MENU>;
gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>;
led-1 {
color = <LED_COLOR_ID_RED>;
gpios = <&main_gpio0 15 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
function = LED_FUNCTION_DISK;
};
led-2 {
color = <LED_COLOR_ID_GREEN>;
gpios = <&main_gpio0 16 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc1";
function = LED_FUNCTION_DISK;
};
};
vcc_3v3_mmc: regulator-sd {
/* TPS22963C */
compatible = "regulator-fixed";
regulator-name = "VCC_3V3_MMC";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&main_pmx0 {
can_tc1_pins_default: can-tc1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (P16) GPMC0_ADVn_ALE.GPIO0_32 */
>;
};
can_tc2_pins_default: can-tc2-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0090, PIN_OUTPUT, 7) /* (P17) GPMC0_BE0n_CLE.GPIO0_35 */
>;
};
gpio_keys_pins_default: gpio-keys-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0044, PIN_INPUT, 7) /* (T18) GPMC0_AD2.GPIO0_17 */
AM64X_IOPAD(0x0054, PIN_INPUT, 7) /* (V20) GPMC0_AD6.GPIO0_21 */
>;
};
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT, 0) /* (C18) I2C1_SCL */
AM64X_IOPAD(0x026c, PIN_INPUT, 0) /* (B19) I2C1_SDA */
>;
};
main_mcan0_pins_default: main-mcan0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
>;
};
main_mcan1_pins_default: main-mcan1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
>;
};
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
>;
};
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
>;
};
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
AM64X_IOPAD(0x024C, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
>;
};
main_usb0_pins_default: main-usb0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
pcie_usb_sel_pins_default: pcie-usb-sel-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x017c, PIN_OUTPUT, 7) /* (T1) PRG0_PRU0_GPO7.GPIO1_7 */
>;
};
pcie0_pins_default: pcie0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (W19) GPMC0_WAIT0.GPIO0_37 */
>;
};
user_leds_pins_default: user-leds-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x003c, PIN_OUTPUT, 7) /* (T20) GPMC0_AD0.GPIO0_15 */
AM64X_IOPAD(0x0040, PIN_OUTPUT, 7) /* (U21) GPMC0_AD1.GPIO0_16 */
>;
};
};
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
eeprom@51 {
compatible = "atmel,24c02";
pagesize = <16>;
reg = <0x51>;
};
led-controller@62 {
compatible = "nxp,pca9533";
reg = <0x62>;
led-3 {
label = "red:user";
type = <PCA9532_TYPE_LED>;
};
led-4 {
label = "green:user";
type = <PCA9532_TYPE_LED>;
};
led-5 {
label = "blue:user";
type = <PCA9532_TYPE_LED>;
};
};
};
&main_mcan0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mcan0_pins_default>;
phys = <&can_tc1>;
};
&main_mcan1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mcan1_pins_default>;
phys = <&can_tc2>;
};
&main_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
current-speed = <115200>;
};
&main_uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
uart-has-rtscts;
current-speed = <115200>;
};
&sdhci1 {
status = "okay";
vmmc-supply = <&vcc_3v3_mmc>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
bus-width = <4>;
ti,driver-strength-ohm = <50>;
disable-wp;
no-1-8-v;
};
&serdes0 {
serdes0_pcie_usb_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_USB3>;
resets = <&serdes_wiz0 1>;
};
};
&serdes_ln_ctrl {
idle-states = <AM64_SERDES0_LANE0_USB>;
};
&usbss0 {
ti,vbus-divider;
};
&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&main_usb0_pins_default>;
dr_mode = "host";
maximum-speed = "super-speed";
phys = <&serdes0_pcie_usb_link>;
phy-names = "cdns3,usb3-phy";
};
arch/arm/dts/k3-am642-phycore-som-binman.dtsi
+457
View File
@@ -0,0 +1,457 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Based on k3-am64x-binman.dtsi
*
* Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*/
#include "k3-binman.dtsi"
#ifdef CONFIG_TARGET_PHYCORE_AM64X_R5
&binman {
tiboot3-am64x_sr2-hs-phycore-som.bin {
filename = "tiboot3-am64x_sr2-hs-phycore-som.bin";
ti-secure-rom {
content = <&u_boot_spl>, <&ti_sci_enc>,
<&combined_sysfw_cfg>, <&sysfw_inner_cert>;
combined;
sysfw-inner-cert;
keyfile = "custMpk.pem";
sw-rev = <1>;
content-sbl = <&u_boot_spl>;
content-sysfw = <&ti_sci_enc>;
content-sysfw-data = <&combined_sysfw_cfg>;
content-sysfw-inner-cert = <&sysfw_inner_cert>;
load = <0x70000000>;
load-sysfw = <0x44000>;
load-sysfw-data = <0x7b000>;
};
u_boot_spl: u-boot-spl {
no-expanded;
};
ti_sci_enc: ti-fs-enc.bin {
filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-enc.bin";
type = "blob-ext";
optional;
};
combined_sysfw_cfg: combined-sysfw-cfg.bin {
filename = "combined-sysfw-cfg.bin";
type = "blob-ext";
};
sysfw_inner_cert: sysfw-inner-cert {
filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-cert.bin";
type = "blob-ext";
optional;
};
};
};
&binman {
tiboot3-am64x_sr2-hs-fs-phycore-som.bin {
filename = "tiboot3-am64x_sr2-hs-fs-phycore-som.bin";
symlink = "tiboot3.bin";
ti-secure-rom {
content = <&u_boot_spl_fs>, <&ti_sci_enc_fs>,
<&combined_sysfw_cfg_fs>, <&sysfw_inner_cert_fs>;
combined;
sysfw-inner-cert;
keyfile = "custMpk.pem";
sw-rev = <1>;
content-sbl = <&u_boot_spl_fs>;
content-sysfw = <&ti_sci_enc_fs>;
content-sysfw-data = <&combined_sysfw_cfg_fs>;
content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
load = <0x70000000>;
load-sysfw = <0x44000>;
load-sysfw-data = <0x7b000>;
};
u_boot_spl_fs: u-boot-spl {
no-expanded;
};
ti_sci_enc_fs: ti-fs-enc.bin {
filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-fs-enc.bin";
type = "blob-ext";
optional;
};
combined_sysfw_cfg_fs: combined-sysfw-cfg.bin {
filename = "combined-sysfw-cfg.bin";
type = "blob-ext";
};
sysfw_inner_cert_fs: sysfw-inner-cert {
filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-fs-cert.bin";
type = "blob-ext";
optional;
};
};
};
&binman {
tiboot3-am64x-gp-phycore-som.bin {
filename = "tiboot3-am64x-gp-phycore-som.bin";
ti-secure-rom {
content = <&u_boot_spl_unsigned>, <&ti_sci_gp>, <&combined_sysfw_cfg_gp>;
combined;
content-sbl = <&u_boot_spl_unsigned>;
load = <0x70000000>;
content-sysfw = <&ti_sci_gp>;
load-sysfw = <0x44000>;
content-sysfw-data = <&combined_sysfw_cfg_gp>;
load-sysfw-data = <0x7b000>;
sw-rev = <1>;
keyfile = "ti-degenerate-key.pem";
};
u_boot_spl_unsigned: u-boot-spl {
no-expanded;
};
ti_sci_gp: ti-sci-gp.bin {
filename = "ti-sysfw/ti-sci-firmware-am64x-gp.bin";
type = "blob-ext";
optional;
};
combined_sysfw_cfg_gp: combined-sysfw-cfg-gp.bin {
filename = "combined-sysfw-cfg.bin";
type = "blob-ext";
};
};
};
#endif
#ifdef CONFIG_TARGET_PHYCORE_AM64X_A53
#define SPL_AM642_PHYBOARD_ELECTRA_DTB "spl/dts/k3-am642-phyboard-electra-rdk.dtb"
#define AM642_PHYBOARD_ELECTRA_DTB "u-boot.dtb"
&binman {
ti-spl {
insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
dm {
blob-ext {
filename = "/dev/null";
};
};
fdt-0 {
description = "k3-am642-phyboard-electra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
ti-secure {
content = <&spl_am642_phyboard_electra_dtb>;
keyfile = "custMpk.pem";
};
spl_am642_phyboard_electra_dtb: blob-ext {
filename = SPL_AM642_PHYBOARD_ELECTRA_DTB;
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am642-phyboard-electra-rdk";
firmware = "atf";
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
};
};
};
};
&binman {
u-boot {
insert-template = <&u_boot_template>;
fit {
images {
uboot {
description = "U-Boot for AM64 board";
};
fdt-0 {
description = "k3-am642-phyboard-electra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
ti-secure {
content = <&am642_phyboard_electra_dtb>;
keyfile = "custMpk.pem";
};
am642_phyboard_electra_dtb: blob-ext {
filename = AM642_PHYBOARD_ELECTRA_DTB;
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am642-phyboard-electra-rdk";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
&binman {
ti-spl_unsigned {
insert-template = <&ti_spl_unsigned_template>;
fit {
images {
dm {
blob-ext {
filename = "/dev/null";
};
};
fdt-0 {
description = "k3-am642-phyboard-electra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
filename = SPL_AM642_PHYBOARD_ELECTRA_DTB;
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am642-phyboard-electra-rdk";
firmware = "atf";
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
};
};
};
};
&binman {
u-boot_unsigned {
insert-template = <&u_boot_unsigned_template>;
fit {
images {
uboot {
description = "U-Boot for AM64 board";
};
fdt-0 {
description = "k3-am642-phyboard-electra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
filename = AM642_PHYBOARD_ELECTRA_DTB;
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am642-phyboard-electra-rdk";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
#endif
#ifdef CONFIG_TARGET_PHYCORE_AM64X_A53
#define SPL_AM642_PHYBOARD_ELECTRA_DTB "spl/dts/k3-am642-phyboard-electra-rdk.dtb"
#define AM642_PHYBOARD_ELECTRA_DTB "u-boot.dtb"
&binman {
ti-spl {
insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
dm {
blob-ext {
filename = "/dev/null";
};
};
fdt-0 {
description = "k3-am642-phyboard-electra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
ti-secure {
content = <&spl_am642_phyboard_electra_dtb>;
keyfile = "custMpk.pem";
};
spl_am642_phyboard_electra_dtb: blob-ext {
filename = SPL_AM642_PHYBOARD_ELECTRA_DTB;
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am642-phyboard-electra-rdk";
firmware = "atf";
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
};
};
};
};
&binman {
u-boot {
insert-template = <&u_boot_template>;
fit {
images {
uboot {
description = "U-Boot for AM64 board";
};
fdt-0 {
description = "k3-am642-phyboard-electra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
ti-secure {
content = <&am642_phyboard_electra_dtb>;
keyfile = "custMpk.pem";
};
am642_phyboard_electra_dtb: blob-ext {
filename = AM642_PHYBOARD_ELECTRA_DTB;
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am642-phyboard-electra-rdk";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
&binman {
ti-spl_unsigned {
insert-template = <&ti_spl_unsigned_template>;
fit {
images {
dm {
blob-ext {
filename = "/dev/null";
};
};
fdt-0 {
description = "k3-am642-phyboard-electra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
filename = SPL_AM642_PHYBOARD_ELECTRA_DTB;
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am642-phyboard-electra-rdk";
firmware = "atf";
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
};
};
};
};
&binman {
u-boot_unsigned {
insert-template = <&u_boot_unsigned_template>;
fit {
images {
uboot {
description = "U-Boot for AM64 board";
};
fdt-0 {
description = "k3-am642-phyboard-electra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
filename = AM642_PHYBOARD_ELECTRA_DTB;
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am642-phyboard-electra-rdk";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
#endif /* CONFIG_TARGET_PHYCORE_AM64X_A53 */
arch/arm/dts/k3-am642-r5-evm.dts
+5 -24
View File
@@ -40,10 +40,6 @@
};
};
&vtt_supply {
bootph-pre-ram;
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
@@ -53,18 +49,6 @@
};
};
&main_esm {
bootph-pre-ram;
};
&cbass_mcu {
bootph-pre-ram;
};
&mcu_esm {
bootph-pre-ram;
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
@@ -74,10 +58,6 @@
ti,secure-host;
};
&vtt_supply {
bootph-pre-ram;
};
&memorycontroller {
vtt-supply = <&vtt_supply>;
};
@@ -92,10 +72,6 @@
clock-names = "clk_xin";
};
&main_gpio0 {
bootph-pre-ram;
};
/* UART is initialized before SYSFW is started
* so we can't do any power-domain/clock operations.
* Delete clock/power-domain properties to avoid
@@ -120,3 +96,8 @@
/delete-property/ assigned-clock-parents;
/delete-property/ power-domains;
};
&ospi0 {
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x00 0x60000000 0x00 0x8000000>;
};
arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts
+140
View File
@@ -0,0 +1,140 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
* Author: Matt McKee <mmckee@phytec.com>
*
* Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*/
/dts-v1/;
#include "k3-am642-phyboard-electra-rdk.dts"
#include "k3-am64-phycore-som-ddr4-2gb.dtsi"
#include "k3-am64-ddr.dtsi"
#include "k3-am642-phyboard-electra-rdk-u-boot.dtsi"
/ {
aliases {
ethernet0 = &cpsw3g;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1000000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
clk_200mhz: dummy-clock-200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
bootph-pre-ram;
};
vtt_supply: vtt-supply {
compatible = "regulator-fixed";
regulator-name = "vtt";
pinctrl-names = "default";
pinctrl-0 = <&ddr_vtt_pins_default>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpios = <&main_gpio0 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
bootph-pre-ram;
};
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
mbox-names = "tx", "rx";
bootph-pre-ram;
};
};
&cbass_mcu {
bootph-pre-ram;
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&main_esm {
bootph-pre-ram;
};
&main_gpio0 {
bootph-pre-ram;
};
&main_pmx0 {
bootph-pre-ram;
ddr_vtt_pins_default: ddr-vtt-default-pins {
bootph-pre-ram;
pinctrl-single,pins = <
AM64X_IOPAD(0x0038, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN3.GPIO0_14 */
>;
};
};
/* timer init is called as part of rproc_start() while
* starting System Firmware, so any clock/power-domain
* operations will fail as SYSFW is not yet up and running.
* Delete all clock/power-domain properties to avoid
* timer init failure.
* This is an always on timer at 20MHz.
*/
&main_timer0 {
/delete-property/ clocks;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ power-domains;
};
/* UART is initialized before SYSFW is started
* so we can't do any power-domain/clock operations.
* Delete clock/power-domain properties to avoid
* UART init failure
*/
&main_uart0 {
/delete-property/ power-domains;
/delete-property/ clocks;
/delete-property/ clock-names;
};
&mcu_esm {
bootph-pre-ram;
};
&memorycontroller {
vtt-supply = <&vtt_supply>;
};
&ospi0 {
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x00 0x60000000 0x00 0x08000000>;
};
arch/arm/dts/k3-am642-r5-sk.dts
+5 -12
View File
@@ -49,18 +49,6 @@
};
};
&main_esm {
bootph-pre-ram;
};
&cbass_mcu {
bootph-pre-ram;
};
&mcu_esm {
bootph-pre-ram;
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
@@ -103,3 +91,8 @@
/delete-property/ assigned-clock-parents;
/delete-property/ power-domains;
};
&ospi0 {
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x00 0x60000000 0x00 0x8000000>;
};
arch/arm/dts/k3-am642-sk-u-boot.dtsi
+7 -85
View File
@@ -9,87 +9,21 @@
chosen {
tick-timer = &main_timer0;
};
memory@80000000 {
bootph-all;
};
};
&cbass_main{
bootph-all;
};
&main_timer0 {
bootph-all;
clock-frequency = <200000000>;
};
&main_conf {
bootph-all;
chipid@14 {
bootph-all;
};
};
&main_pmx0 {
bootph-all;
};
&main_i2c0_pins_default {
bootph-all;
};
&main_i2c0 {
bootph-all;
};
&main_uart0_pins_default {
bootph-all;
};
&main_uart0 {
bootph-all;
};
&dmss {
bootph-all;
};
&secure_proxy_main {
bootph-all;
};
&dmsc {
bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-all;
};
};
&k3_pds {
bootph-all;
};
&k3_clks {
bootph-all;
};
&k3_reset {
bootph-all;
};
&sdhci0 {
status = "disabled";
bootph-all;
};
&sdhci1 {
bootph-all;
};
&main_mmc1_pins_default {
bootph-all;
};
&inta_main_dmss {
@@ -180,34 +114,22 @@
bootph-all;
};
&main_usb0_pins_default {
bootph-all;
};
&serdes_ln_ctrl {
u-boot,mux-autoprobe;
};
&usbss0 {
bootph-all;
};
&usb0 {
&ospi0_pins_default {
bootph-all;
};
&serdes_wiz0 {
&fss {
bootph-all;
};
&serdes0_usb_link {
bootph-all;
};
&ospi0 {
bootph-all;
&serdes0 {
bootph-all;
};
&serdes_refclk {
bootph-all;
flash@0 {
bootph-all;
};
};
arch/arm/dts/k3-am64x-binman.dtsi
+3 -3
View File
@@ -118,11 +118,11 @@
#ifdef CONFIG_TARGET_AM642_A53_EVM
#define SPL_AM642_EVM_DTB "spl/dts/k3-am642-evm.dtb"
#define SPL_AM642_SK_DTB "spl/dts/k3-am642-sk.dtb"
#define SPL_AM642_EVM_DTB "spl/dts/ti/k3-am642-evm.dtb"
#define SPL_AM642_SK_DTB "spl/dts/ti/k3-am642-sk.dtb"
#define AM642_EVM_DTB "u-boot.dtb"
#define AM642_SK_DTB "arch/arm/dts/k3-am642-sk.dtb"
#define AM642_SK_DTB "dts/upstream/src/arm64/ti/k3-am642-sk.dtb"
&binman {
ti-spl {
arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
+2 -2
View File
@@ -51,8 +51,8 @@
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
load = <CONFIG_K3_OPTEE_LOAD_ADDR>;
entry = <CONFIG_K3_OPTEE_LOAD_ADDR>;
tee-os {
};
};
arch/arm/dts/k3-am69-r5-sk.dts
+106
View File
@@ -0,0 +1,106 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "k3-am69-sk.dts"
#include "k3-j784s4-ddr-evm-lp4-4266.dtsi"
#include "k3-j784s4-ddr.dtsi"
#include "k3-am69-sk-u-boot.dtsi"
/ {
chosen {
tick-timer = &mcu_timer0;
};
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a72_0;
};
a72_0: a72@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
clocks = <&k3_clks 61 0>;
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <2000000000>;
ti,sci = <&sms>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <3>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_mcu 21>, <&secure_proxy_mcu 23>;
bootph-pre-ram;
};
};
&mcu_timer0 {
status = "okay";
clock-frequency = <250000000>;
bootph-pre-ram;
};
&secure_proxy_sa3 {
status = "okay";
bootph-pre-ram;
};
&secure_proxy_mcu {
status = "okay";
bootph-pre-ram;
};
&cbass_mcu_wakeup {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_mcu 4>,
<&secure_proxy_mcu 5>,
<&secure_proxy_sa3 5>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
&sms {
mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
bootph-pre-ram;
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
bootph-pre-ram;
status = "okay";
};
&ospi0 {
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;
};
&ospi1 {
reg = <0x0 0x47050000 0x0 0x100>,
<0x0 0x58000000 0x0 0x8000000>;
};
&mcu_ringacc {
ti,sci = <&dm_tifs>;
};
&mcu_udmap {
ti,sci = <&dm_tifs>;
};
arch/arm/dts/k3-am69-sk-u-boot.dtsi
+54
View File
@@ -0,0 +1,54 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-j784s4-binman.dtsi"
/ {
memory@80000000 {
bootph-all;
};
};
&mcu_udmap {
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x284c0000 0x0 0x4000>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x284a0000 0x0 0x4000>,
<0x0 0x2aa00000 0x0 0x40000>,
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
bootph-pre-ram;
};
&sms {
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-pre-ram;
};
};
#ifdef CONFIG_TARGET_J784S4_A72_EVM
#define SPL_AM69_SK_DTB "spl/dts/ti/k3-am69-sk.dtb"
#define AM69_SK_DTB "u-boot.dtb"
&spl_j784s4_evm_dtb {
filename = SPL_AM69_SK_DTB;
};
&j784s4_evm_dtb {
filename = AM69_SK_DTB;
};
&spl_j784s4_evm_dtb_unsigned {
filename = SPL_AM69_SK_DTB;
};
&j784s4_evm_dtb_unsigned {
filename = AM69_SK_DTB;
};
#endif
arch/arm/dts/k3-binman.dtsi
+6 -4
View File
@@ -286,13 +286,14 @@
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
load = <CONFIG_K3_OPTEE_LOAD_ADDR>;
entry = <CONFIG_K3_OPTEE_LOAD_ADDR>;
ti-secure {
content = <&tee>;
keyfile = "custMpk.pem";
};
tee: tee-os {
optional;
};
};
@@ -356,10 +357,11 @@
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
load = <CONFIG_K3_OPTEE_LOAD_ADDR>;
entry = <CONFIG_K3_OPTEE_LOAD_ADDR>;
tee-os {
filename = "tee-raw.bin";
optional;
};
};
arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+4
View File
@@ -195,6 +195,10 @@
&ospi0 {
bootph-all;
flash@0 {
bootph-all;
};
};
&serdes_ln_ctrl {
arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+14 -1
View File
@@ -52,7 +52,7 @@
};
&mcu_timer0 {
clock-frequency = <25000000>;
clock-frequency = <250000000>;
bootph-pre-ram;
};
@@ -83,3 +83,16 @@
&wkup_vtm0 {
bootph-pre-ram;
};
&ospi0 {
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;
};
&mcu_ringacc {
ti,sci = <&dm_tifs>;
};
&mcu_udmap {
ti,sci = <&dm_tifs>;
};
arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
+2 -4
View File
@@ -165,7 +165,6 @@
&serdes_ln_ctrl {
bootph-all;
u-boot,mux-autoprobe;
};
&serdes2_usb_link {
@@ -174,7 +173,6 @@
&usb_serdes_mux {
bootph-all;
u-boot,mux-autoprobe;
};
&serdes_wiz2 {
@@ -250,8 +248,8 @@
arch = "arm64";
compression = "none";
os = "tee";
load = <0x9e800000>;
entry = <0x9e800000>;
load = <CONFIG_K3_OPTEE_LOAD_ADDR>;
entry = <CONFIG_K3_OPTEE_LOAD_ADDR>;
tee-os {
filename = "tee-raw.bin";
};
arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+2 -2
View File
@@ -94,11 +94,11 @@
};
&serdes_ln_ctrl {
u-boot,mux-autoprobe;
bootph-all;
};
&usb_serdes_mux {
u-boot,mux-autoprobe;
bootph-all;
};
&main_usbss0_pins_default {
arch/arm/dts/k3-j721e-sk-u-boot.dtsi
+2 -6
View File
@@ -90,11 +90,11 @@
};
&serdes_ln_ctrl {
u-boot,mux-autoprobe;
bootph-all;
};
&usb_serdes_mux {
u-boot,mux-autoprobe;
bootph-all;
};
&main_usbss0_pins_default {
@@ -157,9 +157,5 @@
flash@0 {
bootph-all;
partition@3fc0000 {
bootph-all;
};
};
};
arch/arm/dts/k3-j784s4-binman.dtsi
+345
View File
@@ -0,0 +1,345 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-binman.dtsi"
#ifdef CONFIG_TARGET_J784S4_R5_EVM
&rcfg_yaml_tifs {
config = "tifs-rm-cfg.yaml";
};
&binman {
tiboot3-j784s4-hs-evm.bin {
filename = "tiboot3-j784s4-hs-evm.bin";
ti-secure-rom {
content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>,
<&combined_dm_cfg>, <&sysfw_inner_cert>;
combined;
dm-data;
sysfw-inner-cert;
keyfile = "custMpk.pem";
sw-rev = <1>;
content-sbl = <&u_boot_spl>;
content-sysfw = <&ti_fs_enc>;
content-sysfw-data = <&combined_tifs_cfg>;
content-sysfw-inner-cert = <&sysfw_inner_cert>;
content-dm-data = <&combined_dm_cfg>;
load = <0x41c00000>;
load-sysfw = <0x40000>;
load-sysfw-data = <0x66800>;
load-dm-data = <0x41c80000>;
};
u_boot_spl: u-boot-spl {
no-expanded;
};
ti_fs_enc: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg: combined-tifs-cfg.bin {
filename = "combined-tifs-cfg.bin";
type = "blob-ext";
};
sysfw_inner_cert: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin";
type = "blob-ext";
optional;
};
combined_dm_cfg: combined-dm-cfg.bin {
filename = "combined-dm-cfg.bin";
type = "blob-ext";
};
};
};
&binman {
tiboot3-j784s4-hs-fs-evm.bin {
filename = "tiboot3-j784s4-hs-fs-evm.bin";
ti-secure-rom {
content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
<&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
combined;
dm-data;
sysfw-inner-cert;
keyfile = "custMpk.pem";
sw-rev = <1>;
content-sbl = <&u_boot_spl_fs>;
content-sysfw = <&ti_fs_enc_fs>;
content-sysfw-data = <&combined_tifs_cfg_fs>;
content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
content-dm-data = <&combined_dm_cfg_fs>;
load = <0x41c00000>;
load-sysfw = <0x40000>;
load-sysfw-data = <0x66800>;
load-dm-data = <0x41c80000>;
};
u_boot_spl_fs: u-boot-spl {
no-expanded;
};
ti_fs_enc_fs: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-enc.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg_fs: combined-tifs-cfg.bin {
filename = "combined-tifs-cfg.bin";
type = "blob-ext";
};
sysfw_inner_cert_fs: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-cert.bin";
type = "blob-ext";
optional;
};
combined_dm_cfg_fs: combined-dm-cfg.bin {
filename = "combined-dm-cfg.bin";
type = "blob-ext";
};
};
};
&binman {
tiboot3-j784s4-gp-evm.bin {
filename = "tiboot3-j784s4-gp-evm.bin";
symlink = "tiboot3.bin";
ti-secure-rom {
content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
combined;
dm-data;
content-sbl = <&u_boot_spl_unsigned>;
load = <0x41c00000>;
content-sysfw = <&ti_fs_gp>;
load-sysfw = <0x40000>;
content-sysfw-data = <&combined_tifs_cfg_gp>;
load-sysfw-data = < 0x66800>;
content-dm-data = <&combined_dm_cfg_gp>;
load-dm-data = <0x41c80000>;
sw-rev = <1>;
keyfile = "ti-degenerate-key.pem";
};
u_boot_spl_unsigned: u-boot-spl {
no-expanded;
};
ti_fs_gp: ti-fs-gp.bin {
filename = "ti-sysfw/ti-fs-firmware-j784s4-gp.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
filename = "combined-tifs-cfg.bin";
type = "blob-ext";
};
combined_dm_cfg_gp: combined-dm-cfg-gp.bin {
filename = "combined-dm-cfg.bin";
type = "blob-ext";
};
};
};
#endif
#ifdef CONFIG_TARGET_J784S4_A72_EVM
#define SPL_J784S4_EVM_DTB "spl/dts/ti/k3-j784s4-evm.dtb"
#define J784S4_EVM_DTB "u-boot.dtb"
&binman {
ti-dm {
filename = "ti-dm.bin";
blob-ext {
filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
};
};
ti-spl {
insert-template = <&ti_spl_template>;
fit {
images {
dm {
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
};
dm: blob-ext {
filename = "ti-dm.bin";
};
};
fdt-0 {
description = "k3-j784s4-evm";
type = "flat_dt";
arch = "arm";
compression = "none";
ti-secure {
content = <&spl_j784s4_evm_dtb>;
keyfile = "custMpk.pem";
};
spl_j784s4_evm_dtb: blob-ext {
filename = SPL_J784S4_EVM_DTB;
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-j784s4-evm";
firmware = "atf";
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
};
};
};
};
&binman {
u-boot {
insert-template = <&u_boot_template>;
fit {
images {
uboot {
description = "U-Boot for J784S4 board";
};
fdt-0 {
description = "k3-j784s4-evm";
type = "flat_dt";
arch = "arm";
compression = "none";
ti-secure {
content = <&j784s4_evm_dtb>;
keyfile = "custMpk.pem";
};
j784s4_evm_dtb: blob-ext {
filename = J784S4_EVM_DTB;
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-j784s4-evm";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
&binman {
ti-spl_unsigned {
insert-template = <&ti_spl_unsigned_template>;
fit {
images {
dm {
blob-ext {
filename = "ti-dm.bin";
};
};
fdt-0 {
description = "k3-j784s4-evm";
type = "flat_dt";
arch = "arm";
compression = "none";
spl_j784s4_evm_dtb_unsigned: blob {
filename = SPL_J784S4_EVM_DTB;
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-j784s4-evm";
firmware = "atf";
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
};
};
};
};
&binman {
u-boot_unsigned {
insert-template = <&u_boot_unsigned_template>;
fit {
images {
uboot {
description = "U-Boot for J784S4 board";
};
fdt-0 {
description = "k3-j784s4-evm";
type = "flat_dt";
arch = "arm";
compression = "none";
j784s4_evm_dtb_unsigned: blob {
filename = J784S4_EVM_DTB;
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-j784s4-evm";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
#endif
arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
+8757
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File diff suppressed because it is too large Load Diff
arch/arm/dts/k3-j784s4-ddr.dtsi
+8858
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File diff suppressed because it is too large Load Diff
arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
+31
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@@ -0,0 +1,31 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-j784s4-binman.dtsi"
/ {
memory@80000000 {
bootph-all;
};
};
&mcu_udmap {
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x284c0000 0x0 0x4000>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x284a0000 0x0 0x4000>,
<0x0 0x2aa00000 0x0 0x40000>,
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
bootph-pre-ram;
};
&sms {
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-pre-ram;
};
};
arch/arm/dts/k3-j784s4-r5-evm.dts
+106
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@@ -0,0 +1,106 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "k3-j784s4-evm.dts"
#include "k3-j784s4-ddr-evm-lp4-4266.dtsi"
#include "k3-j784s4-ddr.dtsi"
#include "k3-j784s4-evm-u-boot.dtsi"
/ {
chosen {
tick-timer = &mcu_timer0;
};
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a72_0;
};
a72_0: a72@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
clocks = <&k3_clks 61 0>;
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <2000000000>;
ti,sci = <&sms>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <3>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_mcu 21>, <&secure_proxy_mcu 23>;
bootph-pre-ram;
};
};
&mcu_timer0 {
status = "okay";
clock-frequency = <250000000>;
bootph-pre-ram;
};
&secure_proxy_sa3 {
status = "okay";
bootph-pre-ram;
};
&secure_proxy_mcu {
status = "okay";
bootph-pre-ram;
};
&cbass_mcu_wakeup {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_mcu 4>,
<&secure_proxy_mcu 5>,
<&secure_proxy_sa3 5>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
&sms {
mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
bootph-pre-ram;
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
bootph-pre-ram;
status = "okay";
};
&ospi0 {
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;
};
&ospi1 {
reg = <0x0 0x47050000 0x0 0x100>,
<0x0 0x58000000 0x0 0x8000000>;
};
&mcu_ringacc {
ti,sci = <&dm_tifs>;
};
&mcu_udmap {
ti,sci = <&dm_tifs>;
};
arch/arm/dts/meson-gxbb-p200.dts
-100
View File
@@ -1,100 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
* Copyright (c) 2016 BayLibre, Inc.
* Author: Kevin Hilman <khilman@kernel.org>
*/
/dts-v1/;
#include "meson-gxbb-p20x.dtsi"
#include <dt-bindings/input/input.h>
/ {
compatible = "amlogic,p200", "amlogic,meson-gxbb";
model = "Amlogic Meson GXBB P200 Development Board";
avdd18_usb_adc: regulator-avdd18_usb_adc {
compatible = "regulator-fixed";
regulator-name = "AVDD18_USB_ADC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
adc_keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
button-home {
label = "Home";
linux,code = <KEY_HOME>;
press-threshold-microvolt = <900000>; /* 50% */
};
button-esc {
label = "Esc";
linux,code = <KEY_ESC>;
press-threshold-microvolt = <684000>; /* 38% */
};
button-up {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
press-threshold-microvolt = <468000>; /* 26% */
};
button-down {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
press-threshold-microvolt = <252000>; /* 14% */
};
button-menu {
label = "Menu";
linux,code = <KEY_MENU>;
press-threshold-microvolt = <0>; /* 0% */
};
};
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_rgmii_pins>;
pinctrl-names = "default";
phy-handle = <&eth_phy0>;
phy-mode = "rgmii";
amlogic,tx-delay-ns = <2>;
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
eth_phy0: ethernet-phy@3 {
/* Micrel KSZ9031 (0x00221620) */
reg = <3>;
reset-assert-us = <10000>;
reset-deassert-us = <30000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_15 */
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&i2c_B {
status = "okay";
pinctrl-0 = <&i2c_b_pins>;
pinctrl-names = "default";
};
&saradc {
status = "okay";
vref-supply = <&avdd18_usb_adc>;
};
arch/arm/dts/meson-gxbb-p201.dts
-26
View File
@@ -1,26 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
* Copyright (c) 2016 BayLibre, Inc.
* Author: Kevin Hilman <khilman@kernel.org>
*/
/dts-v1/;
#include "meson-gxbb-p20x.dtsi"
/ {
compatible = "amlogic,p201", "amlogic,meson-gxbb";
model = "Amlogic Meson GXBB P201 Development Board";
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_rmii_pins>;
pinctrl-names = "default";
phy-mode = "rmii";
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0>, <10000>, <1000000>;
snps,reset-active-low;
};
arch/arm/dts/msm8916-pm8916.dtsi
+157
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@@ -0,0 +1,157 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* msm8916-pm8916.dtsi describes common properties (e.g. regulator connections)
* that apply to most devices that make use of the MSM8916 SoC and PM8916 PMIC.
* Many regulators have a fixed purpose in the original reference design and
* were rarely re-used for different purposes. Devices that deviate from the
* typical reference design should not make use of this include and instead add
* the necessary properties in the board-specific device tree.
*/
#include "msm8916.dtsi"
#include "pm8916.dtsi"
&camss {
vdda-supply = <&pm8916_l2>;
};
&mdss_dsi0 {
vdda-supply = <&pm8916_l2>;
vddio-supply = <&pm8916_l6>;
};
&mdss_dsi0_phy {
vddio-supply = <&pm8916_l6>;
};
&mpss {
pll-supply = <&pm8916_l7>;
};
&pm8916_codec {
vdd-cdc-io-supply = <&pm8916_l5>;
vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>;
vdd-micbias-supply = <&pm8916_l13>;
};
&sdhc_1 {
vmmc-supply = <&pm8916_l8>;
vqmmc-supply = <&pm8916_l5>;
};
&sdhc_2 {
vmmc-supply = <&pm8916_l11>;
vqmmc-supply = <&pm8916_l12>;
};
&usb_hs_phy {
v1p8-supply = <&pm8916_l7>;
v3p3-supply = <&pm8916_l13>;
};
&wcnss {
vddpx-supply = <&pm8916_l7>;
};
&wcnss_iris {
vddxo-supply = <&pm8916_l7>;
vddrfa-supply = <&pm8916_s3>;
vddpa-supply = <&pm8916_l9>;
vdddig-supply = <&pm8916_l5>;
};
&rpm_requests {
pm8916_rpm_regulators: regulators {
compatible = "qcom,rpm-pm8916-regulators";
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l4_l5_l6-supply = <&pm8916_s4>;
vdd_l7-supply = <&pm8916_s4>;
/* pm8916_s1 is managed by rpmpd (MSM8916_VDDCX) */
pm8916_s3: s3 {
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1350000>;
regulator-always-on; /* Needed for L2 */
};
pm8916_s4: s4 {
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <2150000>;
regulator-always-on; /* Needed for L5/L7 */
};
/*
* Some of the regulators are unused or managed by another
* processor (e.g. the modem). We should still define nodes for
* them to ensure the vote from the application processor can be
* dropped in case the regulators are already on during boot.
*
* The labels for these nodes are omitted on purpose because
* boards should configure a proper voltage before using them.
*/
l1 {};
pm8916_l2: l2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on; /* Needed for LPDDR RAM */
};
/* pm8916_l3 is managed by rpmpd (MSM8916_VDDMX) */
l4 {};
pm8916_l5: l5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on; /* Needed for most digital I/O */
};
pm8916_l6: l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8916_l7: l7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on; /* Needed for CPU PLL */
};
pm8916_l8: l8 {
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
};
pm8916_l9: l9 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
l10 {};
pm8916_l11: l11 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
regulator-system-load = <200000>;
};
pm8916_l12: l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
pm8916_l13: l13 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3075000>;
};
l14 {};
l15 {};
l16 {};
l17 {};
l18 {};
};
};
arch/arm/dts/msm8916.dtsi
+2702
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File diff suppressed because it is too large Load Diff
arch/arm/dts/msm8996.dtsi
+3884
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File diff suppressed because it is too large Load Diff
arch/arm/dts/mt7988-sd-rfb.dts
+2
View File
@@ -87,10 +87,12 @@
pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI",
"SPI2_CLK", "SPI2_HOLD";
input-enable;
drive-strength = <MTK_DRIVE_4mA>;
};
conf-clk {
pins = "SPI2_WP";
drive-strength = <MTK_DRIVE_4mA>;
};
};
};
arch/arm/dts/mt7988.dtsi
+1
View File
@@ -9,6 +9,7 @@
#include <dt-bindings/clock/mt7988-clk.h>
#include <dt-bindings/reset/mt7988-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include <dt-bindings/phy/phy.h>
/ {
arch/arm/dts/pm8916.dtsi
+178
View File
@@ -0,0 +1,178 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
pm8916_0: pmic@0 {
compatible = "qcom,pm8916", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x800>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_POWER>;
};
pm8916_resin: resin {
compatible = "qcom,pm8941-resin";
interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
status = "disabled";
};
watchdog {
compatible = "qcom,pm8916-wdt";
interrupts = <0x0 0x8 6 IRQ_TYPE_EDGE_RISING>;
timeout-sec = <60>;
};
};
pm8916_usbin: usb-detect@1300 {
compatible = "qcom,pm8941-misc";
reg = <0x1300>;
interrupts = <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "usb_vbus";
status = "disabled";
};
pm8916_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
io-channels = <&pm8916_vadc VADC_DIE_TEMP>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};
pm8916_vadc: adc@3100 {
compatible = "qcom,spmi-vadc";
reg = <0x3100>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@0 {
reg = <VADC_USBIN>;
qcom,pre-scaling = <1 10>;
};
channel@7 {
reg = <VADC_VSYS>;
qcom,pre-scaling = <1 3>;
};
channel@8 {
reg = <VADC_DIE_TEMP>;
};
channel@9 {
reg = <VADC_REF_625MV>;
};
channel@a {
reg = <VADC_REF_1250MV>;
};
channel@e {
reg = <VADC_GND_REF>;
};
channel@f {
reg = <VADC_VDD_VADC>;
};
};
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>, <0x6100>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
};
pm8916_mpps: mpps@a000 {
compatible = "qcom,pm8916-mpp", "qcom,spmi-mpp";
reg = <0xa000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pm8916_mpps 0 0 4>;
interrupt-controller;
#interrupt-cells = <2>;
};
pm8916_gpios: gpio@c000 {
compatible = "qcom,pm8916-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pm8916_gpios 0 0 4>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pm8916_1: pmic@1 {
compatible = "qcom,pm8916", "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8916_pwm: pwm {
compatible = "qcom,pm8916-pwm";
#pwm-cells = <2>;
status = "disabled";
};
pm8916_vib: vibrator@c000 {
compatible = "qcom,pm8916-vib";
reg = <0xc000>;
status = "disabled";
};
pm8916_codec: audio-codec@f000 {
compatible = "qcom,pm8916-wcd-analog-codec";
reg = <0xf000>;
interrupt-parent = <&spmi_bus>;
interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>,
<0x1 0xf0 0x1 IRQ_TYPE_NONE>,
<0x1 0xf0 0x2 IRQ_TYPE_NONE>,
<0x1 0xf0 0x3 IRQ_TYPE_NONE>,
<0x1 0xf0 0x4 IRQ_TYPE_NONE>,
<0x1 0xf0 0x5 IRQ_TYPE_NONE>,
<0x1 0xf0 0x6 IRQ_TYPE_NONE>,
<0x1 0xf0 0x7 IRQ_TYPE_NONE>,
<0x1 0xf1 0x0 IRQ_TYPE_NONE>,
<0x1 0xf1 0x1 IRQ_TYPE_NONE>,
<0x1 0xf1 0x2 IRQ_TYPE_NONE>,
<0x1 0xf1 0x3 IRQ_TYPE_NONE>,
<0x1 0xf1 0x4 IRQ_TYPE_NONE>,
<0x1 0xf1 0x5 IRQ_TYPE_NONE>;
interrupt-names = "cdc_spk_cnp_int",
"cdc_spk_clip_int",
"cdc_spk_ocp_int",
"mbhc_ins_rem_det1",
"mbhc_but_rel_det",
"mbhc_but_press_det",
"mbhc_ins_rem_det",
"mbhc_switch_int",
"cdc_ear_ocp_int",
"cdc_hphr_ocp_int",
"cdc_hphl_ocp_det",
"cdc_ear_cnp_int",
"cdc_hphr_cnp_int",
"cdc_hphl_cnp_int";
#sound-dai-cells = <1>;
status = "disabled";
};
};
};
arch/arm/dts/pm8994.dtsi
+152
View File
@@ -0,0 +1,152 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pm8994-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&pm8994_temp>;
trips {
pm8994_alert0: pm8994-alert0 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
pm8994_crit: pm8994-crit {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pmic@0 {
compatible = "qcom,pm8994", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>, <0x6100>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
};
pm8994_pon: pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x800>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_POWER>;
};
pm8994_resin: resin {
compatible = "qcom,pm8941-resin";
interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
status = "disabled";
};
};
pm8994_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
io-channels = <&pm8994_vadc VADC_DIE_TEMP>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};
pm8994_vadc: adc@3100 {
compatible = "qcom,spmi-vadc";
reg = <0x3100>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@7 {
reg = <VADC_VSYS>;
qcom,pre-scaling = <1 3>;
label = "vph_pwr";
};
channel@8 {
reg = <VADC_DIE_TEMP>;
label = "die_temp";
};
channel@9 {
reg = <VADC_REF_625MV>;
label = "ref_625mv";
};
channel@a {
reg = <VADC_REF_1250MV>;
label = "ref_1250mv";
};
channel@e {
reg = <VADC_GND_REF>;
};
channel@f {
reg = <VADC_VDD_VADC>;
};
};
pm8994_gpios: gpio@c000 {
compatible = "qcom,pm8994-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pm8994_gpios 0 0 22>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pm8994_mpps: mpps@a000 {
compatible = "qcom,pm8994-mpp", "qcom,spmi-mpp";
reg = <0xa000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pm8994_mpps 0 0 8>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pmic@1 {
compatible = "qcom,pm8994", "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8994_lpg: pwm {
compatible = "qcom,pm8994-lpg";
#address-cells = <1>;
#size-cells = <0>;
#pwm-cells = <2>;
status = "disabled";
};
pm8994_spmi_regulators: regulators {
compatible = "qcom,pm8994-regulators";
};
};
};
arch/arm/dts/pm8998.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/* Copyright 2018 Google LLC. */
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/thermal/thermal.h>
/ {
thermal-zones {
pm8998-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&pm8998_temp>;
trips {
pm8998_alert0: pm8998-alert0 {
temperature = <105000>;
hysteresis = <2000>;
type = "passive";
};
pm8998_crit: pm8998-crit {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pm8998_lsid0: pmic@0 {
compatible = "qcom,pm8998", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8998_pon: pon@800 {
compatible = "qcom,pm8998-pon";
reg = <0x800>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pm8998_pwrkey: pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_POWER>;
};
pm8998_resin: resin {
compatible = "qcom,pm8941-resin";
interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
status = "disabled";
};
};
pm8998_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
io-channels = <&pm8998_adc ADC5_DIE_TEMP>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};
pm8998_coincell: charger@2800 {
compatible = "qcom,pm8998-coincell", "qcom,pm8941-coincell";
reg = <0x2800>;
status = "disabled";
};
pm8998_adc: adc@3100 {
compatible = "qcom,spmi-adc-rev2";
reg = <0x3100>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@6 {
reg = <ADC5_DIE_TEMP>;
label = "die_temp";
};
};
pm8998_adc_tm: adc-tm@3400 {
compatible = "qcom,spmi-adc-tm-hc";
reg = <0x3400>;
interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
#thermal-sensor-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>, <0x6100>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
};
pm8998_gpios: gpio@c000 {
compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pm8998_gpios 0 0 26>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pm8998_lsid1: pmic@1 {
compatible = "qcom,pm8998", "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
};
};
arch/arm/dts/pmi8994.dtsi
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// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
pmic@2 {
compatible = "qcom,pmi8994", "qcom,spmi-pmic";
reg = <0x2 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmi8994_gpios: gpio@c000 {
compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pmi8994_gpios 0 0 10>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pmi8994_mpps: mpps@a000 {
compatible = "qcom,pmi8994-mpp", "qcom,spmi-mpp";
reg = <0xa000>;
gpio-controller;
gpio-ranges = <&pmi8994_mpps 0 0 4>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pmic@3 {
compatible = "qcom,pmi8994", "qcom,spmi-pmic";
reg = <0x3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmi8994_lpg: pwm {
compatible = "qcom,pmi8994-lpg";
#address-cells = <1>;
#size-cells = <0>;
#pwm-cells = <2>;
status = "disabled";
};
pmi8994_spmi_regulators: regulators {
compatible = "qcom,pmi8994-regulators";
};
pmi8994_wled: wled@d800 {
compatible = "qcom,pmi8994-wled";
reg = <0xd800>, <0xd900>;
interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
<0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ovp", "short";
qcom,cabc;
qcom,external-pfet;
status = "disabled";
};
};
};
arch/arm/dts/pmi8998.dtsi
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// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
pmi8998_lsid0: pmic@2 {
compatible = "qcom,pmi8998", "qcom,spmi-pmic";
reg = <0x2 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmi8998_charger: charger@1000 {
compatible = "qcom,pmi8998-charger";
reg = <0x1000>;
interrupts = <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>,
<0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "usb-plugin",
"bat-ov",
"wdog-bark",
"usbin-icl-change";
io-channels = <&pmi8998_rradc 3>,
<&pmi8998_rradc 4>;
io-channel-names = "usbin_i", "usbin_v";
status = "disabled";
};
pmi8998_gpios: gpio@c000 {
compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pmi8998_gpios 0 0 14>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pmi8998_rradc: adc@4500 {
compatible = "qcom,pmi8998-rradc";
reg = <0x4500>;
#io-channel-cells = <1>;
};
};
pmi8998_lsid1: pmic@3 {
compatible = "qcom,pmi8998", "qcom,spmi-pmic";
reg = <0x3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
labibb {
compatible = "qcom,pmi8998-lab-ibb";
ibb: ibb {
interrupts = <0x3 0xdc 0x2 IRQ_TYPE_EDGE_RISING>,
<0x3 0xdc 0x0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sc-err", "ocp";
};
lab: lab {
interrupts = <0x3 0xde 0x1 IRQ_TYPE_EDGE_RISING>,
<0x3 0xde 0x0 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sc-err", "ocp";
};
};
pmi8998_lpg: pwm {
compatible = "qcom,pmi8998-lpg";
#address-cells = <1>;
#size-cells = <0>;
#pwm-cells = <2>;
status = "disabled";
};
pmi8998_flash: led-controller@d300 {
compatible = "qcom,pmi8998-flash-led", "qcom,spmi-flash-led";
reg = <0xd300>;
status = "disabled";
};
pmi8998_wled: leds@d800 {
compatible = "qcom,pmi8998-wled";
reg = <0xd800>, <0xd900>;
interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
<0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ovp", "short";
label = "backlight";
status = "disabled";
};
};
};
arch/arm/dts/pms405.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, Linaro Limited
*/
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/thermal/thermal.h>
/ {
thermal-zones {
pms405-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&pms405_temp>;
trips {
pms405_alert0: pms405-alert0 {
temperature = <105000>;
hysteresis = <2000>;
type = "passive";
};
pms405_crit: pms405-crit {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pms405_0: pms405@0 {
compatible = "qcom,pms405", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pms405_gpios: gpio@c000 {
compatible = "qcom,pms405-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pms405_gpios 0 0 12>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pon@800 {
compatible = "qcom,pms405-pon";
reg = <0x0800>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_POWER>;
};
};
pms405_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
io-channels = <&pms405_adc ADC5_DIE_TEMP>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};
pms405_adc: adc@3100 {
compatible = "qcom,pms405-adc", "qcom,spmi-adc-rev2";
reg = <0x3100>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
label = "ref_gnd";
};
channel@1 {
reg = <ADC5_1P25VREF>;
qcom,pre-scaling = <1 1>;
label = "vref_1p25";
};
channel@131 {
reg = <ADC5_VPH_PWR>;
qcom,pre-scaling = <1 3>;
label = "vph_pwr";
};
channel@6 {
reg = <ADC5_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "die_temp";
};
channel@77 {
reg = <ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "pa_therm1";
};
channel@79 {
reg = <ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "pa_therm3";
};
channel@76 {
reg = <ADC5_XO_THERM_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "xo_therm";
};
};
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>, <0x6100>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
};
};
pms405_1: pms405@1 {
compatible = "qcom,pms405", "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
pms405_spmi_regulators: regulators {
compatible = "qcom,pms405-regulators";
};
};
};
arch/arm/dts/qcs404-evb-4000-u-boot.dtsi
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// SPDX-License-Identifier: GPL-2.0+
#include <dt-bindings/gpio/gpio.h>
/delete-node/ &usb3_vbus_reg;
/delete-node/ &usb_vbus_boost_pin;
/ {
/* U-Boot uses different bindings for GPIO regulators, this
* one is required for USB
*/
usb3_vbus_reg: usb3_vbus_reg {
compatible = "regulator-gpio";
regulator-name = "usb3_vbus_reg";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-gpios = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
states = <0 0>, <5000000 1>;
};
};
&blsp1_uart2 {
/* This defines the bit clock divider which defines the baud rate.
* 0xFF is a divider of 16 for both the RX and TX lines. The QCS404
* clock driver in U-Boot hardcodes a 1843200Hz frequency for the
* UART core clock, and 1843200 / 16 = 115200.
*/
bit-rate = <0xFF>;
};
&gcc {
/* The clock framework in U-Boot "sort of" has the idea of linking an
* individual clock to a device via uclass_priv. However the qcom clock
* driver instead associates many clocks with a single device. This is
* usually fine but it seems that assigned-clocks wreak havoc on this
* and we wind up having a reference to the XO clock which is associated
* with the qcom_clk device...
* For now we'll just remove these properties, no other board has these.
*/
/delete-property/ assigned-clock-rates;
/delete-property/ assigned-clocks;
};
&usb3_dwc3 {
/* Make sure the VBUS supply is switched on */
vbus-supply = <&usb3_vbus_reg>;
};
arch/arm/dts/qcs404-evb-4000.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, Linaro Limited
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "qcs404-evb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QCS404 EVB 4000";
compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb",
"qcom,qcs404";
};
&ethernet {
status = "okay";
snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 10000>;
pinctrl-names = "default";
pinctrl-0 = <&ethernet_defaults>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy1: phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
device_type = "ethernet-phy";
reg = <0x4>;
};
};
};
&tlmm {
ethernet_defaults: ethernet-defaults-state {
int-pins {
pins = "gpio61";
function = "rgmii_int";
bias-disable;
drive-strength = <2>;
};
mdc-pins {
pins = "gpio76";
function = "rgmii_mdc";
bias-pull-up;
};
mdio-pins {
pins = "gpio75";
function = "rgmii_mdio";
bias-pull-up;
};
tx-pins {
pins = "gpio67", "gpio66", "gpio65", "gpio64";
function = "rgmii_tx";
bias-pull-up;
drive-strength = <16>;
};
rx-pins {
pins = "gpio73", "gpio72", "gpio71", "gpio70";
function = "rgmii_rx";
bias-disable;
drive-strength = <2>;
};
tx-ctl-pins {
pins = "gpio68";
function = "rgmii_ctl";
bias-pull-up;
drive-strength = <16>;
};
rx-ctl-pins {
pins = "gpio74";
function = "rgmii_ctl";
bias-disable;
drive-strength = <2>;
};
tx-ck-pins {
pins = "gpio63";
function = "rgmii_ck";
bias-pull-up;
drive-strength = <16>;
};
rx-ck-pins {
pins = "gpio69";
function = "rgmii_ck";
bias-disable;
drive-strength = <2>;
};
};
};
arch/arm/dts/qcs404-evb-uboot.dtsi
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// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot addition to handle QCS404 EVB pre-relocation devices
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
/ {
soc {
bootph-all;
pinctrl_north@1300000 {
bootph-all;
};
clock-controller@1800000 {
bootph-all;
};
serial@78b1000 {
bootph-all;
};
};
};
&pms405_gpios {
usb_vbus_boost_pin {
gpios = <&pms405_gpios 2 0>;
};
};
arch/arm/dts/qcs404-evb.dts
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// SPDX-License-Identifier: GPL-2.0+
/*
* Qualcomm QCS404 based evaluation board device tree source
*
* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
*/
/dts-v1/;
#include "skeleton64.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
/ {
model = "Qualcomm Technologies, Inc. QCS404 EVB";
compatible = "qcom,qcs404-evb", "qcom,qcs404";
#address-cells = <0x2>;
#size-cells = <0x2>;
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &debug_uart;
i2c0 = &blsp1_i2c0;
i2c1 = &blsp1_i2c1;
i2c2 = &blsp1_i2c2;
i2c3 = &blsp1_i2c3;
i2c4 = &blsp1_i2c4;
};
memory {
device_type = "memory";
reg = <0 0x80000000 0 0x40000000>;
};
soc {
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges = <0x0 0x0 0x0 0xffffffff>;
compatible = "simple-bus";
soc_gpios: pinctrl_north@1300000 {
compatible = "qcom,qcs404-pinctrl";
reg = <0x1300000 0x200000>;
gpio-controller;
gpio-count = <120>;
gpio-bank-name="soc";
#gpio-cells = <2>;
blsp1_uart2: uart {
pins = "GPIO_17", "GPIO_18";
function = "blsp_uart2";
};
blsp1_i2c0_default: blsp1-i2c0-default {
pins = "GPIO_32", "GPIO_33";
function = "blsp_i2c0";
};
blsp1_i2c1_default: blsp1-i2c1-default {
pins = "GPIO_24", "GPIO_25";
function = "blsp_i2c1";
};
blsp1_i2c2_default: blsp1-i2c2-default {
sda {
pins = "GPIO_19";
function = "blsp_i2c_sda_a2";
};
scl {
pins = "GPIO_20";
function = "blsp_i2c_scl_a2";
};
};
blsp1_i2c3_default: blsp1-i2c3-default {
pins = "GPIO_84", "GPIO_85";
function = "blsp_i2c3";
};
blsp1_i2c4_default: blsp1-i2c4-default {
pins = "GPIO_117", "GPIO_118";
function = "blsp_i2c4";
};
ethernet_defaults: ethernet-defaults {
int {
pins = "GPIO_61";
function = "rgmii_int";
bias-disable;
drive-strength = <2>;
};
mdc {
pins = "GPIO_76";
function = "rgmii_mdc";
bias-pull-up;
};
mdio {
pins = "GPIO_75";
function = "rgmii_mdio";
bias-pull-up;
};
tx {
pins = "GPIO_67", "GPIO_66", "GPIO_65", "GPIO_64";
function = "rgmii_tx";
bias-pull-up;
drive-strength = <16>;
};
rx {
pins = "GPIO_73", "GPIO_72", "GPIO_71", "GPIO_70";
function = "rgmii_rx";
bias-disable;
drive-strength = <2>;
};
tx-ctl {
pins = "GPIO_68";
function = "rgmii_ctl";
bias-pull-up;
drive-strength = <16>;
};
rx-ctl {
pins = "GPIO_74";
function = "rgmii_ctl";
bias-disable;
drive-strength = <2>;
};
tx-ck {
pins = "GPIO_63";
function = "rgmii_ck";
bias-pull-up;
drive-strength = <16>;
};
rx-ck {
pins = "GPIO_69";
function = "rgmii_ck";
bias-disable;
drive-strength = <2>;
};
};
};
blsp1_i2c0: i2c@78b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b5000 0x600>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c0_default>;
#address-cells = <1>;
#size-cells = <0>;
};
blsp1_i2c1: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b6000 0x600>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c1_default>;
#address-cells = <1>;
#size-cells = <0>;
};
blsp1_i2c2: i2c@78b7000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b7000 0x600>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c2_default>;
#address-cells = <1>;
#size-cells = <0>;
};
blsp1_i2c3: i2c@78b8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b8000 0x600>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c3_default>;
#address-cells = <1>;
#size-cells = <0>;
};
blsp1_i2c4: i2c@78b9000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b9000 0x600>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c4_default>;
#address-cells = <1>;
#size-cells = <0>;
};
gcc: clock-controller@1800000 {
compatible = "qcom,gcc-qcs404";
reg = <0x1800000 0x80000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <1>;
#reset-cells = <1>;
};
debug_uart: serial@78b1000 {
compatible = "qcom,msm-uartdm-v1.4";
reg = <0x78b1000 0x200>;
clock = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
bit-rate = <0xFF>;
pinctrl-names = "uart";
pinctrl-0 = <&blsp1_uart2>;
};
sdhci@7804000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x7804000 0x1000 0x7805000 0x1000>;
clock = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>;
bus-width = <0x8>;
index = <0x0>;
non-removable;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
};
usb3_phy: phy@78000 {
compatible = "qcom,usb-ss-28nm-phy";
#phy-cells = <0>;
reg = <0x78000 0x400>;
clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB3_PHY_PIPE_CLK>;
clock-names = "ahb", "pipe";
resets = <&gcc GCC_USB3_PHY_BCR>,
<&gcc GCC_USB3PHY_PHY_BCR>;
reset-names = "com", "phy";
};
usb2_phy_prim: phy@7a000 {
compatible = "qcom,usb-hs-28nm-femtophy";
#phy-cells = <0>;
reg = <0x7a000 0x200>;
clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB2A_PHY_SLEEP_CLK>;
clock-names = "ahb", "sleep";
resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
<&gcc GCC_USB2A_PHY_BCR>;
reset-names = "phy", "por";
};
usb2_phy_sec: phy@7c000 {
compatible = "qcom,usb-hs-28nm-femtophy";
#phy-cells = <0>;
reg = <0x7c000 0x200>;
clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB2A_PHY_SLEEP_CLK>;
clock-names = "ahb", "sleep";
resets = <&gcc GCC_QUSB2_PHY_BCR>,
<&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
reset-names = "phy", "por";
};
usb3: usb@7678800 {
compatible = "qcom,dwc3";
reg = <0x7678800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_USB30_MASTER_CLK>,
<&gcc GCC_SYS_NOC_USB3_CLK>,
<&gcc GCC_USB30_SLEEP_CLK>,
<&gcc GCC_USB30_MOCK_UTMI_CLK>;
clock-names = "core", "iface", "sleep", "mock_utmi";
dwc3@7580000 {
compatible = "snps,dwc3";
reg = <0x7580000 0xcd00>;
phys = <&usb2_phy_prim>, <&usb3_phy>;
phy-names = "usb2-phy", "usb3-phy";
dr_mode = "host";
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
};
};
usb2: usb@79b8800 {
compatible = "qcom,dwc3";
reg = <0x79b8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
<&gcc GCC_PCNOC_USB2_CLK>,
<&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
<&gcc GCC_USB20_MOCK_UTMI_CLK>;
clock-names = "core", "iface", "sleep", "mock_utmi";
dwc3@78c0000 {
compatible = "snps,dwc3";
reg = <0x78c0000 0xcc00>;
phys = <&usb2_phy_sec>;
phy-names = "usb2-phy";
dr_mode = "peripheral";
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
snps,usb3_lpm_capable;
maximum-speed = "high-speed";
};
};
ethernet: ethernet@7a80000 {
compatible = "qcom,qcs404-ethqos";
reg = <0x07a80000 0x10000>,
<0x07a96000 0x100>;
reg-names = "stmmaceth", "rgmii";
clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
clocks = <&gcc GCC_ETH_AXI_CLK>,
<&gcc GCC_ETH_SLAVE_AHB_CLK>,
<&gcc GCC_ETH_PTP_CLK>,
<&gcc GCC_ETH_RGMII_CLK>;
resets = <&gcc GCC_EMAC_BCR>;
reset-names = "emac";
snps,tso;
rx-fifo-depth = <4096>;
tx-fifo-depth = <4096>;
snps,reset-gpio = <&soc_gpios 60 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 10000>;
pinctrl-names = "default";
pinctrl-0 = <&ethernet_defaults>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
max-speed = <1000>;
mdio {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "snps,dwmac-mdio";
phy1: phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
device_type = "ethernet-phy";
reg = <0x3>;
};
};
};
spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x200f000 0x001000>,
<0x2400000 0x800000>,
<0x2c00000 0x800000>;
reg-names = "core", "chnls", "obsrvr";
#address-cells = <0x1>;
#size-cells = <0x1>;
pms405_0: pms405@0 {
compatible = "qcom,spmi-pmic";
reg = <0x0 0x1>;
#address-cells = <0x1>;
#size-cells = <0x1>;
pms405_gpios: pms405_gpios@c000 {
compatible = "qcom,pms405-gpio";
reg = <0xc000 0x400>;
gpio-controller;
gpio-ranges = <&pms405_gpios 0 0 12>;
#gpio-cells = <2>;
};
};
};
};
};
#include "qcs404-evb-uboot.dtsi"
arch/arm/dts/qcs404-evb.dtsi
+389
View File
@@ -0,0 +1,389 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, Linaro Limited
*/
#include <dt-bindings/gpio/gpio.h>
#include "qcs404.dtsi"
#include "pms405.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
aliases {
serial0 = &blsp1_uart2;
serial1 = &blsp1_uart3;
};
chosen {
stdout-path = "serial0";
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-always-on;
regulator-boot-on;
};
vdd_ch0_3p3:
vdd_esmps3_3p3: vdd-esmps3-3p3-regulator {
compatible = "regulator-fixed";
regulator-name = "eSMPS3_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
usb3_vbus_reg: regulator-usb3-vbus {
compatible = "regulator-fixed";
regulator-name = "VBUS_BOOST_5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_vbus_boost_pin>;
vin-supply = <&vph_pwr>;
enable-active-high;
/* TODO: Drop this when introducing role switching */
regulator-always-on;
};
};
&blsp1_uart3 {
status = "okay";
bluetooth {
compatible = "qcom,wcn3990-bt";
vddio-supply = <&vreg_l6_1p8>;
vddxo-supply = <&vreg_l5_1p8>;
vddrf-supply = <&vreg_l1_1p3>;
vddch0-supply = <&vdd_ch0_3p3>;
local-bd-address = [ 02 00 00 00 5a ad ];
max-speed = <3200000>;
};
};
&blsp1_dma {
qcom,controlled-remotely;
};
&blsp2_dma {
qcom,controlled-remotely;
};
&gcc {
protected-clocks = <GCC_BIMC_CDSP_CLK>,
<GCC_CDSP_CFG_AHB_CLK>,
<GCC_CDSP_BIMC_CLK_SRC>,
<GCC_CDSP_TBU_CLK>,
<141>, /* GCC_WCSS_Q6_AHB_CLK */
<142>; /* GCC_WCSS_Q6_AXIM_CLK */
};
&pms405_spmi_regulators {
vdd_s3-supply = <&vph_pwr>;
pms405_s3: s3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd_apc";
regulator-initial-mode = <1>;
regulator-min-microvolt = <1048000>;
regulator-max-microvolt = <1384000>;
};
};
&pcie {
status = "okay";
perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&perst_state>;
};
&pcie_phy {
status = "okay";
vdda-vp-supply = <&vreg_l3_1p05>;
vdda-vph-supply = <&vreg_l5_1p8>;
};
&remoteproc_adsp {
status = "okay";
};
&remoteproc_cdsp {
status = "okay";
};
&remoteproc_wcss {
status = "okay";
};
&rpm_requests {
regulators {
compatible = "qcom,rpm-pms405-regulators";
vdd_s1-supply = <&vph_pwr>;
vdd_s2-supply = <&vph_pwr>;
vdd_s3-supply = <&vph_pwr>;
vdd_s4-supply = <&vph_pwr>;
vdd_s5-supply = <&vph_pwr>;
vdd_l1_l2-supply = <&vreg_s5_1p35>;
vdd_l3_l8-supply = <&vreg_s5_1p35>;
vdd_l4-supply = <&vreg_s5_1p35>;
vdd_l5_l6-supply = <&vreg_s4_1p8>;
vdd_l7-supply = <&vph_pwr>;
vdd_l9-supply = <&vreg_s5_1p35>;
vdd_l10_l11_l12_l13-supply = <&vph_pwr>;
vreg_s4_1p8: s4 {
regulator-min-microvolt = <1728000>;
regulator-max-microvolt = <1920000>;
};
vreg_s5_1p35: s5 {
regulator-min-microvolt = <1352000>;
regulator-max-microvolt = <1352000>;
};
vreg_l1_1p3: l1 {
regulator-min-microvolt = <1240000>;
regulator-max-microvolt = <1352000>;
};
vreg_l2_1p275: l2 {
regulator-min-microvolt = <1048000>;
regulator-max-microvolt = <1280000>;
};
vreg_l3_1p05: l3 {
regulator-min-microvolt = <1048000>;
regulator-max-microvolt = <1160000>;
};
vreg_l4_1p2: l4 {
regulator-min-microvolt = <1144000>;
regulator-max-microvolt = <1256000>;
};
vreg_l5_1p8: l5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l6_1p8: l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vreg_l7_1p8: l7 {
regulator-min-microvolt = <1616000>;
regulator-max-microvolt = <3000000>;
};
vreg_l8_1p2: l8 {
regulator-min-microvolt = <1136000>;
regulator-max-microvolt = <1352000>;
};
vreg_l10_3p3: l10 {
regulator-min-microvolt = <2936000>;
regulator-max-microvolt = <3088000>;
};
vreg_l11_sdc2: l11 {
regulator-min-microvolt = <2696000>;
regulator-max-microvolt = <3304000>;
};
vreg_l12_3p3: l12 {
regulator-min-microvolt = <3050000>;
regulator-max-microvolt = <3300000>;
};
vreg_l13_3p3: l13 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
};
};
};
&sdcc1 {
status = "okay";
supports-cqe;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
non-removable;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_on>;
pinctrl-1 = <&sdc1_off>;
};
&tlmm {
perst_state: perst-state {
pins = "gpio43";
function = "gpio";
drive-strength = <2>;
bias-disable;
output-low;
};
sdc1_on: sdc1-on-state {
clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
sdc1_off: sdc1-off-state {
clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
usb3_id_pin: usb3-id-state {
pins = "gpio116";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
&pms405_gpios {
usb_vbus_boost_pin: usb-vbus-boost-state {
pinconf {
pins = "gpio3";
function = PMIC_GPIO_FUNC_NORMAL;
output-low;
power-source = <1>;
};
};
usb3_vbus_pin: usb3-vbus-state {
pinconf {
pins = "gpio12";
function = PMIC_GPIO_FUNC_NORMAL;
input-enable;
bias-pull-down;
power-source = <1>;
};
};
};
&usb2 {
status = "okay";
};
&usb2_phy_sec {
vdd-supply = <&vreg_l4_1p2>;
vdda1p8-supply = <&vreg_l5_1p8>;
vdda3p3-supply = <&vreg_l12_3p3>;
status = "okay";
};
&usb3 {
status = "okay";
};
&usb3_dwc3 {
dr_mode = "host";
};
&usb2_phy_prim {
vdd-supply = <&vreg_l4_1p2>;
vdda1p8-supply = <&vreg_l5_1p8>;
vdda3p3-supply = <&vreg_l12_3p3>;
status = "okay";
};
&usb3_phy {
vdd-supply = <&vreg_l3_1p05>;
vdda1p8-supply = <&vreg_l5_1p8>;
status = "okay";
};
&wifi {
status = "okay";
vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>;
vdd-1.8-xo-supply = <&vreg_l5_1p8>;
vdd-1.3-rfa-supply = <&vreg_l1_1p3>;
};
/* PINCTRL - additions to nodes defined in qcs404.dtsi */
&blsp1_uart2_default {
rx-pins {
drive-strength = <2>;
bias-disable;
};
tx-pins {
drive-strength = <2>;
bias-disable;
};
};
&blsp1_uart3_default {
cts-pins {
bias-disable;
};
rts-tx-pins {
drive-strength = <2>;
bias-disable;
};
rx-pins {
bias-pull-up;
};
};
arch/arm/dts/qcs404.dtsi
+1829
View File
File diff suppressed because it is too large Load Diff
arch/arm/dts/rk3328-evb-u-boot.dtsi
+4
View File
@@ -44,3 +44,7 @@
/* Integrated PHY unsupported by U-Boot */
status = "broken"
};
&vcc_sd {
bootph-pre-ram;
};
arch/arm/dts/rk3328-evb.dts
+1
View File
@@ -11,6 +11,7 @@
compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
aliases {
ethernet0 = &gmac2phy;
mmc0 = &sdmmc;
mmc1 = &sdio;
mmc2 = &emmc;
arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
-6
View File
@@ -1,9 +1,3 @@
// SPDX-License-Identifier: GPL-2.0-or-later
#include "rk3328-nanopi-r2c-u-boot.dtsi"
/ {
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
};
};

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