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arm: dts: layerscape: drop leading zeros from unit addresses

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Fix many dtc warning for the Layerscape device trees with W=1.
Without this fix, it emits over 30 unit_address_format warnings.

No functional change.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Vincent Jardin
2026-08-11 15:47:52 +08:00
committed by Peng Fan
parent 607d45d1e3
commit d13ee7acaf
5 changed files with 12 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
+4 -4
View File
@@ -25,28 +25,28 @@
status = "okay";
managed = "in-band-status";
phy-mode = "qsgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>;
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@8}>;
};
&mscc_felix_port1 {
status = "okay";
managed = "in-band-status";
phy-mode = "qsgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>;
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@9}>;
};
&mscc_felix_port2 {
status = "okay";
managed = "in-band-status";
phy-mode = "qsgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>;
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@a}>;
};
&mscc_felix_port3 {
status = "okay";
managed = "in-band-status";
phy-mode = "qsgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>;
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@b}>;
};
&mscc_felix_port4 {
arch/arm/dts/fsl-ls1028a-qds.dtsi
+1 -1
View File
@@ -147,7 +147,7 @@
mdio-parent-bus = <&enetc_mdio_pf3>;
/* on-board MDIO with a single RGMII PHY */
mdio@00 {
mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00>;
arch/arm/dts/fsl-ls1088a-qds.dtsi
+1 -1
View File
@@ -41,7 +41,7 @@
mux-reg-masks = <0x54 0xe0>; // reg 0x54, bits 7:5
mdio-parent-bus = <&emdio1>;
mdio@00 {
mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00>;
arch/arm/dts/fsl-lx2160a-qds.dtsi
+2 -2
View File
@@ -161,7 +161,7 @@
mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3
mdio-parent-bus = <&emdio1>;
mdio@00 {
mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00>;
@@ -170,7 +170,7 @@
reg = <0x1>;
};
};
mdio@08 {
mdio@8 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40>;
arch/arm/dts/fsl-sch-28021.dtsi
+4 -4
View File
@@ -12,18 +12,18 @@
* PHY addresses are 0x08 - 0x0b.
* On the card the first port is the top port (farthest from PEX connector).
*/
phy@08 {
phy@8 {
reg = <0x08>;
};
phy@09 {
phy@9 {
reg = <0x09>;
};
phy@0a {
phy@a {
reg = <0x0a>;
};
phy@0b {
phy@b {
reg = <0x0b>;
};