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arm: dts: renesas: Clean up RPC DT nodes

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Remove duplicate properties which are present both in arch/arm/dts/
and upstream dts/upstream/src/arm64/renesas/ in favor of those in
upstream DTs. Since those are duplicates, this causes no functional
change. Remove unused num-cs and bank-width DT properties.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut
2026-05-05 12:53:53 +02:00
parent 57460fde4b
commit d0abd8b4c5
28 changed files with 0 additions and 240 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/dts/r7s72100-gr-peach-u-boot.dtsi
-1
View File
@@ -49,7 +49,6 @@
compatible = "renesas,r7s72100-rpc-if";
reg = <0x3fefa000 0x100>, <0x18000000 0x08000000>;
bank-width = <2>;
num-cs = <1>;
status = "okay";
spi-max-frequency = <50000000>;
#address-cells = <1>;
arch/arm/dts/r8a774c0-ek874-u-boot.dtsi
-1
View File
@@ -14,7 +14,6 @@
};
&rpc {
num-cs = <1>;
status = "okay";
spi-max-frequency = <50000000>;
#address-cells = <1>;
arch/arm/dts/r8a774c0-u-boot.dtsi
-12
View File
@@ -6,18 +6,6 @@
*
*/
/ {
soc {
rpc: spi@ee200000 {
compatible = "renesas,r8a774c0-rpc-if", "renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
clocks = <&cpg CPG_MOD 917>;
bank-width = <2>;
status = "disabled";
};
};
};
/delete-node/ &can0;
/delete-node/ &can1;
/delete-node/ &canfd;
arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi
-5
View File
@@ -23,11 +23,6 @@
};
};
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "disabled";
};
&sdhi0 {
sd-uhs-sdr12;
sd-uhs-sdr25;
arch/arm/dts/r8a77951-u-boot.dtsi
-12
View File
@@ -5,18 +5,6 @@
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/
/ {
soc {
rpc: spi@ee200000 {
compatible = "renesas,r8a7795-rpc-if", "renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
clocks = <&cpg CPG_MOD 917>;
bank-width = <2>;
status = "disabled";
};
};
};
/delete-node/ &ak4613;
/delete-node/ &audma0;
/delete-node/ &audma1;
arch/arm/dts/r8a77951-ulcb-u-boot.dtsi
-5
View File
@@ -32,11 +32,6 @@
};
};
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "disabled";
};
&sdhi0 {
sd-uhs-sdr12;
sd-uhs-sdr25;
arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi
-5
View File
@@ -23,11 +23,6 @@
};
};
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "disabled";
};
&sdhi0 {
sd-uhs-sdr12;
sd-uhs-sdr25;
arch/arm/dts/r8a77960-u-boot.dtsi
-12
View File
@@ -5,18 +5,6 @@
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/
/ {
soc {
rpc: spi@ee200000 {
compatible = "renesas,r8a7796-rpc-if", "renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
clocks = <&cpg CPG_MOD 917>;
bank-width = <2>;
status = "disabled";
};
};
};
/delete-node/ &ak4613;
/delete-node/ &audma0;
/delete-node/ &audma1;
arch/arm/dts/r8a77960-ulcb-u-boot.dtsi
-5
View File
@@ -32,11 +32,6 @@
};
};
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "disabled";
};
&sdhi0 {
sd-uhs-sdr12;
sd-uhs-sdr25;
arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi
-5
View File
@@ -23,11 +23,6 @@
};
};
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "disabled";
};
&sdhi0 {
sd-uhs-sdr12;
sd-uhs-sdr25;
arch/arm/dts/r8a77965-u-boot.dtsi
-12
View File
@@ -5,18 +5,6 @@
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/
/ {
soc {
rpc: spi@ee200000 {
compatible = "renesas,r8a77965-rpc-if", "renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
clocks = <&cpg CPG_MOD 917>;
bank-width = <2>;
status = "disabled";
};
};
};
/delete-node/ &ak4613;
/delete-node/ &audma0;
/delete-node/ &audma1;
arch/arm/dts/r8a77965-ulcb-u-boot.dtsi
-5
View File
@@ -32,11 +32,6 @@
};
};
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "disabled";
};
&sdhi0 {
sd-uhs-sdr12;
sd-uhs-sdr25;
arch/arm/dts/r8a77970-eagle-u-boot.dtsi
-3
View File
@@ -5,7 +5,6 @@
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/
#include "r8a77970-u-boot.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
@@ -34,9 +33,7 @@
};
&rpc {
num-cs = <1>;
status = "okay";
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
arch/arm/dts/r8a77970-u-boot.dtsi
-18
View File
@@ -1,18 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on R-Car R8A77970 SoC
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/
/ {
soc {
rpc: spi@ee200000 {
compatible = "renesas,r8a77970-rpc-if", "renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
clocks = <&cpg CPG_MOD 917>;
bank-width = <2>;
status = "disabled";
};
};
};
arch/arm/dts/r8a77970-v3msk-u-boot.dtsi
-3
View File
@@ -5,7 +5,6 @@
* Copyright (C) 2019 Cogent Embedded, Inc.
*/
#include "r8a77970-u-boot.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
@@ -45,9 +44,7 @@
};
&rpc {
num-cs = <1>;
status = "okay";
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
arch/arm/dts/r8a77980-condor-u-boot.dtsi
-4
View File
@@ -5,8 +5,6 @@
* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
*/
#include "r8a77980-u-boot.dtsi"
/ {
aliases {
spi0 = &rpc;
@@ -28,9 +26,7 @@
};
&rpc {
num-cs = <1>;
status = "okay";
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
arch/arm/dts/r8a77980-u-boot.dtsi
-18
View File
@@ -1,18 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on R-Car R8A77980 SoC
*
* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
*/
/ {
soc {
rpc: spi@ee200000 {
compatible = "renesas,r8a77980-rpc-if", "renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
clocks = <&cpg CPG_MOD 917>;
bank-width = <2>;
status = "disabled";
};
};
};
arch/arm/dts/r8a77980-v3hsk-u-boot.dtsi
-4
View File
@@ -5,8 +5,6 @@
* Copyright (C) 2019 Cogent Embedded, Inc.
*/
#include "r8a77980-u-boot.dtsi"
/ {
aliases {
spi0 = &rpc;
@@ -14,9 +12,7 @@
};
&rpc {
num-cs = <1>;
status = "okay";
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
arch/arm/dts/r8a77990-ebisu-u-boot.dtsi
-7
View File
@@ -5,8 +5,6 @@
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/
#include "r8a77990-u-boot.dtsi"
/ {
sysinfo {
compatible = "renesas,rcar-sysinfo";
@@ -33,11 +31,6 @@
};
};
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "disabled";
};
&sdhi0 {
sd-uhs-sdr12;
sd-uhs-sdr25;
arch/arm/dts/r8a77990-u-boot.dtsi
-18
View File
@@ -1,18 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on R-Car R8A77990 SoC
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/
/ {
soc {
rpc: spi@ee200000 {
compatible = "renesas,r8a77990-rpc-if", "renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
clocks = <&cpg CPG_MOD 917>;
bank-width = <2>;
status = "disabled";
};
};
};
arch/arm/dts/r8a77995-draak-u-boot.dtsi
-7
View File
@@ -5,8 +5,6 @@
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/
#include "r8a77995-u-boot.dtsi"
/ {
sysinfo {
compatible = "renesas,rcar-sysinfo";
@@ -22,8 +20,3 @@
bootph-all;
};
};
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "disabled";
};
arch/arm/dts/r8a77995-u-boot.dtsi
-18
View File
@@ -1,18 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on R-Car R8A77995 SoC
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/
/ {
soc {
rpc: spi@ee200000 {
compatible = "renesas,r8a77995-rpc-if", "renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
clocks = <&cpg CPG_MOD 917>;
bank-width = <2>;
status = "disabled";
};
};
};
arch/arm/dts/r8a779a0-falcon-u-boot.dtsi
-4
View File
@@ -5,8 +5,6 @@
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a779a0-u-boot.dtsi"
/ {
aliases {
spi0 = &rpc;
@@ -16,8 +14,6 @@
&rpc {
#address-cells = <1>;
#size-cells = <0>;
num-cs = <1>;
spi-max-frequency = <50000000>;
status = "okay";
flash@0 {
arch/arm/dts/r8a779a0-u-boot.dtsi
-19
View File
@@ -1,19 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on R-Car R8A779A0 SoC
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/ {
soc {
rpc: spi@ee200000 {
compatible = "renesas,r8a779a0-rpc-if", "renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>;
clocks = <&cpg CPG_MOD 629>;
bank-width = <2>;
num-cs = <1>;
status = "disabled";
};
};
};
arch/arm/dts/r8a779g0-u-boot.dtsi
-5
View File
@@ -93,11 +93,6 @@
bootph-all;
};
&rpc {
bank-width = <2>;
num-cs = <1>;
};
&soc {
apmu@e6170000 { /* Remoteproc */
compatible = "renesas,r8a779g0-cr52";
arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi
-20
View File
@@ -5,36 +5,16 @@
* Copyright (C) 2025 Renesas Electronics Corp.
*/
#include "r8a779h0-u-boot.dtsi"
/ {
aliases {
spi0 = &rpc;
};
};
&pfc {
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <40000000>;
status = "disabled";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
arch/arm/dts/r8a779h0-u-boot.dtsi
-11
View File
@@ -1,11 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on R-Car R8A779H0 SoC
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
&rpc {
bank-width = <2>;
num-cs = <1>;
};
arch/arm/dts/rz-g2-beacon-u-boot.dtsi
-1
View File
@@ -47,7 +47,6 @@
&rpc {
pinctrl-0 = <&qspi_pins>;
pinctrl-names = "default";
num-cs = <1>;
spi-max-frequency = <40000000>;
#address-cells = <1>;
#size-cells = <0>;