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board: tqma6: use runtime SoC detection in enet setup

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Select the appropriate iomux settings based on the CPU type
during ethernet configuration.

Signed-off-by: Paul Gerber <Paul.Gerber@ew.tq-group.com>
Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com>
This commit is contained in:
Max Merchel
2026-07-27 13:05:07 -03:00
committed by Fabio Estevam
parent 2416b2a21c
commit c6bf5b6a14
1 changed files with 15 additions and 18 deletions
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board/tq/tqma6/tqma6_mba6.c
+15 -18
View File
@@ -33,21 +33,11 @@
#include "../common/tq_bb.h"
#if defined(CONFIG_TQMA6Q)
#define TQMA6Q_IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790
#define TQMA6Q_IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac
#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790
#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac
#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768
#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788
#else
#error "need to select module"
#endif
#define TQMA6DL_IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768
#define TQMA6DL_IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788
/* disable on die termination for RGMII */
#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE 0x00000000
@@ -63,10 +53,17 @@ static void mba6_setup_iomuxc_enet(void)
/* clear gpr1[ENET_CLK_SEL] for externel clock */
clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
__raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE,
(void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
__raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
(void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
if (is_mx6sdl()) {
__raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE,
(void *)TQMA6DL_IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
__raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
(void *)TQMA6DL_IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
} else if (is_mx6dq()) {
__raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE,
(void *)TQMA6Q_IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
__raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
(void *)TQMA6Q_IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
}
}
int board_mmc_get_env_dev(int devno)