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armv8: enable HAFDBS for other ELx when FEAT_HAFDBS is present

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u-boot could be run at EL1/EL2/EL3. so we set it as same as EL1 does.
otherwise it will hang when enable mmu, that is what we encounter
in our SOC.

Signed-off-by: meitao <meitaogao@asrmicro.com>
[ Paul: pick from the Android tree. Rebase to the upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: https://android.googlesource.com/platform/external/u-boot/+/3bf38943aeab4700c2319bff2a1477d99c6afd2f
This commit is contained in:
meitao
2023-04-25 15:31:27 -04:00
committed by Tom Rini
parent 836b8d4b20
commit c1da6fdb5c
2 changed files with 13 additions and 3 deletions
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arch/arm/cpu/armv8/cache_v8.c
+5 -1
View File
@@ -94,11 +94,15 @@ u64 get_tcr(u64 *pips, u64 *pva_bits)
if (el == 1) {
tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
if (gd->arch.has_hafdbs)
tcr |= TCR_HA | TCR_HD;
tcr |= TCR_EL1_HA | TCR_EL1_HD;
} else if (el == 2) {
tcr = TCR_EL2_RSVD | (ips << 16);
if (gd->arch.has_hafdbs)
tcr |= TCR_EL2_HA | TCR_EL2_HD;
} else {
tcr = TCR_EL3_RSVD | (ips << 16);
if (gd->arch.has_hafdbs)
tcr |= TCR_EL3_HA | TCR_EL3_HD;
}
/* PTWs cacheable, inner/outer WBWA and inner shareable */
arch/arm/include/asm/armv8/mmu.h
+8 -2
View File
@@ -102,8 +102,14 @@
#define TCR_TG0_16K (2 << 14)
#define TCR_EPD1_DISABLE (1 << 23)
#define TCR_HA BIT(39)
#define TCR_HD BIT(40)
#define TCR_EL1_HA BIT(39)
#define TCR_EL1_HD BIT(40)
#define TCR_EL2_HA BIT(21)
#define TCR_EL2_HD BIT(22)
#define TCR_EL3_HA BIT(21)
#define TCR_EL3_HD BIT(22)
#define TCR_EL1_RSVD (1U << 31)
#define TCR_EL2_RSVD (1U << 31 | 1 << 23)