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andes: cpu: Enable memboost feature

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Andes CPU has memboost feature including prefetch,
write-around and non-blocking load. Enable them by default.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
This commit is contained in:
Leo Yu-Chi Liang
2023-12-27 17:29:07 +08:00
parent b0469041c0
commit bf12bb99d8
2 changed files with 14 additions and 1 deletions
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arch/riscv/cpu/andesv5/cpu.c
+8 -1
View File
@@ -31,8 +31,11 @@ void harts_early_init(void)
/* Enable I/D-cache in SPL */
if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL);
mcache_ctl_val |= MCACHE_CTL_CCTL_SUEN;
mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \
MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \
MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN);
if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
mcache_ctl_val |= MCACHE_CTL_IC_EN;
@@ -52,5 +55,9 @@ void harts_early_init(void)
while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
}
}
mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN;
csr_write(CSR_MMISC_CTL, mmisc_ctl_val);
}
}
arch/riscv/include/asm/arch-andes/csr.h
+6
View File
@@ -19,9 +19,15 @@
#define MCACHE_CTL_IC_EN BIT(0)
#define MCACHE_CTL_DC_EN BIT(1)
#define MCACHE_CTL_CCTL_SUEN BIT(8)
#define MCACHE_CTL_IC_PREFETCH_EN BIT(9)
#define MCACHE_CTL_DC_PREFETCH_EN BIT(10)
#define MCACHE_CTL_DC_WAROUND_EN BIT(13)
#define MCACHE_CTL_L2C_WAROUND_EN BIT(15)
#define MCACHE_CTL_DC_COHEN BIT(19)
#define MCACHE_CTL_DC_COHSTA BIT(20)
/* mmisc_ctl register */
#define MMISC_CTL_NON_BLOCKING_EN BIT(8)
#define CCTL_L1D_WBINVAL_ALL 6