board: mediatek: add MT7988 reference boards
This patch adds general board files based on MT7988 SoCs. MT7988 uses one mmc controller for booting from both SD and eMMC, and the pins of mmc controller booting from SD are also shared with one of spi controllers. So two configs are need for these boot types: 1. mt7988_rfb_defconfig - SPI-NOR, SPI-NAND and eMMC 2. mt7988_sd_rfb_defconfig - SPI-NAND and SD Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
Weijie Gao
Tom Rini
@@ -1341,6 +1341,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt7986b-sd-rfb.dtb \
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mt7986a-emmc-rfb.dtb \
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mt7986b-emmc-rfb.dtb \
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mt7988-rfb.dtb \
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mt7988-sd-rfb.dtb \
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mt8183-pumpkin.dtb \
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mt8512-bm1-emmc.dtb \
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mt8516-pumpkin.dtb \
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@@ -0,0 +1,182 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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/dts-v1/;
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#include "mt7988.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "mt7988-rfb";
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compatible = "mediatek,mt7988-rfb";
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chosen {
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stdout-path = &uart0;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0x10000000>;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&uart0 {
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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status = "okay";
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};
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ð {
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status = "okay";
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mediatek,gmac-id = <0>;
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phy-mode = "usxgmii";
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mediatek,switch = "mt7988";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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&pinctrl {
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i2c1_pins: i2c1-pins {
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mux {
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function = "i2c";
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groups = "i2c1_0";
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};
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};
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pwm_pins: pwm-pins {
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mux {
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function = "pwm";
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groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
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"pwm5", "pwm6", "pwm7";
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};
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};
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spi0_pins: spi0-pins {
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mux {
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function = "spi";
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groups = "spi0", "spi0_wp_hold";
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};
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};
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spi2_pins: spi2-pins {
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mux {
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function = "spi";
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groups = "spi2", "spi2_wp_hold";
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};
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};
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mmc0_pins_default: mmc0default {
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mux {
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function = "flash";
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groups = "emmc_51";
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};
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conf-cmd-dat {
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pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
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"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
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"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
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input-enable;
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};
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conf-clk {
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pins = "EMMC_CK";
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};
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conf-dsl {
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pins = "EMMC_DSL";
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};
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conf-rst {
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pins = "EMMC_RSTB";
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};
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};
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};
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&pwm {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm_pins>;
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status = "okay";
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_pins>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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must_tx;
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enhance_timing;
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dma_ext;
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ipm_design;
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support_quad;
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tick_dly = <2>;
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sample_sel = <0>;
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spi_nand@0 {
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compatible = "spi-nand";
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reg = <0>;
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spi-max-frequency = <52000000>;
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};
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};
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&spi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi2_pins>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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must_tx;
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enhance_timing;
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dma_ext;
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ipm_design;
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support_quad;
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tick_dly = <2>;
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sample_sel = <0>;
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spi_nor@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <52000000>;
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};
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};
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins_default>;
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max-frequency = <52000000>;
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bus-width = <8>;
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cap-mmc-highspeed;
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cap-mmc-hw-reset;
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_1p8v>;
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non-removable;
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status = "okay";
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};
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@@ -0,0 +1,134 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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/dts-v1/;
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#include "mt7988.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "mt7988-rfb";
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compatible = "mediatek,mt7988-rfb", "mediatek,mt7988-sd-rfb";
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chosen {
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stdout-path = &uart0;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0x10000000>;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&uart0 {
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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status = "okay";
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};
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ð {
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status = "okay";
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mediatek,gmac-id = <0>;
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phy-mode = "usxgmii";
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mediatek,switch = "mt7988";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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&pinctrl {
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i2c1_pins: i2c1-pins {
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mux {
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function = "i2c";
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groups = "i2c1_0";
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};
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};
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pwm_pins: pwm-pins {
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mux {
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function = "pwm";
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groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
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"pwm5", "pwm6", "pwm7";
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};
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};
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spi0_pins: spi0-pins {
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mux {
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function = "spi";
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groups = "spi0", "spi0_wp_hold";
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};
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};
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mmc1_pins_default: mmc1default {
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mux {
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function = "flash";
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groups = "emmc_45";
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};
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conf-cmd-dat {
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pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI",
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"SPI2_CLK", "SPI2_HOLD";
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input-enable;
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};
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conf-clk {
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pins = "SPI2_WP";
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};
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};
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};
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&pwm {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm_pins>;
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status = "okay";
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_pins>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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must_tx;
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enhance_timing;
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dma_ext;
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ipm_design;
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support_quad;
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tick_dly = <2>;
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sample_sel = <0>;
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spi_nand@0 {
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compatible = "spi-nand";
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reg = <0>;
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spi-max-frequency = <52000000>;
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};
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};
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins_default>;
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max-frequency = <52000000>;
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bus-width = <4>;
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cap-sd-highspeed;
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_3p3v>;
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status = "okay";
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};
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@@ -0,0 +1,7 @@
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MT7988
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M: Sam Shih <sam.shih@mediatek.com>
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S: Maintained
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F: board/mediatek/mt7988
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F: include/configs/mt7988.h
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F: configs/mt7988_rfb_defconfig
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F: configs/mt7988_sd_rfb_defconfig
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@@ -0,0 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-y += mt7988_rfb.o
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@@ -0,0 +1,10 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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int board_init(void)
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{
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return 0;
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}
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@@ -0,0 +1,83 @@
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CONFIG_ARM=y
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CONFIG_SYS_HAS_NONCACHED_MEMORY=y
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CONFIG_POSITION_INDEPENDENT=y
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CONFIG_ARCH_MEDIATEK=y
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CONFIG_TEXT_BASE=0x41e00000
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CONFIG_SYS_MALLOC_F_LEN=0x4000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb"
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CONFIG_SYS_PROMPT="MT7988> "
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CONFIG_TARGET_MT7988=y
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CONFIG_DEBUG_UART_BASE=0x11000000
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CONFIG_DEBUG_UART_CLOCK=40000000
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CONFIG_SYS_LOAD_ADDR=0x46000000
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CONFIG_DEBUG_UART=y
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# CONFIG_AUTOBOOT is not set
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CONFIG_DEFAULT_FDT_FILE="mt7988-rfb"
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CONFIG_LOGLEVEL=7
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CONFIG_LOG=y
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CONFIG_SYS_CBSIZE=512
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CONFIG_SYS_PBSIZE=1049
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# CONFIG_BOOTM_NETBSD is not set
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# CONFIG_BOOTM_PLAN9 is not set
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# CONFIG_BOOTM_RTEMS is not set
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# CONFIG_BOOTM_VXWORKS is not set
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# CONFIG_CMD_ELF is not set
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CONFIG_CMD_CLK=y
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CONFIG_CMD_DM=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_PWM=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_MTD=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_SMC=y
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CONFIG_DOS_PARTITION=y
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CONFIG_EFI_PARTITION=y
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CONFIG_PARTITION_TYPE_GUID=y
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CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_USE_IPADDR=y
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CONFIG_IPADDR="192.168.1.1"
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CONFIG_USE_NETMASK=y
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CONFIG_NETMASK="255.255.255.0"
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CONFIG_USE_SERVERIP=y
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CONFIG_SERVERIP="192.168.1.2"
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CONFIG_PROT_TCP=y
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CONFIG_REGMAP=y
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CONFIG_SYSCON=y
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CONFIG_CLK=y
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CONFIG_MMC_HS200_SUPPORT=y
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CONFIG_MMC_MTK=y
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CONFIG_MTD=y
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CONFIG_DM_MTD=y
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CONFIG_MTD_SPI_NAND=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_SFDP_SUPPORT=y
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_ISSI=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_SPI_FLASH_XMC=y
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CONFIG_SPI_FLASH_XTX=y
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CONFIG_SPI_FLASH_MTD=y
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CONFIG_PHY_FIXED=y
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CONFIG_MEDIATEK_ETH=y
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CONFIG_PINCTRL=y
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CONFIG_PINCONF=y
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CONFIG_PINCTRL_MT7988=y
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CONFIG_POWER_DOMAIN=y
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CONFIG_MTK_POWER_DOMAIN=y
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CONFIG_DM_PWM=y
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CONFIG_PWM_MTK=y
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CONFIG_RAM=y
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CONFIG_DM_SERIAL=y
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CONFIG_MTK_SERIAL=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_MTK_SPIM=y
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CONFIG_LZO=y
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CONFIG_HEXDUMP=y
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# CONFIG_EFI_LOADER is not set
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@@ -0,0 +1,71 @@
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CONFIG_ARM=y
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CONFIG_SYS_HAS_NONCACHED_MEMORY=y
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CONFIG_POSITION_INDEPENDENT=y
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CONFIG_ARCH_MEDIATEK=y
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CONFIG_TEXT_BASE=0x41e00000
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CONFIG_SYS_MALLOC_F_LEN=0x4000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_DEFAULT_DEVICE_TREE="mt7988-sd-rfb"
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CONFIG_SYS_PROMPT="MT7988> "
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CONFIG_TARGET_MT7988=y
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CONFIG_DEBUG_UART_BASE=0x11000000
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CONFIG_DEBUG_UART_CLOCK=40000000
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CONFIG_SYS_LOAD_ADDR=0x46000000
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CONFIG_DEBUG_UART=y
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# CONFIG_AUTOBOOT is not set
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CONFIG_DEFAULT_FDT_FILE="mt7988-sd-rfb"
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CONFIG_LOGLEVEL=7
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CONFIG_LOG=y
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CONFIG_SYS_CBSIZE=512
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CONFIG_SYS_PBSIZE=1049
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# CONFIG_BOOTM_NETBSD is not set
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# CONFIG_BOOTM_PLAN9 is not set
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# CONFIG_BOOTM_RTEMS is not set
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# CONFIG_BOOTM_VXWORKS is not set
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# CONFIG_CMD_ELF is not set
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CONFIG_CMD_CLK=y
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CONFIG_CMD_DM=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_PWM=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_MTD=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_SMC=y
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CONFIG_DOS_PARTITION=y
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CONFIG_EFI_PARTITION=y
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CONFIG_PARTITION_TYPE_GUID=y
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CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_USE_IPADDR=y
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CONFIG_IPADDR="192.168.1.1"
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CONFIG_USE_NETMASK=y
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CONFIG_NETMASK="255.255.255.0"
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CONFIG_USE_SERVERIP=y
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CONFIG_SERVERIP="192.168.1.2"
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CONFIG_PROT_TCP=y
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CONFIG_REGMAP=y
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CONFIG_SYSCON=y
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CONFIG_CLK=y
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CONFIG_MMC_HS200_SUPPORT=y
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CONFIG_MMC_MTK=y
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CONFIG_MTD=y
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CONFIG_DM_MTD=y
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CONFIG_MTD_SPI_NAND=y
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CONFIG_PHY_FIXED=y
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CONFIG_MEDIATEK_ETH=y
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CONFIG_PINCTRL=y
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CONFIG_PINCONF=y
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CONFIG_PINCTRL_MT7988=y
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CONFIG_POWER_DOMAIN=y
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CONFIG_MTK_POWER_DOMAIN=y
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||||
CONFIG_DM_PWM=y
|
||||
CONFIG_PWM_MTK=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MTK_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_MTK_SPIM=y
|
||||
CONFIG_LZO=y
|
||||
CONFIG_HEXDUMP=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
@@ -0,0 +1,14 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Configuration for MediaTek MT7988 SoC
|
||||
*
|
||||
* Copyright (C) 2022 MediaTek Inc.
|
||||
* Author: Sam Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
#ifndef __MT7988_H
|
||||
#define __MT7988_H
|
||||
|
||||
#define CFG_MAX_MEM_MAPPED 0xC0000000
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user