renesas: Renesas R-Car Gen4 watchdog driver
Add support of Renesas R-Car Gen4 watchdog timer. Timeouts up to
8184.0s are supported (CKS1 register is not involved). The watchdog
uses the clock of type CLK_TYPE_GEN4_MDSEL.
The timeout is set in
dts/upstream/src/arm64/renesas/r8a779f0-spider-cpu.dtsi section &rwdt.
This driver is based on upstream linux commit:
e70140ba0d2b("Get rid of 'remove_new' relic from platform driver struct")
Signed-off-by: Shmuel Leib Melamud <smelamud@redhat.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Shmuel Leib Melamud
committed by
Marek Vasut
Marek Vasut
parent
77700bcc1d
commit
b1d017afda
@@ -335,6 +335,14 @@ config WDT_K3_RTI_FW_FILE
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endif
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config WDT_RENESAS
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bool "Renesas watchdog timer support"
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depends on WDT && R8A779F0
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select CLK
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select CLK_RENESAS
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help
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Enables Renesas SoC R8A779F0 watchdog timer support.
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config WDT_SANDBOX
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bool "Enable Watchdog Timer support for Sandbox"
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depends on SANDBOX && WDT
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@@ -43,6 +43,7 @@ obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
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obj-$(CONFIG_WDT_NPCM) += npcm_wdt.o
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obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o
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obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o
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obj-$(CONFIG_WDT_RENESAS) += renesas_wdt.o
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obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o
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obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o
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obj-$(CONFIG_WDT_SIEMENS_PMIC) += siemens_pmic_wdt.o
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@@ -0,0 +1,189 @@
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// SPDX-License-Identifier: GPL-2.0+
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// Copyright 2025 Red Hat, Inc., Shmuel Leib Melamud <smelamud@redhat.com>
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#include <asm/io.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include <wdt.h>
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#define usleep_range(a, b) udelay((a))
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struct rwdt {
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u32 cnt;
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u32 csra;
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u32 csrb;
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};
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#define RWTCSRA_WOVF BIT(4)
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#define RWTCSRA_WRFLG BIT(5)
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#define RWTCSRA_TME BIT(7)
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#define CSR_MASK 0xA5A5A500
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#define CNT_MASK 0x5A5A0000
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#define MAX_CNT_VALUE 65536
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/*
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* In probe, clk_rate is checked to be not more than 16 bit * biggest clock
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* divider (12 bits). d is only a factor to fully utilize the WDT counter and
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* will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits.
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*/
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#define MUL_BY_CLKS_PER_SEC(p, d) \
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DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
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/* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
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#define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
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static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 };
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struct rwdt_priv {
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struct rwdt __iomem *wdt;
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unsigned long clk_rate;
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u8 cks;
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struct clk clk;
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};
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static void rwdt_wait_cycles(struct rwdt_priv *priv, unsigned int cycles)
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{
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unsigned int delay;
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delay = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate);
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usleep_range(delay, 2 * delay);
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}
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static int rwdt_start(struct udevice *dev, u64 timeout, ulong flags)
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{
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struct rwdt_priv *priv = dev_get_priv(dev);
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u64 max_timeout;
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u8 val;
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max_timeout = DIV_BY_CLKS_PER_SEC(priv, MAX_CNT_VALUE);
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timeout = min(max_timeout, timeout / 1000);
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/* Stop the timer before we modify any register */
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val = readb_relaxed(&priv->wdt->csra) & ~RWTCSRA_TME;
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writel_relaxed(val | CSR_MASK, &priv->wdt->csra);
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/* Delay 2 cycles before setting watchdog counter */
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rwdt_wait_cycles(priv, 2);
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while (readb_relaxed(&priv->wdt->csra) & RWTCSRA_WRFLG)
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cpu_relax();
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writel_relaxed((MAX_CNT_VALUE - MUL_BY_CLKS_PER_SEC(priv, timeout))
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| CNT_MASK, &priv->wdt->cnt);
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writel_relaxed(priv->cks | RWTCSRA_TME | CSR_MASK, &priv->wdt->csra);
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return 0;
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}
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static int rwdt_stop(struct udevice *dev)
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{
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struct rwdt_priv *priv = dev_get_priv(dev);
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writel_relaxed(priv->cks | CSR_MASK, &priv->wdt->csra);
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return 0;
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}
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static int rwdt_reset(struct udevice *dev)
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{
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struct rwdt_priv *priv = dev_get_priv(dev);
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u8 val;
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/* Stop the timer before we modify any register */
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val = readb_relaxed(&priv->wdt->csra) & ~RWTCSRA_TME;
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writel_relaxed(val | CSR_MASK, &priv->wdt->csra);
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/* Delay 2 cycles before setting watchdog counter */
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rwdt_wait_cycles(priv, 2);
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writel_relaxed(0xffff | CNT_MASK, &priv->wdt->cnt);
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/* smallest divider to reboot soon */
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writel_relaxed(0 | CSR_MASK, &priv->wdt->csra);
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readb_poll_timeout(&priv->wdt->csra, val, !(val & RWTCSRA_WRFLG), 100);
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writel_relaxed(RWTCSRA_TME | CSR_MASK, &priv->wdt->csra);
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/* wait 2 cycles, so watchdog will trigger */
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rwdt_wait_cycles(priv, 2);
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return 0;
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}
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static int rwdt_probe(struct udevice *dev)
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{
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struct rwdt_priv *priv = dev_get_priv(dev);
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unsigned long clks_per_sec;
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int ret, i;
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priv->wdt = dev_remap_addr(dev);
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if (!priv->wdt)
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return -EINVAL;
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&priv->clk);
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if (ret)
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return ret;
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priv->clk_rate = clk_get_rate(&priv->clk);
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if (!priv->clk_rate) {
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ret = -ENOENT;
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goto err_clk_disable;
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}
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/*
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* Find the largest possible divider that allows clock rate
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* (clks_per_sec) to stay within 16 bits. In this case, we can still
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* measure the smallest timeout (1s) and make the largest allowed
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* timeout as large as possible.
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*/
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for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) {
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clks_per_sec = priv->clk_rate / clk_divs[i];
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if (clks_per_sec && clks_per_sec < 65536) {
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priv->cks = i;
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break;
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}
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}
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/* can't find a suitable clock divider */
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if (i < 0) {
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ret = -ERANGE;
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goto err_clk_disable;
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}
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return 0;
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err_clk_disable:
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clk_disable(&priv->clk);
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return ret;
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}
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static const struct wdt_ops rwdt_ops = {
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.start = rwdt_start,
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.reset = rwdt_reset,
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.stop = rwdt_stop,
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};
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static const struct udevice_id rwdt_ids[] = {
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{ .compatible = "renesas,rcar-gen2-wdt" },
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{ .compatible = "renesas,rcar-gen3-wdt" },
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{ .compatible = "renesas,rcar-gen4-wdt" },
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{}
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};
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U_BOOT_DRIVER(wdt_renesas) = {
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.name = "wdt_renesas",
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.id = UCLASS_WDT,
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.of_match = rwdt_ids,
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.ops = &rwdt_ops,
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.probe = rwdt_probe,
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.priv_auto = sizeof(struct rwdt_priv),
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};
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