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spacemit: k1: enable SPL with debug UART

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Add SPL support featuring debug UART output for early boot
diagnostics on K1 SoC.

Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Tested-by: Songsong Zhang <sszhang@vsit.ai>
This commit is contained in:
Raymond Mao
2026-07-21 16:57:13 +08:00
committed by Tim Ouyang
parent d577665526
commit ae94d8af7f
6 changed files with 52 additions and 2 deletions
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arch/riscv/cpu/k1/Kconfig
+2
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@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Copyright (C) 2024, Kongyang Liu <seashell11234455@gmail.com>
# Copyright (C) 2025-2026, RISCstar Ltd.
if TARGET_SPACEMIT_K1
@@ -9,6 +10,7 @@ config SPACEMIT_K1
select BINMAN
select ARCH_EARLY_INIT_R
select SYS_CACHE_SHIFT_6
select SUPPORT_SPL
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi
+4
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@@ -11,3 +11,7 @@
reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
};
};
&uart0 {
bootph-pre-ram;
};
board/spacemit/k1/Makefile
+2
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@@ -1,5 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
# Copyright (c) 2025-2026, RISCstar Ltd.
obj-y := board.o
obj-$(CONFIG_SPL_BUILD) += spl.o
board/spacemit/k1/spl.c
+24
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@@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2025-2026, RISCstar Ltd.
*/
#include <spl.h>
void board_init_f(ulong dummy)
{
int ret;
ret = spl_early_init();
if (ret)
panic("spl_early_init() failed:%d\n", ret);
riscv_cpu_setup();
preloader_console_init();
}
u32 spl_boot_device(void)
{
return BOOT_DEVICE_NONE;
}
configs/spacemit_k1_defconfig
+16
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@@ -4,17 +4,30 @@ CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="spacemit/k1-bananapi-f3"
CONFIG_SPL_STACK=0xc083fb00
CONFIG_SPL_TEXT_BASE=0xc0801000
CONFIG_SPL_BSS_START_ADDR=0xc083fc00
CONFIG_SPL_BSS_MAX_SIZE=0x400
CONFIG_SYS_BOOTM_LEN=0xa000000
CONFIG_SYS_LOAD_ADDR=0x200000
CONFIG_SPL_SIZE_LIMIT=0x31000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd4017000
CONFIG_DEBUG_UART_CLOCK=14700000
CONFIG_TARGET_SPACEMIT_K1=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_STACK_SIZE=0x100000
CONFIG_FIT=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
# CONFIG_BOARD_INIT is not set
CONFIG_SPL_MAX_SIZE=0x33000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_HAVE_INIT_STACK=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_UPSTREAM=y
CONFIG_ENV_OVERWRITE=y
@@ -22,5 +35,8 @@ CONFIG_CLK_SPACEMIT=y
CONFIG_CLK_SPACEMIT_K1=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_DEBUG_UART_NS16550=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_SYS_NS16550=y
CONFIG_SYS_NS16550_MEM32=y
include/configs/k1.h
+4 -2
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@@ -1,13 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
* Copyright (C) 2025-2026, RISCstar Ltd.
*
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CFG_SYS_SDRAM_BASE 0x0
#define CFG_SYS_NS16550_IER 0x40 /* UART Unit Enable */
#define CFG_SYS_NS16550_CLK 14700000
#define CFG_SYS_NS16550_IER 0x40 /* UART Unit Enable */
#define CFG_SYS_SDRAM_BASE 0x0
#endif /* __CONFIG_H */