spi: airoha: add dma support
This patch speed up cache reading/writing/updating opearions. It was tested on en7523/an7581 and some other Airoha chips. It will speed up * page reading/writing without oob * page reading/writing with oob * oob reading/writing (significant for UBI scanning) The only know issue appears in a very specific conditions for en7523 family chips only. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
This commit is contained in:
Mikhail Kshevetskiy
committed by
Michael Trimarchi
Michael Trimarchi
parent
ba04299ff7
commit
a7c3319bc0
@@ -141,12 +141,14 @@
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#define SPI_NFI_CUS_SEC_SIZE_EN BIT(16)
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#define REG_SPI_NFI_RD_CTL2 0x0510
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#define REG_SPI_NFI_RD_CTL3 0x0514
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#define REG_SPI_NFI_PG_CTL1 0x0524
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#define SPI_NFI_PG_LOAD_CMD GENMASK(15, 8)
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#define REG_SPI_NFI_PG_CTL2 0x0528
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#define REG_SPI_NFI_NOR_PROG_ADDR 0x052c
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#define REG_SPI_NFI_NOR_RD_ADDR 0x0534
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@@ -219,6 +221,8 @@ struct airoha_snand_priv {
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u8 sec_num;
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u8 spare_size;
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} nfi_cfg;
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u8 *txrx_buf;
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};
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static int airoha_snand_set_fifo_op(struct airoha_snand_priv *priv,
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@@ -614,6 +618,302 @@ static bool airoha_snand_supports_op(struct spi_slave *slave,
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(!op->data.nbytes || op->data.buswidth == 1);
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}
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static int airoha_snand_dirmap_create(struct spi_mem_dirmap_desc *desc)
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{
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struct spi_slave *slave = desc->slave;
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struct udevice *bus = slave->dev->parent;
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struct airoha_snand_priv *priv = dev_get_priv(bus);
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if (!priv->txrx_buf)
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return -EINVAL;
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if (desc->info.offset + desc->info.length > U32_MAX)
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return -EINVAL;
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if (!airoha_snand_supports_op(desc->slave, &desc->info.op_tmpl))
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return -EOPNOTSUPP;
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return 0;
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}
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static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
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u64 offs, size_t len, void *buf)
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{
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struct spi_mem_op *op = &desc->info.op_tmpl;
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struct spi_slave *slave = desc->slave;
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struct udevice *bus = slave->dev->parent;
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struct airoha_snand_priv *priv = dev_get_priv(bus);
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u8 *txrx_buf = priv->txrx_buf;
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dma_addr_t dma_addr;
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u32 val, rd_mode;
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int err;
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switch (op->cmd.opcode) {
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case SPI_NAND_OP_READ_FROM_CACHE_DUAL:
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rd_mode = 1;
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break;
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case SPI_NAND_OP_READ_FROM_CACHE_QUAD:
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rd_mode = 2;
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break;
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default:
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rd_mode = 0;
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break;
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}
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err = airoha_snand_set_mode(priv, SPI_MODE_DMA);
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if (err < 0)
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return err;
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err = airoha_snand_nfi_config(priv);
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if (err)
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goto error_dma_mode_off;
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dma_addr = dma_map_single(txrx_buf, SPI_NAND_CACHE_SIZE,
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DMA_FROM_DEVICE);
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/* set dma addr */
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err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_STRADDR,
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dma_addr);
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if (err)
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goto error_dma_unmap;
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/* set cust sec size */
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val = priv->nfi_cfg.sec_size * priv->nfi_cfg.sec_num;
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val = FIELD_PREP(SPI_NFI_READ_DATA_BYTE_NUM, val);
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err = regmap_update_bits(priv->regmap_nfi,
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REG_SPI_NFI_SNF_MISC_CTL2,
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SPI_NFI_READ_DATA_BYTE_NUM, val);
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if (err)
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goto error_dma_unmap;
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/* set read command */
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err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_RD_CTL2,
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op->cmd.opcode);
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if (err)
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goto error_dma_unmap;
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/* set read mode */
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err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
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FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, rd_mode));
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if (err)
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goto error_dma_unmap;
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/* set read addr: zero page offset + descriptor read offset */
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err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_RD_CTL3,
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desc->info.offset);
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if (err)
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goto error_dma_unmap;
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/* set nfi read */
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err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
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SPI_NFI_OPMODE,
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FIELD_PREP(SPI_NFI_OPMODE, 6));
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if (err)
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goto error_dma_unmap;
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err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
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SPI_NFI_READ_MODE | SPI_NFI_DMA_MODE);
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if (err)
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goto error_dma_unmap;
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err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_CMD, 0x0);
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if (err)
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goto error_dma_unmap;
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/* trigger dma reading */
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err = regmap_clear_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
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SPI_NFI_RD_TRIG);
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if (err)
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goto error_dma_unmap;
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err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
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SPI_NFI_RD_TRIG);
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if (err)
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goto error_dma_unmap;
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err = regmap_read_poll_timeout(priv->regmap_nfi,
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REG_SPI_NFI_SNF_STA_CTL1, val,
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(val & SPI_NFI_READ_FROM_CACHE_DONE),
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0, 1 * MSEC_PER_SEC);
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if (err)
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goto error_dma_unmap;
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/*
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* SPI_NFI_READ_FROM_CACHE_DONE bit must be written at the end
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* of dirmap_read operation even if it is already set.
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*/
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err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
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SPI_NFI_READ_FROM_CACHE_DONE,
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SPI_NFI_READ_FROM_CACHE_DONE);
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if (err)
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goto error_dma_unmap;
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err = regmap_read_poll_timeout(priv->regmap_nfi, REG_SPI_NFI_INTR,
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val, (val & SPI_NFI_AHB_DONE), 0,
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1 * MSEC_PER_SEC);
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if (err)
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goto error_dma_unmap;
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/* DMA read need delay for data ready from controller to DRAM */
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udelay(1);
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dma_unmap_single(dma_addr, SPI_NAND_CACHE_SIZE, DMA_FROM_DEVICE);
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err = airoha_snand_set_mode(priv, SPI_MODE_MANUAL);
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if (err < 0)
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return err;
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memcpy(buf, txrx_buf + offs, len);
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return len;
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error_dma_unmap:
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dma_unmap_single(dma_addr, SPI_NAND_CACHE_SIZE, DMA_FROM_DEVICE);
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error_dma_mode_off:
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airoha_snand_set_mode(priv, SPI_MODE_MANUAL);
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return err;
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}
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static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
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u64 offs, size_t len, const void *buf)
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{
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struct spi_slave *slave = desc->slave;
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struct udevice *bus = slave->dev->parent;
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struct airoha_snand_priv *priv = dev_get_priv(bus);
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u8 *txrx_buf = priv->txrx_buf;
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dma_addr_t dma_addr;
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u32 wr_mode, val, opcode;
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int err;
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opcode = desc->info.op_tmpl.cmd.opcode;
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switch (opcode) {
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case SPI_NAND_OP_PROGRAM_LOAD_SINGLE:
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case SPI_NAND_OP_PROGRAM_LOAD_RAMDOM_SINGLE:
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wr_mode = 0;
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break;
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case SPI_NAND_OP_PROGRAM_LOAD_QUAD:
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case SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD:
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wr_mode = 2;
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break;
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default:
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/* unknown opcode */
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return -EOPNOTSUPP;
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}
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memcpy(txrx_buf + offs, buf, len);
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err = airoha_snand_set_mode(priv, SPI_MODE_DMA);
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if (err < 0)
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return err;
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err = airoha_snand_nfi_config(priv);
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if (err)
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goto error_dma_mode_off;
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dma_addr = dma_map_single(txrx_buf, SPI_NAND_CACHE_SIZE,
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DMA_TO_DEVICE);
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/* set dma addr */
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err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_STRADDR,
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dma_addr);
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if (err)
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goto error_dma_unmap;
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val = FIELD_PREP(SPI_NFI_PROG_LOAD_BYTE_NUM,
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priv->nfi_cfg.sec_size * priv->nfi_cfg.sec_num);
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err = regmap_update_bits(priv->regmap_nfi,
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REG_SPI_NFI_SNF_MISC_CTL2,
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SPI_NFI_PROG_LOAD_BYTE_NUM, val);
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if (err)
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goto error_dma_unmap;
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/* set write command */
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err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_PG_CTL1,
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FIELD_PREP(SPI_NFI_PG_LOAD_CMD, opcode));
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if (err)
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goto error_dma_unmap;
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/* set write mode */
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err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
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FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, wr_mode));
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if (err)
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goto error_dma_unmap;
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/* set write addr: zero page offset + descriptor write offset */
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err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_PG_CTL2,
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desc->info.offset);
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if (err)
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goto error_dma_unmap;
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err = regmap_clear_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
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SPI_NFI_READ_MODE);
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if (err)
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goto error_dma_unmap;
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err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
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SPI_NFI_OPMODE,
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FIELD_PREP(SPI_NFI_OPMODE, 3));
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if (err)
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goto error_dma_unmap;
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err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
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SPI_NFI_DMA_MODE);
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if (err)
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goto error_dma_unmap;
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err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_CMD, 0x80);
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if (err)
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goto error_dma_unmap;
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/* trigger dma writing */
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err = regmap_clear_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
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SPI_NFI_WR_TRIG);
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if (err)
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goto error_dma_unmap;
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err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
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SPI_NFI_WR_TRIG);
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if (err)
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goto error_dma_unmap;
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err = regmap_read_poll_timeout(priv->regmap_nfi, REG_SPI_NFI_INTR,
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val, (val & SPI_NFI_AHB_DONE), 0,
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1 * MSEC_PER_SEC);
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if (err)
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goto error_dma_unmap;
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err = regmap_read_poll_timeout(priv->regmap_nfi,
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REG_SPI_NFI_SNF_STA_CTL1, val,
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(val & SPI_NFI_LOAD_TO_CACHE_DONE),
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0, 1 * MSEC_PER_SEC);
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if (err)
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goto error_dma_unmap;
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/*
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* SPI_NFI_LOAD_TO_CACHE_DONE bit must be written at the end
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* of dirmap_write operation even if it is already set.
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*/
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err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
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SPI_NFI_LOAD_TO_CACHE_DONE,
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SPI_NFI_LOAD_TO_CACHE_DONE);
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if (err)
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goto error_dma_unmap;
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dma_unmap_single(dma_addr, SPI_NAND_CACHE_SIZE, DMA_TO_DEVICE);
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err = airoha_snand_set_mode(priv, SPI_MODE_MANUAL);
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if (err < 0)
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return err;
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return len;
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error_dma_unmap:
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dma_unmap_single(dma_addr, SPI_NAND_CACHE_SIZE, DMA_TO_DEVICE);
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error_dma_mode_off:
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airoha_snand_set_mode(priv, SPI_MODE_MANUAL);
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return err;
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}
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static int airoha_snand_exec_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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@@ -696,6 +996,12 @@ static int airoha_snand_probe(struct udevice *dev)
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struct airoha_snand_priv *priv = dev_get_priv(dev);
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int ret;
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priv->txrx_buf = memalign(ARCH_DMA_MINALIGN, SPI_NAND_CACHE_SIZE);
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if (!priv->txrx_buf) {
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dev_err(dev, "failed to alloacate memory for dirmap\n");
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return -ENOMEM;
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}
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ret = regmap_init_mem_index(dev_ofnode(dev), &priv->regmap_ctrl, 0);
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if (ret) {
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dev_err(dev, "failed to init spi ctrl regmap\n");
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@@ -769,6 +1075,9 @@ static int airoha_snand_nfi_setup(struct spi_slave *slave,
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static const struct spi_controller_mem_ops airoha_snand_mem_ops = {
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.supports_op = airoha_snand_supports_op,
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.exec_op = airoha_snand_exec_op,
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.dirmap_create = airoha_snand_dirmap_create,
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.dirmap_read = airoha_snand_dirmap_read,
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.dirmap_write = airoha_snand_dirmap_write,
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};
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static const struct dm_spi_ops airoha_snfi_spi_ops = {
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