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mmc: am654_sdhci: Set ENDLL=1 for DDR52 mode

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According to the device datasheet [0], ENDLL=1 for
DDR52 mode, so call am654_sdhci_setup_dll() and write
itapdly after since we do not carry out tuning.

[0] https://www.ti.com/lit/ds/symlink/am62p.pdf

Fixes: c964447ea3 ("mmc: am654_sdhci: Add support for input tap delay")
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This commit is contained in:
Judith Mendez
2024-04-29 10:55:27 -06:00
committed by Tom Rini
parent 056af04a39
commit a124e31a97
1 changed files with 3 additions and 1 deletions
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drivers/mmc/am654_sdhci.c
+3 -1
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@@ -289,12 +289,14 @@ static int am654_sdhci_set_ios_post(struct sdhci_host *host)
regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
if (mode > UHS_SDR25 && speed >= CLOCK_TOO_SLOW_HZ) {
if ((mode > UHS_SDR25 || mode == MMC_DDR_52) && speed >= CLOCK_TOO_SLOW_HZ) {
ret = am654_sdhci_setup_dll(plat, speed);
if (ret)
return ret;
plat->dll_enable = true;
am654_sdhci_write_itapdly(plat, plat->itap_del_sel[mode],
plat->itap_del_ena[mode]);
} else {
am654_sdhci_setup_delay_chain(plat, mode);
plat->dll_enable = false;