arm: ti: omap: Extract common clock definitions
Lots of clock definitions are common to OMAP3, OMAP4 and OMAP5. So the same macros are defined both in arch-am33xx/clock.h and in arch-omap5/clock.h. Upcoming support for OMAP4 will again need the same macros. Group these common macro definitions into a common omap_clock header shared across the OMAP2+ families. Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com>
This commit is contained in:
Bastien Curutchet
committed by
Tom Rini
Tom Rini
parent
bc93b4bcb3
commit
9a4f679096
@@ -12,31 +12,10 @@
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#include <asm/arch/clocks_am33xx.h>
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#include <asm/arch/hardware.h>
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#include <asm/ti-common/omap_clock.h>
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#define LDELAY 1000000
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/*CM_<clock_domain>__CLKCTRL */
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#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
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#define CD_CLKCTRL_CLKTRCTRL_MASK 3
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#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
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#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
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#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
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/* CM_<clock_domain>_<module>_CLKCTRL */
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#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
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#define MODULE_CLKCTRL_MODULEMODE_MASK 3
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#define MODULE_CLKCTRL_IDLEST_SHIFT 16
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#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
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#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
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#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
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#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
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#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
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#define MODULE_CLKCTRL_IDLEST_IDLE 2
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#define MODULE_CLKCTRL_IDLEST_DISABLED 3
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/* CM_CLKMODE_DPLL */
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#define CM_CLKMODE_DPLL_SSC_EN_SHIFT 12
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#define CM_CLKMODE_DPLL_SSC_EN_MASK (1 << 12)
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@@ -53,26 +32,6 @@
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#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
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#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
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#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
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#define CM_CLKMODE_DPLL_EN_SHIFT 0
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#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
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#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
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#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
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#define DPLL_EN_STOP 1
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#define DPLL_EN_MN_BYPASS 4
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#define DPLL_EN_LOW_POWER_BYPASS 5
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#define DPLL_EN_FAST_RELOCK_BYPASS 6
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#define DPLL_EN_LOCK 7
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/* CM_IDLEST_DPLL fields */
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#define ST_DPLL_CLK_MASK 1
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/* CM_CLKSEL_DPLL */
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#define CM_CLKSEL_DPLL_M_SHIFT 8
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#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
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#define CM_CLKSEL_DPLL_N_SHIFT 0
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#define CM_CLKSEL_DPLL_N_MASK 0x7F
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/* CM_SSC_DELTAM_DPLL */
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#define CM_SSC_DELTAM_DPLL_FRAC_SHIFT 0
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@@ -22,7 +22,6 @@
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#define UART_CLK_RUNNING_MASK 0x1
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#define UART_SMART_IDLE_EN (0x1 << 0x3)
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#define CM_DLL_CTRL_NO_OVERRIDE 0x0
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#define CM_DLL_READYST 0x4
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#define NUM_OPPS 6
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@@ -9,6 +9,8 @@
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#ifndef _CLOCKS_OMAP5_H_
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#define _CLOCKS_OMAP5_H_
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#include <asm/ti-common/omap_clock.h>
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/*
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* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
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* loop, allow for a minimum of 2 ms wait (in reality the wait will be
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@@ -19,7 +21,6 @@
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/* CM_DLL_CTRL */
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#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
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#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
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#define CM_DLL_CTRL_NO_OVERRIDE 0
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/* CM_CLKMODE_DPLL */
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#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
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@@ -32,20 +33,6 @@
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#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
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#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
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#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
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#define CM_CLKMODE_DPLL_EN_SHIFT 0
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#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
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#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
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#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
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#define DPLL_EN_STOP 1
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#define DPLL_EN_MN_BYPASS 4
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#define DPLL_EN_LOW_POWER_BYPASS 5
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#define DPLL_EN_FAST_RELOCK_BYPASS 6
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#define DPLL_EN_LOCK 7
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/* CM_IDLEST_DPLL fields */
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#define ST_DPLL_CLK_MASK 1
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/* SGX */
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#define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25)
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@@ -54,24 +41,6 @@
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/* CM_CLKSEL_DPLL */
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#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
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#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
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#define CM_CLKSEL_DPLL_M_SHIFT 8
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#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
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#define CM_CLKSEL_DPLL_N_SHIFT 0
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#define CM_CLKSEL_DPLL_N_MASK 0x7F
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#define CM_CLKSEL_DCC_EN_SHIFT 22
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#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
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/* CM_SYS_CLKSEL */
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#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
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/* CM_CLKSEL_CORE */
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#define CLKSEL_CORE_SHIFT 0
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#define CLKSEL_L3_SHIFT 4
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#define CLKSEL_L4_SHIFT 8
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#define CLKSEL_CORE_X2_DIV_1 0
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#define CLKSEL_L3_CORE_DIV_2 1
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#define CLKSEL_L4_L3_DIV_2 1
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/* CM_ABE_PLL_REF_CLKSEL */
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#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
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@@ -91,57 +60,12 @@
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#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
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/* CM_SHADOW_FREQ_CONFIG1 */
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#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
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#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
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#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
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#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
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#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
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#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
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#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
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/*CM_<clock_domain>__CLKCTRL */
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#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
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#define CD_CLKCTRL_CLKTRCTRL_MASK 3
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#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
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#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
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#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
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#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
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/* CM_<clock_domain>_<module>_CLKCTRL */
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#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
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#define MODULE_CLKCTRL_MODULEMODE_MASK 3
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#define MODULE_CLKCTRL_IDLEST_SHIFT 16
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#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
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#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
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#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
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#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
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#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
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#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
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#define MODULE_CLKCTRL_IDLEST_IDLE 2
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#define MODULE_CLKCTRL_IDLEST_DISABLED 3
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/* CM_L4PER_GPIO4_CLKCTRL */
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#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
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/* CM_L3INIT_HSMMCn_CLKCTRL */
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#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
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#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (3 << 25)
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/* CM_IPU1_IPU1_CLKCTRL CLKSEL MASK */
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#define IPU1_CLKCTRL_CLKSEL_MASK BIT(24)
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/* CM_L3INIT_SATA_CLKCTRL */
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#define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
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/* CM_WKUP_GPTIMER1_CLKCTRL */
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#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
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/* CM_CAM_ISS_CLKCTRL */
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#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
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@@ -181,12 +105,6 @@
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/* CM_L3INIT_OCP2SCP1_CLKCTRL */
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#define OCP2SCP1_CLKCTRL_MODULEMODE_HW (1 << 0)
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/* CM_MPU_MPU_CLKCTRL */
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#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
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#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24)
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#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26
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#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26)
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/* CM_WKUPAON_SCRM_CLKCTRL */
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#define OPTFCLKEN_SCRM_PER_SHIFT 9
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#define OPTFCLKEN_SCRM_PER_MASK (1 << 9)
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@@ -201,9 +119,6 @@
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#define RSTTIME1_SHIFT 0
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#define RSTTIME1_MASK (0x3ff << 0)
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/* Clock frequencies */
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#define OMAP_SYS_CLK_IND_38_4_MHZ 6
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/* CTRL_CORE_SRCOMP_NORTH_SIDE */
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#define USB2PHY_DISCHGDET (1 << 29)
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#define USB2PHY_AUTORESUME_EN (1 << 30)
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@@ -399,16 +314,4 @@
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/* CKO buffer control */
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#define CKOBUFFER_CLK_ENABLE_MASK (1 << 28)
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/* AUXCLKx reg fields */
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#define AUXCLK_ENABLE_MASK (1 << 8)
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#define AUXCLK_SRCSELECT_SHIFT 1
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#define AUXCLK_SRCSELECT_MASK (3 << 1)
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#define AUXCLK_CLKDIV_SHIFT 16
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#define AUXCLK_CLKDIV_MASK (0xF << 16)
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#define AUXCLK_SRCSELECT_SYS_CLK 0
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#define AUXCLK_SRCSELECT_CORE_DPLL 1
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#define AUXCLK_SRCSELECT_PER_DPLL 2
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#define AUXCLK_SRCSELECT_ALTERNATE 3
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#endif /* _CLOCKS_OMAP5_H_ */
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@@ -0,0 +1,114 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef _OMAP_CLOCK_H_
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#define _OMAP_CLOCK_H_
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/* CM_CLKMODE_DPLL */
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#define CM_CLKMODE_DPLL_EN_SHIFT 0
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#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
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#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
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#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
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#define DPLL_EN_STOP 1
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#define DPLL_EN_MN_BYPASS 4
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#define DPLL_EN_LOW_POWER_BYPASS 5
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#define DPLL_EN_FAST_RELOCK_BYPASS 6
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#define DPLL_EN_LOCK 7
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#define DPLL_NO_LOCK 0
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#define DPLL_LOCK 1
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/* CM_IDLEST_DPLL fields */
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#define ST_DPLL_CLK_MASK 1
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/* CM_CLKSEL_CORE */
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#define CLKSEL_CORE_SHIFT 0
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#define CLKSEL_L3_SHIFT 4
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#define CLKSEL_L4_SHIFT 8
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/* CM_DLL_CTRL */
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#define CM_DLL_CTRL_NO_OVERRIDE 0
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/* CM_CLKSEL_DPLL */
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#define CM_CLKSEL_DPLL_N_SHIFT 0
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#define CM_CLKSEL_DPLL_N_MASK 0x7F
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#define CM_CLKSEL_DPLL_M_SHIFT 8
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#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
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#define CM_CLKSEL_DCC_EN_SHIFT 22
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#define CM_CLKSEL_DCC_EN_MASK BIT(22)
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#define CLKSEL_CORE_X2_DIV_1 0
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#define CLKSEL_L3_CORE_DIV_2 1
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#define CLKSEL_L4_L3_DIV_2 1
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/* CM_SYS_CLKSEL */
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#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
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/*CM_<clock_domain>__CLKCTRL */
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#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
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#define CD_CLKCTRL_CLKTRCTRL_MASK 3
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#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
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#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
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#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
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#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
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/* CM_SHADOW_FREQ_CONFIG1 */
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#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
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#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
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#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
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#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
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#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
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#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
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#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
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/* CM_<clock_domain>_<module>_CLKCTRL */
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#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
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#define MODULE_CLKCTRL_MODULEMODE_MASK 3
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#define MODULE_CLKCTRL_IDLEST_SHIFT 16
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#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
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#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
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#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
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#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
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#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
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#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
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#define MODULE_CLKCTRL_IDLEST_IDLE 2
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#define MODULE_CLKCTRL_IDLEST_DISABLED 3
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/* CM_L4PER_GPIO4_CLKCTRL */
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#define GPIO4_CLKCTRL_OPTFCLKEN_MASK BIT(8)
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/* CM_WKUP_GPTIMER1_CLKCTRL */
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#define GPTIMER1_CLKCTRL_CLKSEL_MASK BIT(24)
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/* CM_L3INIT_HSMMCn_CLKCTRL */
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#define HSMMC_CLKCTRL_CLKSEL_MASK BIT(24)
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#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (3 << 25)
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/* Clock frequencies */
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#define OMAP_SYS_CLK_IND_38_4_MHZ 6
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/* AUXCLKx reg fields */
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#define AUXCLK_ENABLE_MASK BIT(8)
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#define AUXCLK_SRCSELECT_SHIFT 1
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#define AUXCLK_SRCSELECT_MASK (3 << 1)
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#define AUXCLK_CLKDIV_SHIFT 16
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#define AUXCLK_CLKDIV_MASK (0xF << 16)
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#define AUXCLK_CLKDIV_2 1
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#define AUXCLK_SRCSELECT_SYS_CLK 0
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#define AUXCLK_SRCSELECT_CORE_DPLL 1
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#define AUXCLK_SRCSELECT_PER_DPLL 2
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#define AUXCLK_SRCSELECT_ALTERNATE 3
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/* CM_MPU_MPU_CLKCTRL */
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#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
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#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24)
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#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26
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#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK BIT(26)
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#endif /* _OMAP_CLOCK_H_ */
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