clk: rs9: Add Renesas 9-series PCIe clock generator driver
Add driver for Renesas 9-series PCIe clock generators. This driver
is designed to support 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ series I2C
PCIe clock generators.
The driver is capable of configuring per-chip spread spectrum mode
and output amplitude, as well as per-output slew rate.
Losely based on Linux 7.1 commit
5ec820fc28d0 ("clk: rs9: Reserve 8 struct clk_hw slots for for 9FGV0841")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut
@@ -215,6 +215,13 @@ config CLK_HSDK
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Enable this to support the cgu clocks on Synopsys ARC HSDK and
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Synopsys ARC HSDK-4xD boards
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config CLK_RS9_PCIE
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tristate "Clock driver for Renesas 9-series PCIe clock generators"
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depends on CLK
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help
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This driver supports the Renesas 9-series PCIe clock generator
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models 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ.
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config CLK_VERSACLOCK
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bool "Enable VersaClock 5/6 devices"
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depends on CLK
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@@ -45,6 +45,7 @@ obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
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obj-$(CONFIG_CLK_OWL) += owl/
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obj-$(CONFIG_CLK_QCOM) += qcom/
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obj-$(CONFIG_CLK_RENESAS) += renesas/
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obj-$(CONFIG_$(PHASE_)CLK_RS9_PCIE) += clk-renesas-pcie.o
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obj-$(CONFIG_$(PHASE_)CLK_SCMI) += clk_scmi.o
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obj-$(CONFIG_CLK_SIFIVE) += sifive/
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obj-$(CONFIG_CLK_SOPHGO) += sophgo/
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@@ -0,0 +1,327 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Driver for Renesas 9-series PCIe clock generator driver
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*
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* The following series can be supported:
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* - 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ
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* Currently supported:
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* - 9FGV0241
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* - 9FGV0441
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* - 9FGV0841
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*
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* Copyright (C) 2022-2026 Marek Vasut
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*/
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#include <clk-uclass.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <errno.h>
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#include <i2c.h>
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#include <linux/bitops.h>
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#define RS9_REG_OE 0x0
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#define RS9_REG_SS 0x1
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#define RS9_REG_SS_AMP_0V6 0x0
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#define RS9_REG_SS_AMP_0V7 0x1
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#define RS9_REG_SS_AMP_0V8 0x2
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#define RS9_REG_SS_AMP_0V9 0x3
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#define RS9_REG_SS_AMP_DEFAULT RS9_REG_SS_AMP_0V8
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#define RS9_REG_SS_AMP_MASK 0x3
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#define RS9_REG_SS_SSC_100 0
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#define RS9_REG_SS_SSC_M025 (1 << 3)
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#define RS9_REG_SS_SSC_M050 (3 << 3)
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#define RS9_REG_SS_SSC_DEFAULT RS9_REG_SS_SSC_100
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#define RS9_REG_SS_SSC_MASK (3 << 3)
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#define RS9_REG_SS_SSC_LOCK BIT(5)
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#define RS9_REG_SR 0x2
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#define RS9_REG_REF 0x3
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#define RS9_REG_REF_OE BIT(4)
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#define RS9_REG_REF_OD BIT(5)
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#define RS9_REG_REF_SR_SLOWEST 0
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#define RS9_REG_REF_SR_SLOW (1 << 6)
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#define RS9_REG_REF_SR_FAST (2 << 6)
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#define RS9_REG_REF_SR_FASTER (3 << 6)
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#define RS9_REG_VID 0x5
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#define RS9_REG_DID 0x6
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#define RS9_REG_BCP 0x7
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#define RS9_REG_VID_MASK GENMASK(3, 0)
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#define RS9_REG_VID_IDT 0x01
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#define RS9_REG_DID_TYPE_FGV (0x0 << RS9_REG_DID_TYPE_SHIFT)
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#define RS9_REG_DID_TYPE_DBV (0x1 << RS9_REG_DID_TYPE_SHIFT)
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#define RS9_REG_DID_TYPE_DMV (0x2 << RS9_REG_DID_TYPE_SHIFT)
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#define RS9_REG_DID_TYPE_SHIFT 0x6
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/* Structure to describe features of a particular 9-series model */
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struct rs9_chip_info {
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unsigned int num_clks;
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u8 outshift;
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u8 did;
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};
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struct rs9_driver_data {
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struct udevice *i2c;
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struct rs9_chip_info *chip_info;
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unsigned long rate;
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u8 pll_amplitude;
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u8 pll_ssc;
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u8 clk_dif_sr;
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};
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static int clk_rs9_request(struct clk *clk)
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{
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struct rs9_driver_data *rs9 = dev_get_priv(clk->dev);
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if (clk->id > rs9->chip_info->num_clks)
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return -EINVAL;
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return 0;
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}
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static ulong clk_rs9_get_rate(struct clk *clk)
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{
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struct rs9_driver_data *rs9 = dev_get_priv(clk->dev);
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return rs9->rate * 4;
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}
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static const struct clk_ops clk_rs9_ops = {
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.request = clk_rs9_request,
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.get_rate = clk_rs9_get_rate,
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};
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static int rs9_write(struct udevice *dev, u8 reg, u8 val)
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{
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u8 data[2] = { 1, val };
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return dm_i2c_write(dev, reg, data, 2);
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}
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static int rs9_read(struct udevice *dev, u8 reg, u8 *val)
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{
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struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
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struct i2c_msg xfer[2];
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u8 txdata = reg;
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u8 rxdata[2];
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int ret;
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xfer[0].addr = chip->chip_addr;
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xfer[0].flags = 0;
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xfer[0].len = 1;
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xfer[0].buf = (void *)&txdata;
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xfer[1].addr = chip->chip_addr;
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xfer[1].flags = I2C_M_RD;
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xfer[1].len = 2;
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xfer[1].buf = (void *)rxdata;
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ret = dm_i2c_xfer(dev, xfer, 2);
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if (ret < 0)
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return ret;
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/*
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* Byte 0 is transfer length, which is always 1 due
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* to BCP register programming to 1 in rs9_probe(),
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* ignore it and use data from Byte 1.
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*/
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*val = rxdata[1];
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return 0;
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}
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static u8 rs9_calc_dif(const struct rs9_driver_data *rs9, int idx)
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{
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/*
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* On 9FGV0241, the DIF OE0 is BIT(1) and DIF OE(1) is BIT(2),
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* on 9FGV0441 and 9FGV0841 the DIF OE0 is BIT(0) and so on.
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* Increment the index in the 9FGV0241 special case here.
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*/
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return BIT(idx + rs9->chip_info->outshift);
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}
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static int rs9_get_output_config(struct rs9_driver_data *rs9, int idx)
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{
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struct udevice *dev = rs9->i2c;
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u8 dif = rs9_calc_dif(rs9, idx);
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unsigned char name[5] = "DIF0";
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ofnode np;
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u32 sr;
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/* Set defaults */
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rs9->clk_dif_sr |= dif;
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snprintf(name, 5, "DIF%d", idx);
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np = dev_read_subnode(dev, name);
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if (!ofnode_valid(np))
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return 0;
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/* Output clock slew rate */
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sr = ofnode_read_u32_default(np, "renesas,slew-rate", 3000000);
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if (sr == 2000000) { /* 2V/ns */
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rs9->clk_dif_sr &= ~dif;
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} else if (sr == 3000000) { /* 3V/ns (default) */
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rs9->clk_dif_sr |= dif;
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} else {
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dev_err(dev, "Invalid renesas,slew-rate value\n");
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return -EINVAL;
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}
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return 0;
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}
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static int rs9_get_common_config(struct rs9_driver_data *rs9)
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{
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struct udevice *dev = rs9->i2c;
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unsigned int amp, ssc;
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/* Set defaults */
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rs9->pll_amplitude = RS9_REG_SS_AMP_DEFAULT;
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rs9->pll_ssc = RS9_REG_SS_SSC_DEFAULT;
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/* Output clock amplitude */
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amp = dev_read_u32_default(dev, "renesas,out-amplitude-microvolt", 700000);
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if (amp == 600000) { /* 0.6V */
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rs9->pll_amplitude = RS9_REG_SS_AMP_0V6;
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} else if (amp == 700000) { /* 0.7V (default) */
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rs9->pll_amplitude = RS9_REG_SS_AMP_0V7;
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} else if (amp == 800000) { /* 0.8V */
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rs9->pll_amplitude = RS9_REG_SS_AMP_0V8;
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} else if (amp == 900000) { /* 0.9V */
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rs9->pll_amplitude = RS9_REG_SS_AMP_0V9;
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} else {
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dev_err(dev, "Invalid renesas,out-amplitude-microvolt value\n");
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return -EINVAL;
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}
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/* Output clock spread spectrum */
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ssc = dev_read_u32_default(dev, "renesas,out-spread-spectrum", 100000);
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if (ssc == 100000) { /* 100% ... no spread (default) */
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rs9->pll_ssc = RS9_REG_SS_SSC_100;
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} else if (ssc == 99750) { /* -0.25% ... down spread */
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rs9->pll_ssc = RS9_REG_SS_SSC_M025;
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} else if (ssc == 99500) { /* -0.50% ... down spread */
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rs9->pll_ssc = RS9_REG_SS_SSC_M050;
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} else {
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dev_err(dev, "Invalid renesas,out-spread-spectrum value\n");
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return -EINVAL;
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}
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return 0;
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}
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static void rs9_update_config(struct rs9_driver_data *rs9)
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{
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struct udevice *dev = rs9->i2c;
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int i;
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/* If amplitude is non-default, update it. */
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if (rs9->pll_amplitude != RS9_REG_SS_AMP_DEFAULT) {
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dm_i2c_reg_clrset(dev, RS9_REG_SS, RS9_REG_SS_AMP_MASK,
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rs9->pll_amplitude);
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}
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/* If SSC is non-default, update it. */
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if (rs9->pll_ssc != RS9_REG_SS_SSC_DEFAULT) {
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dm_i2c_reg_clrset(dev, RS9_REG_SS, RS9_REG_SS_SSC_MASK,
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rs9->pll_ssc);
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}
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for (i = 0; i < rs9->chip_info->num_clks; i++) {
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u8 dif = rs9_calc_dif(rs9, i);
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if (rs9->clk_dif_sr & dif)
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continue;
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dm_i2c_reg_clrset(dev, RS9_REG_SR, dif,
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rs9->clk_dif_sr & dif);
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}
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}
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static int clk_rs9_probe(struct udevice *dev)
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{
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struct rs9_driver_data *rs9 = dev_get_priv(dev);
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struct clk *clk;
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u8 vid, did;
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int i, ret;
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rs9->i2c = dev;
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rs9->chip_info = (struct rs9_chip_info *)dev_get_driver_data(dev);
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if (!rs9->chip_info)
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return -EINVAL;
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clk = devm_clk_get(dev, NULL);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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rs9->rate = clk_get_rate(clk);
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/* Fetch common configuration from DT (if specified) */
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ret = rs9_get_common_config(rs9);
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if (ret)
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return ret;
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/* Fetch DIFx output configuration from DT (if specified) */
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for (i = 0; i < rs9->chip_info->num_clks; i++) {
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ret = rs9_get_output_config(rs9, i);
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if (ret)
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return ret;
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}
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/* Always read back 1 Byte via I2C */
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ret = rs9_write(dev, RS9_REG_BCP, 1);
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if (ret < 0)
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return ret;
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ret = rs9_read(dev, RS9_REG_VID, &vid);
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if (ret < 0)
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return ret;
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ret = rs9_read(dev, RS9_REG_DID, &did);
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if (ret < 0)
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return ret;
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vid &= RS9_REG_VID_MASK;
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if (vid != RS9_REG_VID_IDT || did != rs9->chip_info->did) {
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dev_err(dev, "Incorrect VID/DID: %#02x, %#02x. Expected %#02x, %#02x\n",
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vid, did, RS9_REG_VID_IDT, rs9->chip_info->did);
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return -ENODEV;
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}
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rs9_update_config(rs9);
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return 0;
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}
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static const struct rs9_chip_info renesas_9fgv0241_info = {
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.num_clks = 2,
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.outshift = 1,
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.did = RS9_REG_DID_TYPE_FGV | 0x02,
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};
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static const struct rs9_chip_info renesas_9fgv0441_info = {
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.num_clks = 4,
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.outshift = 0,
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.did = RS9_REG_DID_TYPE_FGV | 0x04,
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};
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static const struct rs9_chip_info renesas_9fgv0841_info = {
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.num_clks = 8,
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.outshift = 0,
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.did = RS9_REG_DID_TYPE_FGV | 0x08,
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};
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static const struct udevice_id clk_rs9_of_match[] = {
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{ .compatible = "renesas,9fgv0241", .data = (ulong)&renesas_9fgv0241_info },
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{ .compatible = "renesas,9fgv0441", .data = (ulong)&renesas_9fgv0441_info },
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{ .compatible = "renesas,9fgv0841", .data = (ulong)&renesas_9fgv0841_info },
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{ /* sentinel */ },
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};
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U_BOOT_DRIVER(clk_rs9) = {
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.name = "clk-renesas-pcie-9series",
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.id = UCLASS_CLK,
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.of_match = clk_rs9_of_match,
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.ops = &clk_rs9_ops,
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.probe = clk_rs9_probe,
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.priv_auto = sizeof(struct rs9_driver_data),
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};
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