vhaudiquet/u-boot-krane
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge patch series "Fix J7200 kernel boot when using upstream u-boot"

Browse Source 
Reid Tonking <reidt@ti.com> says:

Since the 09.01.00.002 release of ti-linux-firmware [0] upstream uboot
has led to the kernel hanging during boot [1] for the TI J7200 S0C. The
issue was found to be a few patches that had be added to ti-u-boot, but not
yet upstreamed. This series adds the missing two patches to allow upstream
u-boot to boot the kernel properly [2].

[0] https://git.ti.com/cgit/processor-firmware/ti-linux-firmware/commit/?h=ti-linux-firmware-next&id=952fd03e36a50ec070e73560dc1060102d637ce0

Boot logs:
[1] https://gist.github.com/reidt1/5f4e85a0db258bcf20d7168bd0caebd0
[2] https://gist.github.com/reidt1/e950dc97f15ad0a09623d64f81edac39

Links to patches on ti-u-boot:
https://git.ti.com/cgit/ti-u-boot/ti-u-boot/commit/?h=ti-u-boot-2023.04-next&id=d878fbef4d4460e87608d8d2dfe5311499de49c5
https://git.ti.com/cgit/ti-u-boot/ti-u-boot/commit/?h=ti-u-boot-2023.04-next&id=543e735fe495be233a8a75b19b3d7f8ed44251e0
This commit is contained in:
Tom Rini
2023-12-19 11:42:03 -05:00
parent 9cfef5fcfb 3d6cb03905
commit 936d0f9dd7
2 changed files with 13 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+2 -1
View File
@@ -24,7 +24,8 @@
<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
clocks = <&k3_clks 61 1>;
assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 323 0>;
assigned-clock-parents= <0>, <0>, <&k3_clks 323 2>;
assigned-clock-rates = <2000000000>, <200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
arch/arm/mach-k3/r5/j7200/clk-data.c
+11 -2
View File
@@ -141,6 +141,11 @@ static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
"hsdiv4_16fft_main_0_hsdivout0_clk",
};
static const char * const main_pll8_sel_extwave_out0_parents[] = {
"pllfracf_ssmod_16fft_main_8_foutvcop_clk",
"hsdiv0_16fft_main_8_hsdivout0_clk",
};
static const char * const mcu_obsclk_outmux_out0_parents[] = {
"mcu_obsclk_div_out0",
"gluelogic_hfosc0_clkout",
@@ -396,6 +401,7 @@ static const struct clk_data clk_list[] = {
CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0),
CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
CLK_MUX("main_pll8_sel_extwave_out0", main_pll8_sel_extwave_out0_parents, 2, 0x688040, 0, 1, 0),
CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0, 0),
CLK_MUX("mcu_obsclk_outmux_out0", mcu_obsclk_outmux_out0_parents, 2, 0x43008000, 24, 1, 0),
CLK_PLL("pllfracf_ssmod_16fft_main_4_foutvcop_clk", "main_pll4_xref_sel_out0", 0x684000, 0),
@@ -545,11 +551,14 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(288, 14, "board_0_hfosc1_clk_out"),
DEV_CLK(288, 15, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(288, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(323, 0, "main_pll8_sel_extwave_out0"),
DEV_CLK(323, 1, "pllfracf_ssmod_16fft_main_8_foutvcop_clk"),
DEV_CLK(323, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
};
const struct ti_k3_clk_platdata j7200_clk_platdata = {
.clk_list = clk_list,
.clk_list_cnt = 109,
.clk_list_cnt = ARRAY_SIZE(clk_list),
.soc_dev_clk_data = soc_dev_clk_data,
.soc_dev_clk_data_cnt = 129,
.soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data),
};