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Merge tag 'xilinx-for-v2026.10-rc1-v3' of https://git.u-boot-project.org/u-boot/custodians/u-boot-amd

Browse Source 
AMD/Xilinx/FPGA changes for v2026.10-rc1 v3

AMD:
- Firmware interface decoupling (part 1)

ZynqMP:
- DT updates
- Add TCG variant detection

Versal/Versal2:
- Drop DDR MMU mapping and map it dynamically

tools:
- Add register initialization to mkimage

MAINTAINERS:
- Clean Zynq/ZynqMP fragments

ufs:
- Fix driver reregistration

fpga:
- altera: Simplify driver conditional compilation selection
This commit is contained in:
Tom Rini
2026-07-08 10:13:24 -06:00
parent ee5d46b45e 34c89c840c
commit 913fedc816
69 changed files with 1833 additions and 1045 deletions
Download Patch File Download Diff File Expand all files Collapse all files
MAINTAINERS
+5 -53
View File
@@ -881,72 +881,24 @@ T: git git://github.com/ARM-software/u-boot.git
F: drivers/misc/vexpress_config.c
N: vexpress
ARM ZYNQ
ARM ZYNQ and ZYNQMP
M: Michal Simek <monstr@monstr.eu>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/mach-zynq/
F: doc/board/xilinx/
F: doc/device-tree-bindings/video/syncoam,seps525.txt
F: drivers/clk/clk_zynq.c
F: drivers/fpga/zynqpl.c
F: drivers/gpio/zynq_gpio.c
F: drivers/i2c/i2c-cdns.c
F: drivers/i2c/muxes/pca954x.c
F: drivers/i2c/zynq_i2c.c
F: drivers/mmc/zynq_sdhci.c
F: drivers/mtd/nand/raw/zynq_nand.c
F: drivers/net/phy/ethernet_id.c
F: drivers/net/phy/xilinx_phy.c
F: drivers/net/zynq_gem.c
F: drivers/pinctrl/pinctrl-zynqmp.c
F: drivers/serial/serial_zynq.c
F: drivers/spi/zynq_qspi.c
F: drivers/spi/zynq_spi.c
F: drivers/usb/host/ehci-zynq.c
F: drivers/watchdog/cdns_wdt.c
F: include/zynqpl.h
F: tools/zynqimage.c
N: zynq
ARM ZYNQMP
M: Michal Simek <michal.simek@amd.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/mach-zynqmp/
F: drivers/bootcount/bootcount_zynqmp.c
F: drivers/clk/clk_zynqmp.c
F: driver/firmware/firmware-zynqmp.c
F: drivers/fpga/zynqpl.c
F: doc/board/xilinx/
F: doc/device-tree-bindings/video/syncoam,seps525.txt
F: drivers/gpio/gpio_slg7xl45106.c
F: drivers/gpio/zynq_gpio.c
F: drivers/gpio/zynqmp_gpio_modepin.c
F: drivers/i2c/i2c-cdns.c
F: drivers/i2c/muxes/pca954x.c
F: drivers/i2c/zynq_i2c.c
F: drivers/mailbox/zynqmp-ipi.c
F: drivers/mmc/zynq_sdhci.c
F: drivers/mtd/nand/raw/zynq_nand.c
F: drivers/net/phy/ethernet_id.c
F: drivers/net/phy/xilinx_phy.c
F: drivers/net/zynq_gem.c
F: drivers/phy/phy-zynqmp.c
F: drivers/power/domain/zynqmp-power-domain.c
F: drivers/pwm/pwm-cadence-ttc.c
F: drivers/serial/serial_zynq.c
F: drivers/reset/reset-zynqmp.c
F: drivers/rtc/zynqmp_rtc.c
F: drivers/soc/soc_xilinx_zynqmp.c
F: drivers/spi/zynq_qspi.c
F: drivers/spi/zynq_spi.c
F: drivers/timer/cadence-ttc.c
F: drivers/video/seps525.c
F: drivers/video/zynqmp/
F: drivers/watchdog/cdns_wdt.c
F: include/zynqmppl.h
F: include/zynqmp_firmware.h
F: tools/zynqmp*
N: ultra96
N: zynqmp
N: zynq
ARM ZYNQMP R5
M: Michal Simek <michal.simek@amd.com>
arch/arm/dts/zynqmp-clk-ccf.dtsi
+14 -1
View File
@@ -3,7 +3,7 @@
* Clock specification for Xilinx ZynqMP
*
* (C) Copyright 2017 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -49,6 +49,14 @@
clock-frequency = <27000000>;
clock-output-names = "aux_ref_clk";
};
rtc_clk: rtc-clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "rtc_clk";
};
};
&zynqmp_firmware {
@@ -302,3 +310,8 @@
<&zynqmp_clk DP_AUDIO_REF>,
<&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */
};
&rtc {
clocks = <&rtc_clk>;
clock-names = "rtc";
};
arch/arm/dts/zynqmp-dlc21-revA.dts
+13 -4
View File
@@ -90,6 +90,9 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
nvmem-cells = <&eth_mac>;
nvmem-cell-names = "mac-address";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
@@ -119,10 +122,10 @@
"USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
"USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
"", "", /* 78 - 79 */
"", "", "", "", "", /* 80 - 84 */
"", "", "", "", "", /* 85 - 89 */
"", "", "", "", "", /* 90 - 94 */
"", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
"", "", "", "", "PMOD_0", /* 80 - 84 */
"PMOD_1", "PMOD_2", "PMOD_3", "PMOD_4", "PMOD_5", /* 85 -89 */
"PMOD_6", "PMOD_7", "", "", "", /* 90 - 94 */
"", "", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
"VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
"", "", "", "", "", /* 105 - 109 */
"SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */
@@ -153,6 +156,12 @@
eeprom: eeprom@50 { /* u46 */
compatible = "atmel,24c32";
reg = <0x50>;
#address-cells = <1>;
#size-cells = <1>;
eth_mac: mac-address@20 {
reg = <0x20 0x6>;
};
};
/* u138 - TUSB320IRWBR - for USB-C */
};
arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+20
View File
@@ -51,83 +51,103 @@
ina226-vccint {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
};
ina226-vcc-soc {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;
};
ina226-vcc-pmc {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;
};
ina226-vcc-ram {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
};
ina226-vcc-pslp {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;
};
ina226-vcc-psfp {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;
};
ina226-vccaux {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;
};
ina226-vccaux-pmc {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;
};
ina226-vcco-500 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;
};
ina226-vcco-501 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;
};
ina226-vcco-502 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;
};
ina226-vcco-503 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;
};
ina226-vcc-1v8 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;
};
ina226-vcc-3v3 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;
};
ina226-vcc-1v2-ddr4 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>,
<&vcc_1v2_ddr4 3>;
};
ina226-vcc-1v1-lp4 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
};
ina226-vadj-fmc {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
};
ina226-mgtyavcc {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;
};
ina226-mgtyavtt {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;
};
ina226-mgtyvccaux {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;
};
};
arch/arm/dts/zynqmp-g-a2197-00-revA.dts
+6
View File
@@ -40,26 +40,32 @@
ina226-u74 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
};
ina226-u75 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
};
ina226-u78 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
};
ina226-u79 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
};
ina226-u82 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>;
};
ina226-u84 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
};
};
arch/arm/dts/zynqmp-m-a2197-01-revA.dts
+6
View File
@@ -45,27 +45,33 @@
ina226-vcc-aux {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
};
ina226-vcc-ram {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
};
ina226-vcc1v1-lp4 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
};
ina226-vcc1v2-lp4 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
};
ina226-vdd1-1v8-lp4 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>,
<&vdd1_1v8_lp4 3>;
};
ina226-vcc0v6-lp4 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>;
};
};
arch/arm/dts/zynqmp-m-a2197-02-revA.dts
+5
View File
@@ -45,22 +45,27 @@
ina226-vcc-aux {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
};
ina226-vcc-ram {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
};
ina226-vcc1v1-lp4 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
};
ina226-vcc1v2-lp4 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
};
ina226-vdd1-1v8-lp4 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>,
<&vdd1_1v8_lp4 3>;
};
arch/arm/dts/zynqmp-m-a2197-03-revA.dts
+5
View File
@@ -45,22 +45,27 @@
ina226-vcc-aux {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
};
ina226-vcc-ram {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
};
ina226-vcc1v1-lp4 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
};
ina226-vcc1v2-lp4 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
};
ina226-vdd1-1v8-lp4 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>,
<&vdd1_1v8_lp4 3>;
};
arch/arm/dts/zynqmp-sc-revB.dts
+87 -84
View File
@@ -136,7 +136,6 @@
#size-cells = <0>;
phy0: ethernet-phy@1 {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
@@ -194,93 +193,97 @@
/* QSPI should also have PINCTRL setup */
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <40000000>; /* 40MHz */
partition@0 {
label = "Image Selector";
reg = <0x0 0x80000>; /* 512KB */
read-only;
lock;
};
partition@80000 {
label = "Image Selector Golden";
reg = <0x80000 0x80000>; /* 512KB */
read-only;
lock;
};
partition@100000 {
label = "Persistent Register";
reg = <0x100000 0x20000>; /* 128KB */
};
partition@120000 {
label = "Persistent Register Backup";
reg = <0x120000 0x20000>; /* 128KB */
};
partition@140000 {
label = "Open_1";
reg = <0x140000 0xc0000>; /* 768KB */
};
partition@200000 {
label = "Image A (FSBL, PMU, ATF, U-Boot)";
reg = <0x200000 0xd00000>; /* 13MB */
};
partition@f00000 {
label = "ImgSel Image A Catch";
reg = <0xf00000 0x80000>; /* 512KB */
read-only;
lock;
};
partition@f80000 {
label = "Image B (FSBL, PMU, ATF, U-Boot)";
reg = <0xf80000 0xd00000>; /* 13MB */
};
partition@1c80000 {
label = "ImgSel Image B Catch";
reg = <0x1c80000 0x80000>; /* 512KB */
read-only;
lock;
};
partition@1d00000 {
label = "Open_2";
reg = <0x1d00000 0x100000>; /* 1MB */
};
partition@1e00000 {
label = "Recovery Image";
reg = <0x1e00000 0x200000>; /* 2MB */
read-only;
lock;
};
partition@2000000 {
label = "Recovery Image Backup";
reg = <0x2000000 0x200000>; /* 2MB */
read-only;
lock;
};
partition@2200000 {
label = "U-Boot storage variables";
reg = <0x2200000 0x20000>; /* 128KB */
};
partition@2220000 {
label = "U-Boot storage variables backup";
reg = <0x2220000 0x20000>; /* 128KB */
};
partition@2240000 {
label = "SHA256";
reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
read-only;
lock;
};
partition@2280000 {
label = "Secure OS Storage";
reg = <0x2280000 0x20000>; /* 128KB */
};
partition@22a0000 {
label = "User";
reg = <0x22a0000 0x1d60000>; /* 29.375 MB */
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Image Selector";
reg = <0x0 0x80000>; /* 512KB */
read-only;
lock;
};
partition@80000 {
label = "Image Selector Golden";
reg = <0x80000 0x80000>; /* 512KB */
read-only;
lock;
};
partition@100000 {
label = "Persistent Register";
reg = <0x100000 0x20000>; /* 128KB */
};
partition@120000 {
label = "Persistent Register Backup";
reg = <0x120000 0x20000>; /* 128KB */
};
partition@140000 {
label = "Open_1";
reg = <0x140000 0xc0000>; /* 768KB */
};
partition@200000 {
label = "Image A (FSBL, PMU, ATF, U-Boot)";
reg = <0x200000 0xd00000>; /* 13MB */
};
partition@f00000 {
label = "ImgSel Image A Catch";
reg = <0xf00000 0x80000>; /* 512KB */
read-only;
lock;
};
partition@f80000 {
label = "Image B (FSBL, PMU, ATF, U-Boot)";
reg = <0xf80000 0xd00000>; /* 13MB */
};
partition@1c80000 {
label = "ImgSel Image B Catch";
reg = <0x1c80000 0x80000>; /* 512KB */
read-only;
lock;
};
partition@1d00000 {
label = "Open_2";
reg = <0x1d00000 0x100000>; /* 1MB */
};
partition@1e00000 {
label = "Recovery Image";
reg = <0x1e00000 0x200000>; /* 2MB */
read-only;
lock;
};
partition@2000000 {
label = "Recovery Image Backup";
reg = <0x2000000 0x200000>; /* 2MB */
read-only;
lock;
};
partition@2200000 {
label = "U-Boot storage variables";
reg = <0x2200000 0x20000>; /* 128KB */
};
partition@2220000 {
label = "U-Boot storage variables backup";
reg = <0x2220000 0x20000>; /* 128KB */
};
partition@2240000 {
label = "SHA256";
reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
read-only;
lock;
};
partition@2280000 {
label = "Secure OS Storage";
reg = <0x2280000 0x20000>; /* 128KB */
};
partition@22a0000 {
label = "User";
reg = <0x22a0000 0x1d60000>; /* 29.375 MB */
};
};
};
};
arch/arm/dts/zynqmp-sc-revC.dts
-1
View File
@@ -23,7 +23,6 @@
#size-cells = <0>;
phy0: ethernet-phy@1 { /* ADI1300 */
#phy-cells = <1>;
compatible = "ethernet-phy-id0283.bc30";
reg = <1>;
adi,rx-internal-delay-ps = <2400>;
arch/arm/dts/zynqmp-sc-vek280-revA.dtso
+2 -3
View File
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP VEK280 revA
*
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc
* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -13,8 +13,7 @@
/plugin/;
&{/} {
compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-vek280-revA",
"xlnx,zynqmp-vek280", "xlnx,zynqmp";
compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-sc-vek280", "xlnx,zynqmp";
vc7_xin: vc7-xin {
compatible = "fixed-clock";
arch/arm/dts/zynqmp-sc-vek280-revB.dtso
+2 -3
View File
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP VEK280 revB
*
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc
* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -10,6 +10,5 @@
#include "zynqmp-sc-vek280-revA.dtso"
&{/} {
compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB",
"xlnx,zynqmp-vek280", "xlnx,zynqmp";
compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-sc-vek280", "xlnx,zynqmp";
};
arch/arm/dts/zynqmp-sc-vhk158-revA.dtso
+2 -3
View File
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP VHK158 revA
*
* (C) Copyright 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -14,8 +14,7 @@
/plugin/;
&{/} {
compatible = "xlnx,zynqmp-sc-vhk158-revA", "xlnx,zynqmp-vhk158-revA",
"xlnx,zynqmp-vhk158", "xlnx,zynqmp";
compatible = "xlnx,zynqmp-sc-vhk158-revA", "xlnx,zynqmp-sc-vhk158", "xlnx,zynqmp";
vc7_xin: vc7-xin {
compatible = "fixed-clock";
arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso
+18 -2
View File
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP VM-P-M1369-00
*
* Copyright (C) 2024, Advanced Micro Devices, Inc.
* Copyright (C) 2024-2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -18,66 +18,82 @@
ina226-u19 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_soc_ina 0>, <&vcc_soc_ina 1>, <&vcc_soc_ina 2>;
};
ina226-u287 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_ram_ina 0>, <&vcc_ram_ina 1>, <&vcc_ram_ina 2>;
};
ina226-u288 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_pslp_ina 0>, <&vcc_pslp_ina 1>, <&vcc_pslp_ina 2>;
};
ina226-u289 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vccaux_ina 0>, <&vccaux_ina 1>, <&vccaux_ina 2>;
};
ina226-u290 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vccaux_pmc_ina 0>, <&vccaux_pmc_ina 1>, <&vccaux_pmc_ina 2>;
};
ina226-u291 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcco_500_ina 0>, <&vcco_500_ina 1>, <&vcco_500_ina 2>;
};
ina226-u292 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcco_501_ina 0>, <&vcco_501_ina 1>, <&vcco_501_ina 2>;
};
ina226-u293 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcco_502_ina 0>, <&vcco_502_ina 1>, <&vcco_502_ina 2>;
};
ina226-u294 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcco_503_ina 0>, <&vcco_503_ina 1>, <&vcco_503_ina 2>;
};
ina226-u295 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_ddr5_rdimm_ina 0>, <&vcc_ddr5_rdimm_ina 1>, <&vcc_ddr5_rdimm_ina 2>;
};
ina226-u298 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&lp5_1v0_ina 0>, <&lp5_1v0_ina 1>, <&lp5_1v0_ina 2>;
};
ina226-u296 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_fmc_ina 0>, <&vcc_fmc_ina 1>, <&vcc_fmc_ina 2>;
};
ina226-u299 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&gtm_avcc_ina 0>, <&gtm_avcc_ina 1>, <&gtm_avcc_ina 2>;
};
ina226-u300 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&gtm_avtt_ina 0>, <&gtm_avtt_ina 1>, <&gtm_avtt_ina 2>;
};
ina226-u301 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&gtm_avccaux_ina 0>, <&gtm_avccaux_ina 1>, <&gtm_avccaux_ina 2>;
};
ina226-u297 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_mipi_ina 0>, <&vcc_mipi_ina 1>, <&vcc_mipi_ina 2>;
};
};
@@ -393,7 +409,7 @@
};
/* connected via J425 connector
ucd90320: power-sequencer@73 { // u16
ucd90320: power-sequencer@73 { // u16
compatible = "ti,ucd90320";
reg = <0x73>;
};*/
arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso
+16
View File
@@ -22,66 +22,82 @@
ina226-u1700 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_ram_ina 0>, <&vcc_ram_ina 1>, <&vcc_ram_ina 2>;
};
ina226-u1732 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc_lpd_ina 0>, <&vcc_lpd_ina 1>, <&vcc_lpd_ina 2>;
};
ina226-u1733 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vccaux_ina 0>, <&vccaux_ina 1>, <&vccaux_ina 2>;
};
ina226-u1736 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vccaux_lpd_ina 0>, <&vccaux_lpd_ina 1>, <&vccaux_lpd_ina 2>;
};
ina226-u1737 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcco_500_ina 0>, <&vcco_500_ina 1>, <&vcco_500_ina 2>;
};
ina226-u1739 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcco_501_ina 0>, <&vcco_501_ina 1>, <&vcco_501_ina 2>;
};
ina226-u1741 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcco_502_ina 0>, <&vcco_502_ina 1>, <&vcco_502_ina 2>;
};
ina226-u1743 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcco_503_ina 0>, <&vcco_503_ina 1>, <&vcco_503_ina 2>;
};
ina226-u1745 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcco_700_ina 0>, <&vcco_700_ina 1>, <&vcco_700_ina 2>;
};
ina226-u1747 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcco_706_ina 0>, <&vcco_706_ina 1>, <&vcco_706_ina 2>;
};
ina226-u1750 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&gtyp_avcc_ina 0>, <&gtyp_avcc_ina 1>, <&gtyp_avcc_ina 2>;
};
ina226-u1752 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&gtyp_avtt_ina 0>, <&gtyp_avtt_ina 1>, <&gtyp_avtt_ina 2>;
};
ina226-u1754 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&gtyp_avccaux_ina 0>, <&gtyp_avccaux_ina 1>, <&gtyp_avccaux_ina 2>;
};
ina226-u1756 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&gtm_avcc_ina 0>, <&gtm_avcc_ina 1>, <&gtm_avcc_ina 2>;
};
ina226-u1758 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&gtm_avtt_ina 0>, <&gtm_avtt_ina 1>, <&gtm_avtt_ina 2>;
};
ina226-u1760 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&gtm_avccaux_ina 0>, <&gtm_avccaux_ina 1>, <&gtm_avccaux_ina 2>;
};
arch/arm/dts/zynqmp-sc-vpk120-revB.dtso
+2 -3
View File
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP VPK120 revB
*
* (C) Copyright 2021 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -14,8 +14,7 @@
/plugin/;
&{/} {
compatible = "xlnx,zynqmp-sc-vpk120-revB", "xlnx,zynqmp-vpk120-revB",
"xlnx,zynqmp-vpk120", "xlnx,zynqmp";
compatible = "xlnx,zynqmp-sc-vpk120-revB", "xlnx,zynqmp-sc-vpk120", "xlnx,zynqmp";
};
&i2c0 {
arch/arm/dts/zynqmp-sc-vpk180-revA.dtso
+2 -3
View File
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP VPK180 revA
*
* (C) Copyright 2021 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -14,8 +14,7 @@
/plugin/;
&{/} {
compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-vpk180-revA",
"xlnx,zynqmp-vpk180", "xlnx,zynqmp";
compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-sc-vpk180", "xlnx,zynqmp";
vc7_xin: vc7-xin {
compatible = "fixed-clock";
arch/arm/dts/zynqmp-sc-vpk180-revB.dtso
+3 -4
View File
@@ -1,9 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx ZynqMP VPK180 revA
* dts file for Xilinx ZynqMP VPK180 revB
*
* (C) Copyright 2021 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -14,8 +14,7 @@
/plugin/;
&{/} {
compatible = "xlnx,zynqmp-sc-vpk180-revB", "xlnx,zynqmp-vpk180-revB",
"xlnx,zynqmp-vpk180", "xlnx,zynqmp";
compatible = "xlnx,zynqmp-sc-vpk180-revB", "xlnx,zynqmp-sc-vpk180", "xlnx,zynqmp";
vc7_xin: vc7-xin {
compatible = "fixed-clock";
arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
+20 -2
View File
@@ -50,6 +50,24 @@
gpio-controller;
gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
};
vdd_usb_hub: regulator-vdd-usb-hub {
compatible = "regulator-fixed";
regulator-name = "vdd_usb_hub";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vdd2_usb_hub: regulator-vdd2-usb-hub {
compatible = "regulator-fixed";
regulator-name = "vdd2_usb_hub";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
};
&can0 {
@@ -76,7 +94,6 @@
slg7xl45106: gpio@11 { /* u13 - reset logic */
compatible = "dlg,slg7xl45106";
reg = <0x11>;
label = "resetchip";
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "USB0_PHY_RESET_B", "",
@@ -124,6 +141,8 @@
peer-hub = <&hub_3_0>;
i2c-bus = <&hub>;
reset-gpios = <&slg_delay 0 10000 10000>;
vdd-supply = <&vdd_usb_hub>;
vdd2-supply = <&vdd2_usb_hub>;
};
/* 3.0 hub on port 2 */
@@ -148,7 +167,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@8 { /* Adin u31 */
#phy-cells = <1>;
compatible = "ethernet-phy-id0283.bc30";
reg = <8>;
adi,rx-internal-delay-ps = <2000>;
arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
+23 -3
View File
@@ -66,6 +66,7 @@
#clock-cells = <0>;
clock-frequency = <25000000>;
};
dpcon {
compatible = "dp-connector";
label = "P11";
@@ -85,6 +86,24 @@
gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>,
<&slg7xl45106 4 GPIO_ACTIVE_LOW>;
};
vdd_usb_hub: regulator-vdd-usb-hub {
compatible = "regulator-fixed";
regulator-name = "vdd_usb_hub";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vdd2_usb_hub: regulator-vdd2-usb-hub {
compatible = "regulator-fixed";
regulator-name = "vdd2_usb_hub";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
};
&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
@@ -105,7 +124,6 @@
slg7xl45106: gpio@11 { /* u19 - reset logic */
compatible = "dlg,slg7xl45106";
reg = <0x11>;
label = "resetchip";
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B",
@@ -196,6 +214,8 @@
peer-hub = <&hub_3_0>;
i2c-bus = <&hub_1>;
reset-gpios = <&slg_delay 0 10000 10000>;
vdd-supply = <&vdd_usb_hub>;
vdd2-supply = <&vdd2_usb_hub>;
};
/* 3.0 hub on port 2 */
@@ -233,6 +253,8 @@
peer-hub = <&hub1_3_0>;
i2c-bus = <&hub_2>;
reset-gpios = <&slg_delay 1 10000 10000>;
vdd-supply = <&vdd_usb_hub>;
vdd2-supply = <&vdd2_usb_hub>;
};
/* 3.0 hub on port 2 */
@@ -265,7 +287,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@4 { /* u81 */
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <4>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
@@ -277,7 +298,6 @@
reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>;
};
phy1: ethernet-phy@8 { /* u36 */
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <8>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
+22 -3
View File
@@ -86,6 +86,24 @@
gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>,
<&slg7xl45106 4 GPIO_ACTIVE_LOW>;
};
vdd_usb_hub: regulator-vdd-usb-hub {
compatible = "regulator-fixed";
regulator-name = "vdd_usb_hub";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vdd2_usb_hub: regulator-vdd2-usb-hub {
compatible = "regulator-fixed";
regulator-name = "vdd2_usb_hub";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
};
&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
@@ -106,7 +124,6 @@
slg7xl45106: gpio@11 { /* u19 - reset logic */
compatible = "dlg,slg7xl45106";
reg = <0x11>;
label = "resetchip";
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B",
@@ -197,6 +214,8 @@
peer-hub = <&hub_3_0>;
i2c-bus = <&hub_1>;
reset-gpios = <&slg_delay 0 10000 10000>;
vdd-supply = <&vdd_usb_hub>;
vdd2-supply = <&vdd2_usb_hub>;
};
/* 3.0 hub on port 2 */
@@ -234,6 +253,8 @@
peer-hub = <&hub1_3_0>;
i2c-bus = <&hub_2>;
reset-gpios = <&slg_delay 1 10000 10000>;
vdd-supply = <&vdd_usb_hub>;
vdd2-supply = <&vdd2_usb_hub>;
};
/* 3.0 hub on port 2 */
@@ -266,7 +287,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@4 { /* u81 */
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <4>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
@@ -278,7 +298,6 @@
reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>;
};
phy1: ethernet-phy@8 { /* u36 */
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <8>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
+38 -19
View File
@@ -85,6 +85,24 @@
gpio-controller;
gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
};
vdd_usb_hub: regulator-vdd-usb-hub {
compatible = "regulator-fixed";
regulator-name = "vdd_usb_hub";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vdd2_usb_hub: regulator-vdd2-usb-hub {
compatible = "regulator-fixed";
regulator-name = "vdd2_usb_hub";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
};
&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
@@ -169,6 +187,8 @@
reg = <1>;
peer-hub = <&hub_3_0>;
reset-gpios = <&slg_delay 0 10000 10000>;
vdd-supply = <&vdd_usb_hub>;
vdd2-supply = <&vdd2_usb_hub>;
};
/* 3.0 hub on port 2 */
@@ -209,7 +229,6 @@
#size-cells = <0>;
phy0: ethernet-phy@1 {
#phy-cells = <1>;
reg = <1>;
compatible = "ethernet-phy-id2000.a231";
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
@@ -227,23 +246,23 @@
status = "okay";
pinctrl_gpio0_default: gpio0-default {
conf {
groups = "gpio0_38_grp";
bias-pull-up;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf {
groups = "gpio0_38_grp";
bias-pull-up;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "gpio0_38_grp";
function = "gpio0";
};
mux {
groups = "gpio0_38_grp";
function = "gpio0";
};
conf-tx {
pins = "MIO38";
bias-disable;
output-enable;
};
};
conf-tx {
pins = "MIO38";
bias-disable;
output-enable;
};
};
pinctrl_uart1_default: uart1-default {
conf {
@@ -402,9 +421,9 @@
};
&gpio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio0_default>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio0_default>;
};
&uart1 {
arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
+21 -2
View File
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* dts file for KV260 revA Carrier Card
* dts file for KV260 revB Carrier Card
*
* (C) Copyright 2020 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
@@ -81,6 +81,24 @@
gpio-controller;
gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
};
vdd_usb_hub: regulator-vdd-usb-hub {
compatible = "regulator-fixed";
regulator-name = "vdd_usb_hub";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vdd2_usb_hub: regulator-vdd2-usb-hub {
compatible = "regulator-fixed";
regulator-name = "vdd2_usb_hub";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
};
&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
@@ -156,6 +174,8 @@
peer-hub = <&hub_3_0>;
i2c-bus = <&hub>;
reset-gpios = <&slg_delay 0 10000 10000>;
vdd-supply = <&vdd_usb_hub>;
vdd2-supply = <&vdd2_usb_hub>;
};
/* 3.0 hub on port 2 */
@@ -200,7 +220,6 @@
#size-cells = <0>;
phy0: ethernet-phy@1 {
#phy-cells = <1>;
reg = <1>;
compatible = "ethernet-phy-id2000.a231";
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
arch/arm/dts/zynqmp-sm-k24-revA.dts
+6 -1
View File
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP SM-K24 RevA
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
* (C) Copyright 2022, Advanced Micro Devices, Inc.
* (C) Copyright 2022-2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -21,3 +21,8 @@
reg = <0 0 0 0x80000000>;
};
};
&cma {
size = <0x0 0x4000000>;
alignment = <0x0 0x4000000>;
};
arch/arm/dts/zynqmp-sm-k26-revA.dts
+10 -1
View File
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
* (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
* (C) Copyright 2023 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -61,6 +61,15 @@
reg = <0x0 0x7ff00000 0x0 0x100000>;
no-map;
};
cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x8000000>;
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
linux,cma-default;
};
};
gpio-keys {
arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
+21 -17
View File
@@ -63,23 +63,27 @@
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <166000000>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "qspi-boot-bin";
reg = <0x00000 0x60000>;
};
partition@60000 {
label = "qspi-u-boot-itb";
reg = <0x60000 0x100000>;
};
partition@160000 {
label = "qspi-u-boot-env";
reg = <0x160000 0x20000>;
};
partition@200000 {
label = "qspi-rootfs";
reg = <0x200000 0x1e00000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "qspi-boot-bin";
reg = <0x00000 0x60000>;
};
partition@60000 {
label = "qspi-u-boot-itb";
reg = <0x60000 0x100000>;
};
partition@160000 {
label = "qspi-u-boot-env";
reg = <0x160000 0x20000>;
};
partition@200000 {
label = "qspi-rootfs";
reg = <0x200000 0x1e00000>;
};
};
};
};
arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
+9 -5
View File
@@ -88,15 +88,19 @@
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-tx-bus-width = <4>; /* maybe 4 here */
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
partition@0 { /* for testing purpose */
label = "qspi";
reg = <0 0x4000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 { /* for testing purpose */
label = "qspi";
reg = <0 0x4000000>;
};
};
};
};
arch/arm/dts/zynqmp-vpk120-revA.dts
+9 -5
View File
@@ -88,15 +88,19 @@
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
partition@0 { /* for testing purpose */
label = "qspi";
reg = <0 0x4000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 { /* for testing purpose */
label = "qspi";
reg = <0 0x4000000>;
};
};
};
};
arch/arm/dts/zynqmp-zc1232-revA.dts
+37 -18
View File
@@ -31,6 +31,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x8000000>;
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
linux,cma-default;
};
};
};
&dcc {
@@ -40,28 +55,32 @@
&qspi {
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB FIXME */
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
};
};
};
};
arch/arm/dts/zynqmp-zc1254-revA.dts
+36 -17
View File
@@ -32,6 +32,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x8000000>;
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
linux,cma-default;
};
};
};
&dcc {
@@ -42,27 +57,31 @@
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
};
};
};
};
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+37 -18
View File
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP zc1751-xm015-dc1
*
* (C) Copyright 2015 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -41,6 +41,21 @@
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x8000000>;
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
linux,cma-default;
};
};
clock_si5338_0: clk27 { /* u55 SI5338-GM */
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -357,28 +372,32 @@
num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
#address-cells = <1>;
#size-cells = <1>;
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
};
};
};
};
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+90 -61
View File
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP zc1751-xm016-dc2
*
* (C) Copyright 2015 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -39,6 +39,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x8000000>;
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
linux,cma-default;
};
};
};
&can0 {
@@ -138,8 +153,6 @@
nand@0 {
reg = <0x0>;
#address-cells = <0x2>;
#size-cells = <0x1>;
nand-ecc-mode = "hw";
nand-rb = <0>;
label = "main-storage-0";
@@ -147,35 +160,39 @@
nand-ecc-strength = <24>;
nand-on-flash-bbt;
partition@0 { /* for testing purpose */
label = "nand-fsbl-uboot";
reg = <0x0 0x0 0x400000>;
};
partition@1 { /* for testing purpose */
label = "nand-linux";
reg = <0x0 0x400000 0x1400000>;
};
partition@2 { /* for testing purpose */
label = "nand-device-tree";
reg = <0x0 0x1800000 0x400000>;
};
partition@3 { /* for testing purpose */
label = "nand-rootfs";
reg = <0x0 0x1c00000 0x1400000>;
};
partition@4 { /* for testing purpose */
label = "nand-bitstream";
reg = <0x0 0x3000000 0x400000>;
};
partition@5 { /* for testing purpose */
label = "nand-misc";
reg = <0x0 0x3400000 0xfcc00000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <2>;
#size-cells = <1>;
partition@0 { /* for testing purpose */
label = "nand-fsbl-uboot";
reg = <0x0 0x0 0x400000>;
};
partition@1 { /* for testing purpose */
label = "nand-linux";
reg = <0x0 0x400000 0x1400000>;
};
partition@2 { /* for testing purpose */
label = "nand-device-tree";
reg = <0x0 0x1800000 0x400000>;
};
partition@3 { /* for testing purpose */
label = "nand-rootfs";
reg = <0x0 0x1c00000 0x1400000>;
};
partition@4 { /* for testing purpose */
label = "nand-bitstream";
reg = <0x0 0x3000000 0x400000>;
};
partition@5 { /* for testing purpose */
label = "nand-misc";
reg = <0x0 0x3400000 0xfcc00000>;
};
};
};
nand@1 {
reg = <0x1>;
#address-cells = <0x2>;
#size-cells = <0x1>;
nand-ecc-mode = "hw";
nand-rb = <0>;
label = "main-storage-1";
@@ -183,29 +200,35 @@
nand-ecc-strength = <24>;
nand-on-flash-bbt;
partition@0 { /* for testing purpose */
label = "nand1-fsbl-uboot";
reg = <0x0 0x0 0x400000>;
};
partition@1 { /* for testing purpose */
label = "nand1-linux";
reg = <0x0 0x400000 0x1400000>;
};
partition@2 { /* for testing purpose */
label = "nand1-device-tree";
reg = <0x0 0x1800000 0x400000>;
};
partition@3 { /* for testing purpose */
label = "nand1-rootfs";
reg = <0x0 0x1c00000 0x1400000>;
};
partition@4 { /* for testing purpose */
label = "nand1-bitstream";
reg = <0x0 0x3000000 0x400000>;
};
partition@5 { /* for testing purpose */
label = "nand1-misc";
reg = <0x0 0x3400000 0xfcc00000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <2>;
#size-cells = <1>;
partition@0 { /* for testing purpose */
label = "nand1-fsbl-uboot";
reg = <0x0 0x0 0x400000>;
};
partition@1 { /* for testing purpose */
label = "nand1-linux";
reg = <0x0 0x400000 0x1400000>;
};
partition@2 { /* for testing purpose */
label = "nand1-device-tree";
reg = <0x0 0x1800000 0x400000>;
};
partition@3 { /* for testing purpose */
label = "nand1-rootfs";
reg = <0x0 0x1c00000 0x1400000>;
};
partition@4 { /* for testing purpose */
label = "nand1-bitstream";
reg = <0x0 0x3000000 0x400000>;
};
partition@5 { /* for testing purpose */
label = "nand1-misc";
reg = <0x0 0x3400000 0xfcc00000>;
};
};
};
};
@@ -503,15 +526,18 @@
pinctrl-0 = <&pinctrl_spi0_default>;
spi0_flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst,sst25wf080", "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "spi0-data";
reg = <0x0 0x100000>;
partition@0 {
label = "spi0-data";
reg = <0x0 0x100000>;
};
};
};
};
@@ -523,15 +549,18 @@
pinctrl-0 = <&pinctrl_spi1_default>;
spi1_flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";
spi-max-frequency = <20000000>;
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "spi1-data";
reg = <0x0 0x84000>;
partition@0 {
label = "spi1-data";
reg = <0x0 0x84000>;
};
};
};
};
arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
+72 -50
View File
@@ -39,6 +39,21 @@
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x8000000>;
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
linux,cma-default;
};
};
clock_si5338_2: clk26 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -133,8 +148,6 @@
nand@0 {
reg = <0x0>;
#address-cells = <0x2>;
#size-cells = <0x1>;
nand-ecc-mode = "hw";
nand-rb = <0>;
label = "main-storage-0";
@@ -142,65 +155,74 @@
nand-ecc-strength = <24>;
nand-on-flash-bbt;
partition@0 { /* for testing purpose */
label = "nand-fsbl-uboot";
reg = <0x0 0x0 0x400000>;
};
partition@1 { /* for testing purpose */
label = "nand-linux";
reg = <0x0 0x400000 0x1400000>;
};
partition@2 { /* for testing purpose */
label = "nand-device-tree";
reg = <0x0 0x1800000 0x400000>;
};
partition@3 { /* for testing purpose */
label = "nand-rootfs";
reg = <0x0 0x1c00000 0x1400000>;
};
partition@4 { /* for testing purpose */
label = "nand-bitstream";
reg = <0x0 0x3000000 0x400000>;
};
partition@5 { /* for testing purpose */
label = "nand-misc";
reg = <0x0 0x3400000 0xfcc00000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <2>;
#size-cells = <1>;
partition@0 { /* for testing purpose */
label = "nand-fsbl-uboot";
reg = <0x0 0x0 0x400000>;
};
partition@1 { /* for testing purpose */
label = "nand-linux";
reg = <0x0 0x400000 0x1400000>;
};
partition@2 { /* for testing purpose */
label = "nand-device-tree";
reg = <0x0 0x1800000 0x400000>;
};
partition@3 { /* for testing purpose */
label = "nand-rootfs";
reg = <0x0 0x1c00000 0x1400000>;
};
partition@4 { /* for testing purpose */
label = "nand-bitstream";
reg = <0x0 0x3000000 0x400000>;
};
partition@5 { /* for testing purpose */
label = "nand-misc";
reg = <0x0 0x3400000 0xfcc00000>;
};
};
};
nand@1 {
reg = <0x1>;
#address-cells = <0x2>;
#size-cells = <0x1>;
nand-ecc-mode = "hw";
nand-rb = <0>;
label = "main-storage-1";
nand-ecc-step-size = <1024>;
nand-ecc-strength = <24>;
nand-on-flash-bbt;
partitions {
compatible = "fixed-partitions";
#address-cells = <2>;
#size-cells = <1>;
partition@0 { /* for testing purpose */
label = "nand1-fsbl-uboot";
reg = <0x0 0x0 0x400000>;
};
partition@1 { /* for testing purpose */
label = "nand1-linux";
reg = <0x0 0x400000 0x1400000>;
};
partition@2 { /* for testing purpose */
label = "nand1-device-tree";
reg = <0x0 0x1800000 0x400000>;
};
partition@3 { /* for testing purpose */
label = "nand1-rootfs";
reg = <0x0 0x1c00000 0x1400000>;
};
partition@4 { /* for testing purpose */
label = "nand1-bitstream";
reg = <0x0 0x3000000 0x400000>;
};
partition@5 { /* for testing purpose */
label = "nand1-misc";
reg = <0x0 0x3400000 0xfcc00000>;
partition@0 { /* for testing purpose */
label = "nand1-fsbl-uboot";
reg = <0x0 0x0 0x400000>;
};
partition@1 { /* for testing purpose */
label = "nand1-linux";
reg = <0x0 0x400000 0x1400000>;
};
partition@2 { /* for testing purpose */
label = "nand1-device-tree";
reg = <0x0 0x1800000 0x400000>;
};
partition@3 { /* for testing purpose */
label = "nand1-rootfs";
reg = <0x0 0x1c00000 0x1400000>;
};
partition@4 { /* for testing purpose */
label = "nand1-bitstream";
reg = <0x0 0x3000000 0x400000>;
};
partition@5 { /* for testing purpose */
label = "nand1-misc";
reg = <0x0 0x3400000 0xfcc00000>;
};
};
};
};
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
+36 -17
View File
@@ -38,6 +38,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x8000000>;
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
linux,cma-default;
};
};
};
&can0 {
@@ -174,27 +189,31 @@
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
};
};
};
};
arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+15
View File
@@ -37,6 +37,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x8000000>;
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
linux,cma-default;
};
};
};
&fpd_dma_chan1 {
arch/arm/dts/zynqmp-zcu100-revC.dts
+18 -1
View File
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU100 revC
*
* (C) Copyright 2016 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Nathalie Chan King Choy
@@ -47,6 +47,21 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x8000000>;
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
linux,cma-default;
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
@@ -61,6 +76,7 @@
iio-hwmon {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
@@ -120,6 +136,7 @@
ina226 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
};
arch/arm/dts/zynqmp-zcu102-revA.dts
+55 -19
View File
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU102 RevA
*
* (C) Copyright 2015 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -45,6 +45,21 @@
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x8000000>;
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
linux,cma-default;
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
@@ -68,74 +83,92 @@
ina226-u76 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
};
ina226-u77 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
};
ina226-u78 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
};
ina226-u87 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
};
ina226-u85 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
};
ina226-u86 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
};
ina226-u93 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
};
ina226-u88 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
};
ina226-u15 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
};
ina226-u92 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
};
ina226-u79 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
};
ina226-u81 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
};
ina226-u80 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
};
ina226-u84 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
};
ina226-u16 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
};
ina226-u65 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
};
ina226-u74 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
};
ina226-u75 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
};
@@ -217,7 +250,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@21 {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <21>;
ti,rx-internal-delay = <0x8>;
@@ -987,28 +1019,32 @@
num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
};
};
};
};
arch/arm/dts/zynqmp-zcu102-revB.dts
-1
View File
@@ -19,7 +19,6 @@
phy-handle = <&phyc>;
mdio: mdio {
phyc: ethernet-phy@c {
#phy-cells = <0x1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
arch/arm/dts/zynqmp-zcu104-revA.dts
+37 -19
View File
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU104
*
* (C) Copyright 2017 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -43,6 +43,21 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x8000000>;
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
linux,cma-default;
};
};
clock_8t49n287_5: clk125 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -126,7 +141,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
@@ -453,27 +467,31 @@
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
};
};
};
};
arch/arm/dts/zynqmp-zcu104-revC.dts
+38 -19
View File
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU104
*
* (C) Copyright 2017 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -43,8 +43,24 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x8000000>;
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
linux,cma-default;
};
};
ina226 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
};
@@ -131,7 +147,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
@@ -465,27 +480,31 @@
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
};
};
};
};
arch/arm/dts/zynqmp-zcu106-revA.dts
+55 -19
View File
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU106
*
* (C) Copyright 2016 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -45,6 +45,21 @@
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x8000000>;
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
linux,cma-default;
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
@@ -68,74 +83,92 @@
ina226-u76 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
};
ina226-u77 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
};
ina226-u78 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
};
ina226-u87 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
};
ina226-u85 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
};
ina226-u86 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
};
ina226-u93 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
};
ina226-u88 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
};
ina226-u15 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
};
ina226-u92 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
};
ina226-u79 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
};
ina226-u81 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
};
ina226-u80 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
};
ina226-u84 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
};
ina226-u16 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
};
ina226-u65 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
};
ina226-u74 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
};
ina226-u75 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
};
@@ -217,7 +250,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
#phy-cells = <1>;
reg = <0xc>;
compatible = "ethernet-phy-id2000.a231";
ti,rx-internal-delay = <0x8>;
@@ -981,28 +1013,32 @@
num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
};
};
};
};
arch/arm/dts/zynqmp-zcu111-revA.dts
+51 -19
View File
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU111
*
* (C) Copyright 2017 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -45,6 +45,21 @@
/* Another 4GB connected to PL */
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x8000000>;
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
linux,cma-default;
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
@@ -68,58 +83,72 @@
ina226-u67 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;
};
ina226-u59 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;
};
ina226-u61 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
};
ina226-u60 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
};
ina226-u64 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
};
ina226-u69 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;
};
ina226-u66 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;
};
ina226-u65 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
};
ina226-u63 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
};
ina226-u3 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;
};
ina226-u71 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;
};
ina226-u77 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
};
ina226-u73 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;
};
ina226-u79 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
};
@@ -189,7 +218,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
@@ -804,28 +832,32 @@
num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
};
};
};
};
arch/arm/dts/zynqmp-zcu1275-revA.dts
+36 -17
View File
@@ -32,6 +32,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x8000000>;
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
linux,cma-default;
};
};
};
&dcc {
@@ -46,27 +61,31 @@
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
};
};
};
};
arch/arm/dts/zynqmp-zcu1275-revB.dts
+36 -17
View File
@@ -35,6 +35,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x8000000>;
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
linux,cma-default;
};
};
};
&dcc {
@@ -73,27 +88,31 @@
status = "okay";
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
};
};
};
};
arch/arm/dts/zynqmp-zcu1285-revA.dts
+15
View File
@@ -36,6 +36,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x8000000>;
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
linux,cma-default;
};
};
};
&dcc {
arch/arm/dts/zynqmp-zcu208-revA.dts
+29 -1
View File
@@ -43,6 +43,21 @@
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x8000000>;
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
linux,cma-default;
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
@@ -66,61 +81,75 @@
ina226-vccint {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
};
ina226-vccint-io-bram {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>,
<&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
};
ina226-vcc1v8 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
};
ina226-vcc1v2 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
};
ina226-vadj-fmc {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
};
ina226-mgtavcc {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
};
ina226-mgt1v2 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
};
ina226-mgt1v8 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
};
ina226-vccint-ams {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
};
ina226-dac-avtt {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
};
ina226-dac-avccaux {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>,
<&dac_avccaux 3>;
};
ina226-adc-avcc {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
};
ina226-adc-avccaux {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>,
<&adc_avccaux 3>;
};
ina226-dac-avcc {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
};
@@ -176,7 +205,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
arch/arm/dts/zynqmp-zcu216-revA.dts
+29 -1
View File
@@ -43,6 +43,21 @@
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x8000000>;
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
linux,cma-default;
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
@@ -66,61 +81,75 @@
ina226-vccint {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
};
ina226-vccint-io-bram {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>,
<&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
};
ina226-vcc1v8 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
};
ina226-vcc1v2 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
};
ina226-vadj-fmc {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
};
ina226-mgtavcc {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
};
ina226-mgt1v2 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
};
ina226-mgt1v8 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
};
ina226-vccint-ams {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
};
ina226-dac-avtt {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
};
ina226-dac-avccaux {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>,
<&dac_avccaux 3>;
};
ina226-adc-avcc {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
};
ina226-adc-avccaux {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>,
<&adc_avccaux 3>;
};
ina226-dac-avcc {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
};
@@ -183,7 +212,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
arch/arm/dts/zynqmp-zcu670-revA.dts
+30 -2
View File
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU670 (67DR)
*
* (C) Copyright 2017 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -46,6 +46,21 @@
/* Another 4GB connected to PL */
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x8000000>;
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
linux,cma-default;
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
@@ -69,61 +84,75 @@
ina226-vccint {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
};
ina226-vccint-io-bram {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>,
<&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
};
ina226-vcc1v8 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
};
ina226-vcc1v2 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
};
ina226-vadj-fmc {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
};
ina226-mgtavcc {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
};
ina226-mgt1v2 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
};
ina226-mgt1v8 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
};
ina226-vccint-ams {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
};
ina226-dac-avtt {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
};
ina226-dac-avccaux {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>,
<&dac_avccaux 3>;
};
ina226-adc-avcc {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
};
ina226-adc-avccaux {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>,
<&adc_avccaux 3>;
};
ina226-dac-avcc {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
};
@@ -185,7 +214,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
arch/arm/dts/zynqmp-zcu670-revB.dts
+30 -2
View File
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU670 (67DR) revB
*
* (C) Copyright 2017 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -46,6 +46,21 @@
/* Another 4GB connected to PL */
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x8000000>;
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
linux,cma-default;
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
@@ -69,61 +84,75 @@
ina226-vccint {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
};
ina226-vccint-io-bram {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>,
<&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
};
ina226-vcc1v8 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
};
ina226-vcc1v2 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
};
ina226-vadj-fmc {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
};
ina226-mgtavcc {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
};
ina226-mgt1v2 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
};
ina226-mgt1v8 {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
};
ina226-vccint-ams {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
};
ina226-dac-avtt {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
};
ina226-dac-avccaux {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>,
<&dac_avccaux 3>;
};
ina226-adc-avcc {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
};
ina226-adc-avccaux {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>,
<&adc_avccaux 3>;
};
ina226-dac-avcc {
compatible = "iio-hwmon";
status = "disabled";
io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
};
@@ -185,7 +214,6 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
arch/arm/dts/zynqmp.dtsi
-1
View File
@@ -1006,7 +1006,6 @@
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "alarm", "sec";
calibration = <0x7FFF>;
};
sata: ahci@fd0c0000 {
arch/arm/mach-versal-net/cpu.c
+149
View File
@@ -7,6 +7,10 @@
*/
#include <init.h>
#include <log.h>
#include <malloc.h>
#include <time.h>
#include <vsprintf.h>
#include <asm/armv8/mmu.h>
#include <asm/cache.h>
#include <asm/global_data.h>
@@ -15,6 +19,9 @@
#include <asm/arch/sys_proto.h>
#include <asm/cache.h>
#include <dm/platdata.h>
#include <linux/bitfield.h>
#include <linux/string.h>
#include "../../../board/xilinx/common/board.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -88,6 +95,148 @@ u64 get_page_table_size(void)
return 0x14000;
}
void versal_net_timer_setup(void)
{
u32 val;
debug("iou_switch ctrl div0 %x\n",
readl(&crlapb_base->iou_switch_ctrl));
writel(IOU_SWITCH_CTRL_CLKACT_BIT |
(CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
&crlapb_base->iou_switch_ctrl);
/* Global timer init - Program time stamp reference clk */
val = readl(&crlapb_base->timestamp_ref_ctrl);
val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
writel(val, &crlapb_base->timestamp_ref_ctrl);
debug("ref ctrl 0x%x\n",
readl(&crlapb_base->timestamp_ref_ctrl));
/* Clear reset of timestamp reg */
writel(0, &crlapb_base->rst_timestamp);
/*
* Program freq register in System counter and
* enable system counter.
*/
writel(CONFIG_COUNTER_FREQUENCY,
&iou_scntr_secure->base_frequency_id_register);
debug("counter val 0x%x\n",
readl(&iou_scntr_secure->base_frequency_id_register));
writel(IOU_SCNTRS_CONTROL_EN,
&iou_scntr_secure->counter_control_register);
debug("scntrs control 0x%x\n",
readl(&iou_scntr_secure->counter_control_register));
debug("timer 0x%llx\n", get_ticks());
debug("timer 0x%llx\n", get_ticks());
}
u32 versal_net_bootmode_reg(void)
{
return readl(&crp_base->boot_mode_usr);
}
u8 __weak versal_net_get_bootmode(void)
{
u32 reg = versal_net_bootmode_reg();
if (reg >> BOOT_MODE_ALT_SHIFT)
reg >>= BOOT_MODE_ALT_SHIFT;
return reg & BOOT_MODES_MASK;
}
static u32 platform_id, platform_version;
char *soc_name_decode(void)
{
char *name, *platform_name;
switch (platform_id) {
case VERSAL_NET_SPP:
platform_name = "ipp";
break;
case VERSAL_NET_EMU:
platform_name = "emu";
break;
case VERSAL_NET_QEMU:
platform_name = "qemu";
break;
default:
return NULL;
}
/*
* --rev. are 6 chars
* max platform name is qemu which is 4 chars
* platform version number are 1+1
* Plus 1 char for \n
*/
name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13);
if (!name)
return NULL;
sprintf(name, "%s-%s-rev%d.%d", CONFIG_SYS_BOARD,
platform_name, platform_version / 10,
platform_version % 10);
return name;
}
bool soc_detection(void)
{
u32 version, ps_version;
version = readl(PMC_TAP_VERSION);
platform_id = FIELD_GET(PLATFORM_MASK, version);
ps_version = FIELD_GET(PS_VERSION_MASK, version);
debug("idcode %x, version %x, usercode %x\n",
readl(PMC_TAP_IDCODE), version,
readl(PMC_TAP_USERCODE));
debug("pmc_ver %lx, ps version %x, rtl version %lx\n",
FIELD_GET(PMC_VERSION_MASK, version),
ps_version,
FIELD_GET(RTL_VERSION_MASK, version));
platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version);
if (platform_id == VERSAL_NET_SPP ||
platform_id == VERSAL_NET_EMU) {
if (ps_version == PS_VERSION_PRODUCTION) {
/*
* ES1 version ends at 1.9 version where there was +9
* used because of IPP/SPP conversion. Production
* version have platform_version started from 0 again
* that's why adding +20 to continue with the same line.
* It means the last ES1 version ends at 1.9 version and
* new PRODUCTION line starts at 2.0.
*/
platform_version += 20;
} else {
/*
* 9 is diff for
* 0 means 0.9 version
* 1 means 1.0 version
* 2 means 1.1 version
* etc,
*/
platform_version += 9;
}
}
debug("Platform id: %d version: %d.%d\n", platform_id,
platform_version / 10, platform_version % 10);
return true;
}
U_BOOT_DRVINFO(soc_xilinx_versal_net) = {
.name = "soc_xilinx_versal_net",
};
arch/arm/mach-versal-net/include/mach/sys_proto.h
+6
View File
@@ -7,3 +7,9 @@
#include <linux/build_bug.h>
void mem_map_fill(void);
/* EL3 clock/timer register setup, called from board_early_init_r() */
void versal_net_timer_setup(void);
/* Overridable bootmode decode: weak MMIO default, firmware override */
u8 versal_net_get_bootmode(void);
/* Direct MMIO read of the bootmode register (EL3 / no-firmware path) */
u32 versal_net_bootmode_reg(void);
arch/arm/mach-versal/cpu.c
+72 -15
View File
@@ -1,10 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 - 2018 Xilinx, Inc.
* (C) Copyright 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
#include <init.h>
#include <log.h>
#include <time.h>
#include <asm/armv8/mmu.h>
#include <asm/cache.h>
#include <asm/global_data.h>
@@ -16,7 +20,7 @@
DECLARE_GLOBAL_DATA_PTR;
#define VERSAL_MEM_MAP_USED 5
#define VERSAL_MEM_MAP_USED 3
#define DRAM_BANKS CONFIG_NR_DRAM_BANKS
@@ -44,26 +48,13 @@ static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
}, { /* FPD_AXI_PL_high */
.virt = 0x400000000UL,
.phys = 0x400000000UL,
.size = 0x200000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x600000000UL,
.phys = 0x600000000UL,
.size = 0x800000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xe00000000UL,
.phys = 0xe00000000UL,
.size = 0xf200000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}
};
@@ -121,6 +112,72 @@ int arm_reserve_mmu(void)
}
#endif
u32 versal_multi_boot_reg(void)
{
return readl(PMC_MULTI_BOOT_REG) & PMC_MULTI_BOOT_MASK;
}
u32 __weak versal_pmc_multi_boot(void)
{
return versal_multi_boot_reg();
}
void versal_timer_setup(void)
{
u32 val;
debug("iou_switch ctrl div0 %x\n",
readl(&crlapb_base->iou_switch_ctrl));
writel(IOU_SWITCH_CTRL_CLKACT_BIT |
(CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
&crlapb_base->iou_switch_ctrl);
/* Global timer init - Program time stamp reference clk */
val = readl(&crlapb_base->timestamp_ref_ctrl);
val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
writel(val, &crlapb_base->timestamp_ref_ctrl);
debug("ref ctrl 0x%x\n",
readl(&crlapb_base->timestamp_ref_ctrl));
/* Clear reset of timestamp reg */
writel(0, &crlapb_base->rst_timestamp);
/*
* Program freq register in System counter and
* enable system counter.
*/
writel(CONFIG_COUNTER_FREQUENCY,
&iou_scntr_secure->base_frequency_id_register);
debug("counter val 0x%x\n",
readl(&iou_scntr_secure->base_frequency_id_register));
writel(IOU_SCNTRS_CONTROL_EN,
&iou_scntr_secure->counter_control_register);
debug("scntrs control 0x%x\n",
readl(&iou_scntr_secure->counter_control_register));
debug("timer 0x%llx\n", get_ticks());
debug("timer 0x%llx\n", get_ticks());
}
u32 versal_bootmode_reg(void)
{
return readl(&crp_base->boot_mode_usr);
}
u8 __weak versal_get_bootmode(void)
{
u32 reg = versal_bootmode_reg();
if (reg >> BOOT_MODE_ALT_SHIFT)
reg >>= BOOT_MODE_ALT_SHIFT;
return reg & BOOT_MODES_MASK;
}
U_BOOT_DRVINFO(soc_xilinx_versal) = {
.name = "soc_xilinx_versal",
};
arch/arm/mach-versal/include/mach/sys_proto.h
+16
View File
@@ -3,6 +3,9 @@
* Copyright 2016 - 2018 Xilinx, Inc.
*/
#ifndef _ASM_ARCH_SYS_PROTO_H
#define _ASM_ARCH_SYS_PROTO_H
#include <linux/build_bug.h>
enum tcm_mode {
@@ -13,3 +16,16 @@ enum tcm_mode {
void initialize_tcm(enum tcm_mode mode);
void tcm_init(enum tcm_mode mode);
void mem_map_fill(void);
/* Overridable PMC multiboot accessor: weak MMIO default, firmware override */
u32 versal_pmc_multi_boot(void);
/* Direct MMIO read of the multiboot register (EL3 / no-firmware path) */
u32 versal_multi_boot_reg(void);
/* Overridable bootmode decode: weak MMIO default, firmware override */
u8 versal_get_bootmode(void);
/* Direct MMIO read of the bootmode register (EL3 / no-firmware path) */
u32 versal_bootmode_reg(void);
/* EL3 clock/timer register setup, called from board_early_init_r() */
void versal_timer_setup(void);
#endif /* _ASM_ARCH_SYS_PROTO_H */
arch/arm/mach-versal2/cpu.c
+145 -15
View File
@@ -7,21 +7,29 @@
*/
#include <init.h>
#include <log.h>
#include <malloc.h>
#include <time.h>
#include <vsprintf.h>
#include <asm/armv8/mmu.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/cache.h>
#include <dm/platdata.h>
#include <linux/bitfield.h>
#include <linux/string.h>
#include "../../../board/xilinx/common/board.h"
DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_IS_ENABLED(PCIE_DW_AMD)
#define VERSAL2_MEM_MAP_USED 6
#define VERSAL2_MEM_MAP_USED 4
#else
#define VERSAL2_MEM_MAP_USED 5
#define VERSAL2_MEM_MAP_USED 3
#endif
#define DRAM_BANKS CONFIG_NR_DRAM_BANKS
@@ -51,19 +59,6 @@ static struct mm_region versal2_mem_map[VERSAL2_MEM_MAP_MAX] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x600000000UL,
.phys = 0x600000000UL,
.size = 0x800000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xe00000000UL,
.phys = 0xe00000000UL,
.size = 0xf200000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
#if CONFIG_IS_ENABLED(PCIE_DW_AMD)
}, {
/* PCIe DBI (1 MB) and config space (255 MB) are contiguous */
@@ -140,6 +135,141 @@ u64 get_page_table_size(void)
}
#endif
u32 versal2_multi_boot_reg(void)
{
return readl(PMC_MULTI_BOOT_REG) & PMC_MULTI_BOOT_MASK;
}
u32 __weak versal2_pmc_multi_boot(void)
{
return versal2_multi_boot_reg();
}
u8 __weak versal2_get_bootmode(void)
{
u8 bootmode;
u32 reg;
reg = readl(&crp_base->boot_mode_usr);
if (reg >> BOOT_MODE_ALT_SHIFT)
reg >>= BOOT_MODE_ALT_SHIFT;
bootmode = reg & BOOT_MODES_MASK;
return bootmode;
}
void versal2_timer_setup(void)
{
u32 val;
debug("iou_switch ctrl div0 %x\n",
readl(&crlapb_base->iou_switch_ctrl));
writel(IOU_SWITCH_CTRL_CLKACT_BIT |
(CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
&crlapb_base->iou_switch_ctrl);
/* Global timer init - Program time stamp reference clk */
val = readl(&crlapb_base->timestamp_ref_ctrl);
val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
writel(val, &crlapb_base->timestamp_ref_ctrl);
debug("ref ctrl 0x%x\n",
readl(&crlapb_base->timestamp_ref_ctrl));
/* Clear reset of timestamp reg */
writel(0, &crlapb_base->rst_timestamp);
/*
* Program freq register in System counter and
* enable system counter.
*/
writel(CONFIG_COUNTER_FREQUENCY,
&iou_scntr_secure->base_frequency_id_register);
debug("counter val 0x%x\n",
readl(&iou_scntr_secure->base_frequency_id_register));
writel(IOU_SCNTRS_CONTROL_EN,
&iou_scntr_secure->counter_control_register);
debug("scntrs control 0x%x\n",
readl(&iou_scntr_secure->counter_control_register));
debug("timer 0x%llx\n", get_ticks());
debug("timer 0x%llx\n", get_ticks());
}
static u32 platform_id, platform_version;
char *soc_name_decode(void)
{
char *name, *platform_name;
switch (platform_id) {
case VERSAL2_SPP:
platform_name = "spp";
break;
case VERSAL2_EMU:
platform_name = "emu";
break;
case VERSAL2_SPP_MMD:
platform_name = "spp-mmd";
break;
case VERSAL2_EMU_MMD:
platform_name = "emu-mmd";
break;
case VERSAL2_QEMU:
platform_name = "qemu";
break;
default:
return NULL;
}
/*
* --rev.-el are 9 chars
* max platform name is emu-mmd which is 7 chars
* platform version number are 1+1
* el is 1 char
* Plus 1 char for NULL byte
*/
name = calloc(1, strlen(CONFIG_SYS_BOARD) + 20);
if (!name)
return NULL;
sprintf(name, "%s-%s-rev%d.%d-el%d", CONFIG_SYS_BOARD,
platform_name, platform_version / 10,
platform_version % 10, current_el());
return name;
}
bool soc_detection(void)
{
u32 version, ps_version;
version = readl(PMC_TAP_VERSION);
platform_id = FIELD_GET(PLATFORM_MASK, version);
ps_version = FIELD_GET(PS_VERSION_MASK, version);
debug("idcode %x, version %x, usercode %x\n",
readl(PMC_TAP_IDCODE), version,
readl(PMC_TAP_USERCODE));
debug("pmc_ver %lx, ps version %x, rtl version %lx\n",
FIELD_GET(PMC_VERSION_MASK, version),
ps_version,
FIELD_GET(RTL_VERSION_MASK, version));
platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version);
debug("Platform id: %d version: %d.%d\n", platform_id,
platform_version / 10, platform_version % 10);
return true;
}
U_BOOT_DRVINFO(soc_amd_versal2) = {
.name = "soc_amd_versal2",
};
arch/arm/mach-versal2/include/mach/sys_proto.h
+14
View File
@@ -4,8 +4,22 @@
* Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
*/
#ifndef _ASM_ARCH_SYS_PROTO_H
#define _ASM_ARCH_SYS_PROTO_H
#include <linux/build_bug.h>
#include <asm/armv8/mmu.h>
void mem_map_fill(struct mm_region *bank_info, u32 num_banks);
void fill_bd_mem_info(void);
/* Overridable PMC multiboot accessor: weak MMIO default, firmware override */
u32 versal2_pmc_multi_boot(void);
/* Direct MMIO read of the multiboot register (EL3 / no-firmware path) */
u32 versal2_multi_boot_reg(void);
/* Weak bootmode decode (MMIO default); a firmware/SCMI build may override */
u8 versal2_get_bootmode(void);
/* EL3 clock/timer register setup, called from board_early_init_r() */
void versal2_timer_setup(void);
#endif /* _ASM_ARCH_SYS_PROTO_H */
arch/arm/mach-zynqmp/cpu.c
+36 -35
View File
@@ -8,6 +8,7 @@
#include <time.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/armv8/mmu.h>
@@ -171,15 +172,19 @@ unsigned int zynqmp_get_silicon_version(void)
return ZYNQMP_CSU_VERSION_SILICON;
}
static int zynqmp_mmio_rawwrite(const u32 address,
const u32 mask,
const u32 value)
int zynqmp_mmio_rawread(const u32 address, u32 *value)
{
*value = readl((ulong)address);
return 0;
}
int zynqmp_mmio_rawwrite(const u32 address, const u32 mask, const u32 value)
{
u32 data;
u32 value_local = value;
int ret;
ret = zynqmp_mmio_read(address, &data);
ret = zynqmp_mmio_rawread(address, &data);
if (ret)
return ret;
@@ -190,48 +195,44 @@ static int zynqmp_mmio_rawwrite(const u32 address,
return 0;
}
static int zynqmp_mmio_rawread(const u32 address, u32 *value)
{
*value = readl((ulong)address);
return 0;
}
int zynqmp_mmio_write(const u32 address,
const u32 mask,
const u32 value)
int __weak zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value)
{
if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3)
return zynqmp_mmio_rawwrite(address, mask, value);
#if defined(CONFIG_ZYNQMP_FIRMWARE)
else
return xilinx_pm_request(PM_MMIO_WRITE, address, mask,
value, 0, 0, 0, NULL);
#endif
return -EINVAL;
}
int zynqmp_mmio_read(const u32 address, u32 *value)
int __weak zynqmp_mmio_read(const u32 address, u32 *value)
{
u32 ret = -EINVAL;
if (!value)
return ret;
return -EINVAL;
if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) {
ret = zynqmp_mmio_rawread(address, value);
if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3)
return zynqmp_mmio_rawread(address, value);
return -EINVAL;
}
void zynqmp_timer_setup(void)
{
u32 val;
val = readl(&crlapb_base->timestamp_ref_ctrl);
val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
if (!val) {
val = readl(&crlapb_base->timestamp_ref_ctrl);
val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
writel(val, &crlapb_base->timestamp_ref_ctrl);
/* Program freq register in System counter */
writel(zynqmp_get_system_timer_freq(),
&iou_scntr_secure->base_frequency_id_register);
/* And enable system counter */
writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
&iou_scntr_secure->counter_control_register);
}
#if defined(CONFIG_ZYNQMP_FIRMWARE)
else {
u32 ret_payload[PAYLOAD_ARG_CNT];
ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0,
0, 0, 0, ret_payload);
*value = ret_payload[1];
}
#endif
return ret;
}
U_BOOT_DRVINFO(soc_xilinx_zynqmp) = {
arch/arm/mach-zynqmp/include/mach/sys_proto.h
+5
View File
@@ -54,5 +54,10 @@ void mem_map_fill(void);
#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
void tcm_init(enum tcm_mode mode);
#endif
/* EL3 clock/timer register setup, called from board_early_init_r() */
void zynqmp_timer_setup(void);
/* Direct MMIO accessors (EL3/SPL or no-firmware path) */
int zynqmp_mmio_rawread(const u32 address, u32 *value);
int zynqmp_mmio_rawwrite(const u32 address, const u32 mask, const u32 value);
#endif /* _ASM_ARCH_SYS_PROTO_H */
board/amd/versal2/board.c
+30 -131
View File
@@ -29,11 +29,8 @@
#include <dm/device.h>
#include <dm/uclass.h>
#include <versalpl.h>
#include <zynqmp_firmware.h>
#include "../../xilinx/common/board.h"
#include <linux/bitfield.h>
#include <linux/sizes.h>
#include <debug_uart.h>
#include <generated/dt.h>
#include <linux/ioport.h>
@@ -62,151 +59,25 @@ int board_init(void)
return 0;
}
static u32 platform_id, platform_version;
char *soc_name_decode(void)
{
char *name, *platform_name;
switch (platform_id) {
case VERSAL2_SPP:
platform_name = "spp";
break;
case VERSAL2_EMU:
platform_name = "emu";
break;
case VERSAL2_SPP_MMD:
platform_name = "spp-mmd";
break;
case VERSAL2_EMU_MMD:
platform_name = "emu-mmd";
break;
case VERSAL2_QEMU:
platform_name = "qemu";
break;
default:
return NULL;
}
/*
* --rev.-el are 9 chars
* max platform name is emu-mmd which is 7 chars
* platform version number are 1+1
* el is 1 char
* Plus 1 char for NULL byte
*/
name = calloc(1, strlen(CONFIG_SYS_BOARD) + 20);
if (!name)
return NULL;
sprintf(name, "%s-%s-rev%d.%d-el%d", CONFIG_SYS_BOARD,
platform_name, platform_version / 10,
platform_version % 10, current_el());
return name;
}
bool soc_detection(void)
{
u32 version, ps_version;
version = readl(PMC_TAP_VERSION);
platform_id = FIELD_GET(PLATFORM_MASK, version);
ps_version = FIELD_GET(PS_VERSION_MASK, version);
debug("idcode %x, version %x, usercode %x\n",
readl(PMC_TAP_IDCODE), version,
readl(PMC_TAP_USERCODE));
debug("pmc_ver %lx, ps version %x, rtl version %lx\n",
FIELD_GET(PMC_VERSION_MASK, version),
ps_version,
FIELD_GET(RTL_VERSION_MASK, version));
platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version);
debug("Platform id: %d version: %d.%d\n", platform_id,
platform_version / 10, platform_version % 10);
return true;
}
int board_early_init_r(void)
{
u32 val;
if (current_el() != 3)
return 0;
debug("iou_switch ctrl div0 %x\n",
readl(&crlapb_base->iou_switch_ctrl));
writel(IOU_SWITCH_CTRL_CLKACT_BIT |
(CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
&crlapb_base->iou_switch_ctrl);
/* Global timer init - Program time stamp reference clk */
val = readl(&crlapb_base->timestamp_ref_ctrl);
val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
writel(val, &crlapb_base->timestamp_ref_ctrl);
debug("ref ctrl 0x%x\n",
readl(&crlapb_base->timestamp_ref_ctrl));
/* Clear reset of timestamp reg */
writel(0, &crlapb_base->rst_timestamp);
/*
* Program freq register in System counter and
* enable system counter.
*/
writel(CONFIG_COUNTER_FREQUENCY,
&iou_scntr_secure->base_frequency_id_register);
debug("counter val 0x%x\n",
readl(&iou_scntr_secure->base_frequency_id_register));
writel(IOU_SCNTRS_CONTROL_EN,
&iou_scntr_secure->counter_control_register);
debug("scntrs control 0x%x\n",
readl(&iou_scntr_secure->counter_control_register));
debug("timer 0x%llx\n", get_ticks());
debug("timer 0x%llx\n", get_ticks());
versal2_timer_setup();
return 0;
}
static u8 versal2_get_bootmode(void)
{
u8 bootmode;
u32 reg = 0;
reg = readl(&crp_base->boot_mode_usr);
if (reg >> BOOT_MODE_ALT_SHIFT)
reg >>= BOOT_MODE_ALT_SHIFT;
bootmode = reg & BOOT_MODES_MASK;
return bootmode;
}
static u32 versal2_multi_boot(void)
{
u8 bootmode = versal2_get_bootmode();
u32 reg = 0;
/* Mostly workaround for QEMU CI pipeline */
if (bootmode == JTAG_MODE)
return 0;
if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3)
reg = zynqmp_pm_get_pmc_multi_boot_reg();
else
reg = readl(PMC_MULTI_BOOT_REG);
return reg & PMC_MULTI_BOOT_MASK;
return versal2_pmc_multi_boot();
}
static int boot_targets_setup(void)
@@ -605,3 +476,31 @@ void set_dfu_alt_info(char *interface, char *devstr)
env_set("dfu_alt_info", buf);
}
#endif
int spi_get_env_dev(void)
{
struct udevice *dev;
const char *name;
int bootseq;
switch (versal2_get_bootmode()) {
case QSPI_MODE_24BIT:
case QSPI_MODE_32BIT:
name = "spi@f1030000";
break;
case OSPI_MODE:
name = "spi@f1010000";
break;
default:
return -1;
}
if (uclass_get_device_by_name(UCLASS_SPI, name, &dev)) {
debug("SPI driver for %s is not present\n", name);
return -1;
}
bootseq = dev_seq(dev);
debug("bootseq %d\n", bootseq);
return bootseq;
}
board/xilinx/versal-net/board.c
+77 -220
View File
@@ -12,6 +12,7 @@
#include <env_internal.h>
#include <log.h>
#include <malloc.h>
#include <mmc.h>
#include <spi.h>
#include <time.h>
#include <asm/cache.h>
@@ -21,11 +22,9 @@
#include <asm/arch/sys_proto.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <zynqmp_firmware.h>
#include <versalpl.h>
#include "../common/board.h"
#include <linux/bitfield.h>
#include <debug_uart.h>
#include <generated/dt.h>
@@ -49,92 +48,6 @@ int board_init(void)
return 0;
}
static u32 platform_id, platform_version;
char *soc_name_decode(void)
{
char *name, *platform_name;
switch (platform_id) {
case VERSAL_NET_SPP:
platform_name = "ipp";
break;
case VERSAL_NET_EMU:
platform_name = "emu";
break;
case VERSAL_NET_QEMU:
platform_name = "qemu";
break;
default:
return NULL;
}
/*
* --rev. are 6 chars
* max platform name is qemu which is 4 chars
* platform version number are 1+1
* Plus 1 char for \n
*/
name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13);
if (!name)
return NULL;
sprintf(name, "%s-%s-rev%d.%d", CONFIG_SYS_BOARD,
platform_name, platform_version / 10,
platform_version % 10);
return name;
}
bool soc_detection(void)
{
u32 version, ps_version;
version = readl(PMC_TAP_VERSION);
platform_id = FIELD_GET(PLATFORM_MASK, version);
ps_version = FIELD_GET(PS_VERSION_MASK, version);
debug("idcode %x, version %x, usercode %x\n",
readl(PMC_TAP_IDCODE), version,
readl(PMC_TAP_USERCODE));
debug("pmc_ver %lx, ps version %x, rtl version %lx\n",
FIELD_GET(PMC_VERSION_MASK, version),
ps_version,
FIELD_GET(RTL_VERSION_MASK, version));
platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version);
if (platform_id == VERSAL_NET_SPP ||
platform_id == VERSAL_NET_EMU) {
if (ps_version == PS_VERSION_PRODUCTION) {
/*
* ES1 version ends at 1.9 version where there was +9
* used because of IPP/SPP conversion. Production
* version have platform_version started from 0 again
* that's why adding +20 to continue with the same line.
* It means the last ES1 version ends at 1.9 version and
* new PRODUCTION line starts at 2.0.
*/
platform_version += 20;
} else {
/*
* 9 is diff for
* 0 means 0.9 version
* 1 means 1.0 version
* 2 means 1.1 version
* etc,
*/
platform_version += 9;
}
}
debug("Platform id: %d version: %d.%d\n", platform_id,
platform_version / 10, platform_version % 10);
return true;
}
int board_early_init_f(void)
{
if (IS_ENABLED(CONFIG_DEBUG_UART)) {
@@ -148,118 +61,103 @@ int board_early_init_f(void)
int board_early_init_r(void)
{
u32 val;
if (current_el() != 3)
return 0;
debug("iou_switch ctrl div0 %x\n",
readl(&crlapb_base->iou_switch_ctrl));
writel(IOU_SWITCH_CTRL_CLKACT_BIT |
(CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
&crlapb_base->iou_switch_ctrl);
/* Global timer init - Program time stamp reference clk */
val = readl(&crlapb_base->timestamp_ref_ctrl);
val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
writel(val, &crlapb_base->timestamp_ref_ctrl);
debug("ref ctrl 0x%x\n",
readl(&crlapb_base->timestamp_ref_ctrl));
/* Clear reset of timestamp reg */
writel(0, &crlapb_base->rst_timestamp);
/*
* Program freq register in System counter and
* enable system counter.
*/
writel(CONFIG_COUNTER_FREQUENCY,
&iou_scntr_secure->base_frequency_id_register);
debug("counter val 0x%x\n",
readl(&iou_scntr_secure->base_frequency_id_register));
writel(IOU_SCNTRS_CONTROL_EN,
&iou_scntr_secure->counter_control_register);
debug("scntrs control 0x%x\n",
readl(&iou_scntr_secure->counter_control_register));
debug("timer 0x%llx\n", get_ticks());
debug("timer 0x%llx\n", get_ticks());
versal_net_timer_setup();
return 0;
}
static u8 versal_net_get_bootmode(void)
static int spi_get_bootseq(u8 bootmode, const char **modename)
{
u8 bootmode;
u32 reg = 0;
struct udevice *dev;
const char *name;
int bootseq;
if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) {
reg = zynqmp_pm_get_bootmode_reg();
} else {
reg = readl(&crp_base->boot_mode_usr);
switch (bootmode) {
case QSPI_MODE_24BIT:
if (modename)
*modename = "QSPI_MODE_24\n";
name = "spi@f1030000";
break;
case QSPI_MODE_32BIT:
if (modename)
*modename = "QSPI_MODE_32\n";
name = "spi@f1030000";
break;
case OSPI_MODE:
if (modename)
*modename = "OSPI_MODE\n";
name = "spi@f1010000";
break;
default:
return -1;
}
if (reg >> BOOT_MODE_ALT_SHIFT)
reg >>= BOOT_MODE_ALT_SHIFT;
if (uclass_get_device_by_name(UCLASS_SPI, name, &dev)) {
debug("SPI driver for %s is not present\n", name);
return -1;
}
bootmode = reg & BOOT_MODES_MASK;
bootseq = dev_seq(dev);
debug("bootseq %d\n", bootseq);
return bootmode;
return bootseq;
}
int spi_get_env_dev(void)
{
struct udevice *dev;
int bootseq = -1;
return spi_get_bootseq(versal_net_get_bootmode(), NULL);
}
switch (versal_net_get_bootmode()) {
case QSPI_MODE_24BIT:
puts("QSPI_MODE_24\n");
if (uclass_get_device_by_name(UCLASS_SPI,
"spi@f1030000", &dev)) {
debug("QSPI driver for QSPI device is not present\n");
break;
}
bootseq = dev_seq(dev);
static int mmc_get_bootseq(u8 bootmode, const char **modename)
{
struct udevice *dev;
const char *name;
switch (bootmode) {
case SD_MODE:
if (modename)
*modename = "SD_MODE\n";
name = "mmc@f1040000";
break;
case QSPI_MODE_32BIT:
puts("QSPI_MODE_32\n");
if (uclass_get_device_by_name(UCLASS_SPI,
"spi@f1030000", &dev)) {
debug("QSPI driver for QSPI device is not present\n");
break;
}
bootseq = dev_seq(dev);
case EMMC_MODE:
if (modename)
*modename = "EMMC_MODE\n";
name = "mmc@f1050000";
break;
case OSPI_MODE:
puts("OSPI_MODE\n");
if (uclass_get_device_by_name(UCLASS_SPI,
"spi@f1010000", &dev)) {
debug("OSPI driver for OSPI device is not present\n");
break;
}
bootseq = dev_seq(dev);
case SD_MODE1:
case SD1_LSHFT_MODE:
if (modename)
*modename = "SD_MODE1\n";
name = "mmc@f1050000";
break;
default:
break;
return -1;
}
debug("bootseq %d\n", bootseq);
return bootseq;
if (uclass_get_device_by_name(UCLASS_MMC, name, &dev)) {
debug("MMC driver for %s is not present\n", name);
return -1;
}
return dev_seq(dev);
}
int mmc_get_env_dev(void)
{
return mmc_get_bootseq(versal_net_get_bootmode(), NULL);
}
static int boot_targets_setup(void)
{
u8 bootmode;
struct udevice *dev;
int bootseq = -1;
int bootseq_len = 0;
int env_targets_len = 0;
const char *mode = NULL;
const char *modename = NULL;
char *new_targets;
char *env_targets;
@@ -276,69 +174,28 @@ static int boot_targets_setup(void)
mode = "jtag pxe dhcp";
break;
case QSPI_MODE_24BIT:
puts("QSPI_MODE_24\n");
if (uclass_get_device_by_name(UCLASS_SPI,
"spi@f1030000", &dev)) {
debug("QSPI driver for QSPI device is not present\n");
break;
}
mode = "xspi";
bootseq = dev_seq(dev);
break;
case QSPI_MODE_32BIT:
puts("QSPI_MODE_32\n");
if (uclass_get_device_by_name(UCLASS_SPI,
"spi@f1030000", &dev)) {
debug("QSPI driver for QSPI device is not present\n");
break;
}
mode = "xspi";
bootseq = dev_seq(dev);
break;
case OSPI_MODE:
puts("OSPI_MODE\n");
if (uclass_get_device_by_name(UCLASS_SPI,
"spi@f1010000", &dev)) {
debug("OSPI driver for OSPI device is not present\n");
break;
}
mode = "xspi";
bootseq = dev_seq(dev);
break;
case EMMC_MODE:
puts("EMMC_MODE\n");
mode = "mmc";
bootseq = dev_seq(dev);
bootseq = spi_get_bootseq(bootmode, &modename);
if (modename)
puts(modename);
if (bootseq >= 0)
mode = "xspi";
break;
case SELECTMAP_MODE:
puts("SELECTMAP_MODE\n");
break;
case SD_MODE:
puts("SD_MODE\n");
if (uclass_get_device_by_name(UCLASS_MMC,
"mmc@f1040000", &dev)) {
debug("SD0 driver for SD0 device is not present\n");
break;
}
debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
mode = "mmc";
bootseq = dev_seq(dev);
break;
case SD1_LSHFT_MODE:
puts("LVL_SHFT_");
fallthrough;
case SD_MODE:
case EMMC_MODE:
case SD_MODE1:
puts("SD_MODE1\n");
if (uclass_get_device_by_name(UCLASS_MMC,
"mmc@f1050000", &dev)) {
debug("SD1 driver for SD1 device is not present\n");
break;
}
debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
mode = "mmc";
bootseq = dev_seq(dev);
bootseq = mmc_get_bootseq(bootmode, &modename);
if (modename)
puts(modename);
if (bootseq >= 0)
mode = "mmc";
break;
default:
printf("Invalid Boot Mode:0x%x\n", bootmode);
board/xilinx/versal/board.c
+2 -64
View File
@@ -28,7 +28,6 @@
#include <dm/device.h>
#include <dm/uclass.h>
#include <versalpl.h>
#include <zynqmp_firmware.h>
#include "../common/board.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -40,40 +39,15 @@ static xilinx_desc versalpl = {
};
#endif
static u8 versal_get_bootmode(void)
{
u8 bootmode;
u32 reg = 0;
if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) {
reg = zynqmp_pm_get_bootmode_reg();
} else {
reg = readl(&crp_base->boot_mode_usr);
}
if (reg >> BOOT_MODE_ALT_SHIFT)
reg >>= BOOT_MODE_ALT_SHIFT;
bootmode = reg & BOOT_MODES_MASK;
return bootmode;
}
static u32 versal_multi_boot(void)
{
u8 bootmode = versal_get_bootmode();
u32 reg = 0;
/* Mostly workaround for QEMU CI pipeline */
if (bootmode == JTAG_MODE)
return 0;
if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3)
reg = zynqmp_pm_get_pmc_multi_boot_reg();
else
reg = readl(PMC_MULTI_BOOT_REG);
return reg & PMC_MULTI_BOOT_MASK;
return versal_pmc_multi_boot();
}
int board_init(void)
@@ -94,46 +68,10 @@ int board_init(void)
int board_early_init_r(void)
{
u32 val;
if (current_el() != 3)
return 0;
debug("iou_switch ctrl div0 %x\n",
readl(&crlapb_base->iou_switch_ctrl));
writel(IOU_SWITCH_CTRL_CLKACT_BIT |
(CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
&crlapb_base->iou_switch_ctrl);
/* Global timer init - Program time stamp reference clk */
val = readl(&crlapb_base->timestamp_ref_ctrl);
val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
writel(val, &crlapb_base->timestamp_ref_ctrl);
debug("ref ctrl 0x%x\n",
readl(&crlapb_base->timestamp_ref_ctrl));
/* Clear reset of timestamp reg */
writel(0, &crlapb_base->rst_timestamp);
/*
* Program freq register in System counter and
* enable system counter.
*/
writel(CONFIG_COUNTER_FREQUENCY,
&iou_scntr_secure->base_frequency_id_register);
debug("counter val 0x%x\n",
readl(&iou_scntr_secure->base_frequency_id_register));
writel(IOU_SCNTRS_CONTROL_EN,
&iou_scntr_secure->counter_control_register);
debug("scntrs control 0x%x\n",
readl(&iou_scntr_secure->counter_control_register));
debug("timer 0x%llx\n", get_ticks());
debug("timer 0x%llx\n", get_ticks());
versal_timer_setup();
return 0;
}
board/xilinx/zynqmp/zynqmp.c
+1 -17
View File
@@ -24,7 +24,6 @@
#include <malloc.h>
#include <memalign.h>
#include <wdt.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/psu_init_gpl.h>
@@ -214,26 +213,11 @@ int board_init(void)
int board_early_init_r(void)
{
u32 val;
if (current_el() != 3)
return 0;
val = readl(&crlapb_base->timestamp_ref_ctrl);
val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
zynqmp_timer_setup();
if (!val) {
val = readl(&crlapb_base->timestamp_ref_ctrl);
val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
writel(val, &crlapb_base->timestamp_ref_ctrl);
/* Program freq register in System counter */
writel(zynqmp_get_system_timer_freq(),
&iou_scntr_secure->base_frequency_id_register);
/* And enable system counter */
writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
&iou_scntr_secure->counter_control_register);
}
return 0;
}
drivers/firmware/firmware-zynqmp.c
+89
View File
@@ -7,6 +7,7 @@
*/
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <cpu_func.h>
#include <dm.h>
@@ -16,6 +17,7 @@
#include <zynqmp_firmware.h>
#include <asm/cache.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <linux/bitfield.h>
#if defined(CONFIG_ZYNQMP_IPI)
@@ -326,6 +328,93 @@ u32 zynqmp_pm_get_pmc_multi_boot_reg(void)
}
#endif
#if defined(CONFIG_ARCH_VERSAL)
u32 versal_pmc_multi_boot(void)
{
/* At EL3 the SMC path to firmware is unavailable, read directly */
if (current_el() == 3)
return versal_multi_boot_reg();
return zynqmp_pm_get_pmc_multi_boot_reg() & PMC_MULTI_BOOT_MASK;
}
u8 versal_get_bootmode(void)
{
u32 reg;
/* At EL3 the SMC path to firmware is unavailable, read directly */
if (current_el() == 3)
reg = versal_bootmode_reg();
else
reg = zynqmp_pm_get_bootmode_reg();
if (reg >> BOOT_MODE_ALT_SHIFT)
reg >>= BOOT_MODE_ALT_SHIFT;
return reg & BOOT_MODES_MASK;
}
#endif
#if defined(CONFIG_ARCH_VERSAL_NET)
u8 versal_net_get_bootmode(void)
{
u32 reg;
/* At EL3 the SMC path to firmware is unavailable, read directly */
if (current_el() == 3)
reg = versal_net_bootmode_reg();
else
reg = zynqmp_pm_get_bootmode_reg();
if (reg >> BOOT_MODE_ALT_SHIFT)
reg >>= BOOT_MODE_ALT_SHIFT;
return reg & BOOT_MODES_MASK;
}
#endif
#if defined(CONFIG_ARCH_ZYNQMP)
int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value)
{
/* At EL3 or in SPL the firmware (SMC) path is unavailable */
if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3)
return zynqmp_mmio_rawwrite(address, mask, value);
return xilinx_pm_request(PM_MMIO_WRITE, address, mask, value,
0, 0, 0, NULL);
}
int zynqmp_mmio_read(const u32 address, u32 *value)
{
u32 ret_payload[PAYLOAD_ARG_CNT];
int ret;
if (!value)
return -EINVAL;
/* At EL3 or in SPL the firmware (SMC) path is unavailable */
if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3)
return zynqmp_mmio_rawread(address, value);
ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0, 0, 0, 0,
ret_payload);
*value = ret_payload[1];
return ret;
}
#endif
#if defined(CONFIG_ARCH_VERSAL2)
u32 versal2_pmc_multi_boot(void)
{
/* At EL3 the SMC path to firmware is unavailable, read directly */
if (current_el() == 3)
return versal2_multi_boot_reg();
return zynqmp_pm_get_pmc_multi_boot_reg() & PMC_MULTI_BOOT_MASK;
}
#endif
int zynqmp_pm_feature(const u32 api_id)
{
int ret;
drivers/fpga/altera.c
+2 -4
View File
@@ -12,8 +12,7 @@
/*
* Altera FPGA support
*/
#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \
IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10)
#if IS_ENABLED(CONFIG_FPGA_INTEL_SDM_MAILBOX)
#include <asm/arch/misc.h>
#endif
#include <errno.h>
@@ -48,8 +47,7 @@ static const struct altera_fpga {
#endif
};
#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \
IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10)
#if IS_ENABLED(CONFIG_FPGA_INTEL_SDM_MAILBOX)
int fpga_is_partial_data(int devnum, size_t img_len)
{
/*
drivers/soc/soc_xilinx_zynqmp.c
+3 -1
View File
@@ -358,7 +358,9 @@ static int soc_xilinx_zynqmp_detect_machine(struct udevice *dev, u32 idcode,
} else if (device->variants & ZYNQMP_VARIANT_DR_SE) {
strlcat(priv->machine, "dr_SE", sizeof(priv->machine));
} else if (device->variants & ZYNQMP_VARIANT_TEG) {
strlcat(priv->machine, "teg", sizeof(priv->machine));
/* Devices with TEG variant might be TEG or TCG family */
strlcat(priv->machine, (idcode2 & EFUSE_GPU_DIS_MASK) ?
"tcg" : "teg", sizeof(priv->machine));
}
return 0;
drivers/ufs/ufs-amd-versal2.c
+1
View File
@@ -563,4 +563,5 @@ U_BOOT_DRIVER(ufs_versal2_pltfm) = {
.id = UCLASS_UFS,
.of_match = ufs_versal2_ids,
.probe = ufs_versal2_probe,
.priv_auto = sizeof(struct ufs_versal2_priv),
};
tools/zynqmpbif.c
+12
View File
@@ -191,6 +191,7 @@ static char *parse_partition_owner(char *line, struct bif_entry *bf)
}
static const struct bif_flags bif_flags[] = {
{ "init", BIF_FLAG_INIT },
{ "fsbl_config", BIF_FLAG_FSBL_CONFIG },
{ "trustzone", BIF_FLAG_TZ },
{ "pmufw_image", BIF_FLAG_PMUFW_IMAGE },
@@ -316,6 +317,15 @@ static int bif_add_pmufw(struct bif_entry *bf, const char *data, size_t len)
return 0;
}
static int bif_add_reginit(struct bif_entry *init)
{
/* User can pass in text file with init list */
if (strlen(init->filename))
zynqmpimage_parse_initparams(bif_output.header, init->filename);
return 0;
}
static int bif_add_part(struct bif_entry *bf, const char *data, size_t len)
{
size_t parthdr_offset = 0;
@@ -340,6 +350,8 @@ static int bif_add_part(struct bif_entry *bf, const char *data, size_t len)
if (bf->flags & (1ULL << BIF_FLAG_PMUFW_IMAGE))
return bif_add_pmufw(bf, data, len);
else if (bf->flags & (1ULL << BIF_FLAG_INIT))
return bif_add_reginit(bf);
r = bif_add_blob(data, len, &bf->offset);
if (r)
tools/zynqmpimage.c
+2 -2
View File
@@ -400,8 +400,8 @@ static void zynqmpimage_pmufw(struct zynqmp_header *zynqhdr,
fclose(fpmu);
}
static void zynqmpimage_parse_initparams(struct zynqmp_header *zynqhdr,
const char *filename)
void zynqmpimage_parse_initparams(struct zynqmp_header *zynqhdr,
const char *filename)
{
FILE *fp;
struct zynqmp_reginit reginit;
tools/zynqmpimage.h
+2
View File
@@ -142,6 +142,8 @@ struct zynqmp_header {
void zynqmpimage_default_header(struct zynqmp_header *ptr);
void zynqmpimage_print_header(const void *ptr, struct image_tool_params *params);
void zynqmpimage_parse_initparams(struct zynqmp_header *zynqhdr,
const char *filename);
static inline struct image_header_table *
zynqmp_get_iht(const struct zynqmp_header *zynqhdr)