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Merge tag 'u-boot-imx-master-20240813' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Browse Source 
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/22014

- Convert tqma6q_mba6 to watchdog DM to fix reset.
- Convert tqma6q_mba6 to PMIC and I2C DM.
- Convert tqma6q_mba6 to OF_UPSTREAM.
- Do not print the board name twice on tqma6.
- Enable CMD_ERASEENV for imx8mm/mp Phytec boards.
- Add imx8ulp binman support.
- Fix imx8 build when CONFIG_IMX_BOOTAUX is set.
This commit is contained in:
Tom Rini
2024-08-13 10:10:29 -06:00
parent 06dceeba3d 72801d9971
commit 90270e0f71
37 changed files with 236 additions and 489 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/dts/Makefile
-4
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@@ -764,8 +764,6 @@ dtb-y += \
imx6dl-icore.dtb \
imx6dl-icore-mipi.dtb \
imx6dl-icore-rqs.dtb \
imx6dl-mba6a.dtb \
imx6dl-mba6b.dtb \
imx6dl-mamoj.dtb \
imx6dl-nitrogen6x.dtb \
imx6dl-pico.dtb \
@@ -815,8 +813,6 @@ dtb-y += \
imx6q-kp.dtb \
imx6q-logicpd.dtb \
imx6q-marsboard.dtb \
imx6q-mba6a.dtb \
imx6q-mba6b.dtb \
imx6q-mccmon6.dtb\
imx6q-nitrogen6x.dtb \
imx6q-novena.dtb \
arch/arm/dts/imx6dl-mba6b-u-boot.dtsi
+3
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@@ -0,0 +1,3 @@
// SPDX-License-Identifier: GPL-2.0
#include "imx6qdl-mba6-u-boot.dtsi"
arch/arm/dts/imx6dl-mba6b.dts
-21
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@@ -1,21 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*
* Copyright 2013-2021 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6dl-tqma6b.dtsi"
#include "imx6qdl-mba6.dtsi"
#include "imx6qdl-mba6b.dtsi"
#include "imx6dl-mba6.dtsi"
/ {
model = "TQ TQMa6S/DL on MBa6x";
compatible = "tq,imx6dl-mba6x-b", "tq,mba6b",
"tq,imx6dl-tqma6dl-b", "fsl,imx6dl";
};
arch/arm/dts/imx6dl-tqma6a.dtsi
-16
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@@ -1,16 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
* Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
*/
#include "imx6dl.dtsi"
#include "imx6qdl-tqma6a.dtsi"
#include "imx6qdl-tqma6.dtsi"
/ {
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x20000000>;
};
};
arch/arm/dts/imx6dl-tqma6b.dtsi
-16
View File
@@ -1,16 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
* Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
*/
#include "imx6dl.dtsi"
#include "imx6qdl-tqma6b.dtsi"
#include "imx6qdl-tqma6.dtsi"
/ {
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x20000000>;
};
};
arch/arm/dts/imx6q-mba6b-u-boot.dtsi
+3
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@@ -0,0 +1,3 @@
// SPDX-License-Identifier: GPL-2.0
#include "imx6qdl-mba6-u-boot.dtsi"
arch/arm/dts/imx6q-mba6b.dts
-20
View File
@@ -1,20 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*
* Copyright 2013-2021 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
/dts-v1/;
#include "imx6q-tqma6b.dtsi"
#include "imx6qdl-mba6.dtsi"
#include "imx6qdl-mba6b.dtsi"
#include "imx6q-mba6.dtsi"
/ {
model = "TQ TQMa6Q on MBa6x";
compatible = "tq,imx6q-mba6x-b", "tq,mba6b",
"tq,imx6q-tqma6q-b", "fsl,imx6q";
};
arch/arm/dts/imx6q-tqma6a.dtsi
-16
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@@ -1,16 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
* Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
*/
#include "imx6q.dtsi"
#include "imx6qdl-tqma6a.dtsi"
#include "imx6qdl-tqma6.dtsi"
/ {
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
};
arch/arm/dts/imx6q-tqma6b.dtsi
-15
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@@ -1,15 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*/
#include "imx6q.dtsi"
#include "imx6qdl-tqma6b.dtsi"
#include "imx6qdl-tqma6.dtsi"
/ {
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
};
arch/arm/dts/imx6qdl-mba6-u-boot.dtsi
+15
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@@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
#include "imx6qdl-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
bootph-pre-ram;
};
};
&wdog1 {
bootph-pre-ram;
};
arch/arm/dts/imx6qdl-tqma6.dtsi
-215
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@@ -1,215 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
* Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "supply-3p3v";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
status = "okay";
m25p80: flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
m25p,fast-read;
};
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
/* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b099
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0xb099
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb099
/* eCSPI1 SS1 */
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0xb099
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899
>;
};
pinctrl_i2c1_recovery: i2c1recoverygrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b899
MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b899
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b899
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899
>;
};
pinctrl_i2c3_recovery: i2c3recoverygrp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b899
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b899
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b099 /* PMIC irq */
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
};
&pmic {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio6>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
regulators {
reg_vddcore: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
reg_vddsoc: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
reg_gen_3v3: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_ddr_1v5a: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
reg_ddr_1v5b: sw3b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5v_600mA: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
regulator-always-on;
};
reg_snvs_3v: vsnvs {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
reg_vrefddr: vrefddr {
regulator-boot-on;
regulator-always-on;
};
reg_vgen1_1v5: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
/* not used */
};
reg_vgen2_1v2_eth: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
reg_vgen3_2v8: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen4_1v8: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen5_1v8_eth: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen6_3v3: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
/* eMMC */
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
vmmc-supply = <&reg_3p3v>;
non-removable;
disable-wp;
no-sd;
no-sdio;
bus-width = <8>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
mmccard: mmccard@0 {
reg = <0>;
compatible = "mmc-card";
broken-hpi;
};
};
arch/arm/dts/imx6qdl-tqma6a.dtsi
-53
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@@ -1,53 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
* Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
*/
#include <dt-bindings/gpio/gpio.h>
&fec {
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
};
&i2c1 {
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_recovery>;
scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <100000>;
status = "okay";
pmic: pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
};
sensor@48 {
compatible = "national,lm75";
reg = <0x48>;
};
eeprom@50 {
compatible = "st,24c64", "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
};
&iomuxc {
/*
* This pinmuxing is required for the ERR006687 workaround. Board
* DTS files that enable the FEC controller with
* fsl,err006687-workaround-present must include this group.
*/
pinctrl_enet_fix: enetfixgrp {
fsl,pins = <
/* ENET ping patch */
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
};
arch/arm/dts/imx6qdl-tqma6b.dtsi
-33
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@@ -1,33 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2013 Sascha Hauer, Pengutronix
* Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
*/
#include <dt-bindings/gpio/gpio.h>
&i2c3 {
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_recovery>;
scl-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <100000>;
status = "okay";
pmic: pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
};
sensor@48 {
compatible = "national,lm75";
reg = <0x48>;
};
eeprom@50 {
compatible = "st,24c64", "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
};
arch/arm/dts/imx8ulp-evk-u-boot.dtsi
+2
View File
@@ -3,6 +3,8 @@
* Copyright 2021 NXP
*/
#include "imx8ulp-u-boot.dtsi"
/ {
mu@27020000 {
compatible = "fsl,imx8ulp-mu";
arch/arm/dts/imx8ulp-u-boot.dtsi
+63
View File
@@ -0,0 +1,63 @@
// SPDX-License-Identifier: GPL-2.0+
#ifdef CONFIG_BINMAN
/ {
binman: binman {
multiple-images;
};
};
&binman {
u-boot-spl-ddr {
align = <4>;
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
u-boot-spl {
align-end = <4>;
filename = "u-boot-spl.bin";
};
};
spl {
filename = "spl.bin";
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8image -e 0x22020000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
u-boot-container {
filename = "u-boot-container.bin";
mkimage {
args = "-n u-boot-container.cfgout -T imx8image -e 0x0";
blob {
filename = "u-boot.bin";
};
};
};
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
spl: blob-ext@1 {
filename = "spl.bin";
offset = <0x0>;
align-size = <0x400>;
align = <0x400>;
};
uboot: blob-ext@2 {
filename = "u-boot-container.bin";
};
};
};
#endif
arch/arm/mach-imx/Makefile
+2 -2
View File
@@ -129,7 +129,7 @@ DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctre
else ifeq ($(CONFIG_ARCH_IMX8M), y)
IMAGE_TYPE := imx8mimage
DEPFILE_EXISTS := 0
else ifeq ($(CONFIG_ARCH_IMX9), y)
else ifeq ($(CONFIG_ARCH_IMX9)$(CONFIG_ARCH_IMX8ULP), y)
IMAGE_TYPE := imx8image
DEPFILE_EXISTS := 0
else
@@ -215,7 +215,7 @@ flash.bin: spl/u-boot-spl.bin FORCE
endif
endif
ifeq ($(CONFIG_ARCH_IMX9), y)
ifeq ($(CONFIG_ARCH_IMX9)$(CONFIG_ARCH_IMX8ULP), y)
quiet_cmd_imx9_check = CHECK $@
cmd_imx9_check = $(srctree)/tools/imx9_image.sh $@
arch/arm/mach-imx/imx8/cpu.c
+2 -2
View File
@@ -258,14 +258,14 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
return -EIO;
}
if (!power_domain_lookup_name("audio_sai0", &pd)) {
if (!imx8_power_domain_lookup_name("audio_sai0", &pd)) {
if (power_domain_on(&pd)) {
printf("Error power on SAI0\n");
return -EIO;
}
}
if (!power_domain_lookup_name("audio_ocram", &pd)) {
if (!imx8_power_domain_lookup_name("audio_ocram", &pd)) {
if (power_domain_on(&pd)) {
printf("Error power on HIFI RAM\n");
return -EIO;
arch/arm/mach-imx/imx8ulp/Kconfig
+1
View File
@@ -23,6 +23,7 @@ choice
config TARGET_IMX8ULP_EVK
bool "imx8ulp_evk"
select BINMAN
select IMX8ULP
select SUPPORT_SPL
select IMX8ULP_DRAM
arch/arm/mach-imx/imx8ulp/container.cfg
+7
View File
@@ -0,0 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
BOOT_FROM SD 0x400
SOC_TYPE ULP
CONTAINER
IMAGE A35 bl31.bin 0x20040000
IMAGE A35 u-boot.bin CONFIG_TEXT_BASE
arch/arm/mach-imx/imx8ulp/imximage.cfg
+9
View File
@@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0+ */
BOOT_FROM SD 0x400
SOC_TYPE ULP
APPEND mx8ulpa2-ahab-container.img
CONTAINER
IMAGE PWR upower.bin
IMAGE M40 m33_image.bin 0x1ffc2000
IMAGE A35 u-boot-spl-ddr.bin 0x22020000
board/tq/tqma6/Kconfig
+1
View File
@@ -72,6 +72,7 @@ config MBA6
select PHY_MICREL
select PHY_MICREL_KSZ90X1
select MXC_UART
imply OF_UPSTREAM
help
Select the MBa6 starterkit. This features a GigE Phy, USB, SD-Card
etc.
board/tq/tqma6/tqma6.c
+10 -56
View File
@@ -19,11 +19,9 @@
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/spi.h>
#include <fsl_esdhc_imx.h>
#include <linux/libfdt.h>
#include <i2c.h>
#include <mmc.h>
#include <power/pfuze100_pmic.h>
#include <power/pmic.h>
@@ -48,10 +46,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
@@ -170,38 +164,6 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
#endif
#endif
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
static struct i2c_pads_info tqma6_i2c3_pads = {
/* I2C3: on board LM75, M24C64, */
.scl = {
.i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL,
I2C_PAD_CTRL),
.gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05,
I2C_PAD_CTRL),
.gp = IMX_GPIO_NR(1, 5)
},
.sda = {
.i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA,
I2C_PAD_CTRL),
.gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06,
I2C_PAD_CTRL),
.gp = IMX_GPIO_NR(1, 6)
}
};
static void tqma6_setup_i2c(void)
{
int ret;
/*
* use logical index for bus, e.g. I2C1 -> 0
* warn on error
*/
ret = setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
if (ret)
printf("setup I2C3 failed: %d\n", ret);
}
#endif
int board_early_init_f(void)
{
return tqma6_bb_board_early_init_f();
@@ -215,10 +177,6 @@ int board_init(void)
#ifndef CONFIG_DM_SPI
tqma6_iomuxc_spi();
#endif
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
tqma6_setup_i2c();
#endif
tqma6_bb_board_init();
return 0;
@@ -246,21 +204,22 @@ static const char *tqma6_get_boardname(void)
};
}
#if CONFIG_IS_ENABLED(POWER_LEGACY)
#if CONFIG_IS_ENABLED(DM_PMIC)
/* setup board specific PMIC */
int power_init_board(void)
{
struct pmic *p;
struct udevice *dev;
u32 reg, rev;
int ret;
power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS);
p = pmic_get("PFUZE100");
if (p && !pmic_probe(p)) {
pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
pmic_reg_read(p, PFUZE100_REVID, &rev);
printf("PMIC: PFUZE100 ID=0x%02x REV=0x%02x\n", reg, rev);
}
ret = pmic_get("pmic@8", &dev);
if (ret < 0)
return 0;
reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
rev = pmic_reg_read(dev, PFUZE100_REVID);
printf("PMIC: PFUZE100 ID=0x%02x REV=0x%02x\n", reg, rev);
return 0;
}
#endif
@@ -271,11 +230,6 @@ int board_late_init(void)
tqma6_bb_board_late_init();
return 0;
}
int checkboard(void)
{
printf("Board: %s on a %s\n", tqma6_get_boardname(),
tqma6_bb_get_boardname());
return 0;
common/spl/Kconfig
+1 -1
View File
@@ -206,7 +206,7 @@ config SPL_BINMAN_SYMBOLS
config SPL_BINMAN_UBOOT_SYMBOLS
bool "Declare binman symbols for U-Boot phases in SPL"
depends on SPL_BINMAN_SYMBOLS
default n if ARCH_IMX8M || ARCH_IMX9
default n if ARCH_IMX8M || ARCH_IMX8ULP || ARCH_IMX9
default y
help
This enables use of symbols in SPL which refer to U-Boot phases,
common/spl/Kconfig.tpl
+1 -1
View File
@@ -23,7 +23,7 @@ config TPL_BINMAN_SYMBOLS
config TPL_BINMAN_UBOOT_SYMBOLS
bool "Declare binman symbols for U-Boot phases in TPL"
depends on TPL_BINMAN_SYMBOLS
default n if ARCH_IMX8M || ARCH_IMX9
default n if ARCH_IMX8M || ARCH_IMX8ULP || ARCH_IMX9
default y
help
This enables use of symbols in TPL which refer to U-Boot phases,
common/spl/Kconfig.vpl
+1 -1
View File
@@ -243,7 +243,7 @@ config VPL_BINMAN_SYMBOLS
config VPL_BINMAN_UBOOT_SYMBOLS
bool "Declare binman symbols for U-Boot phases in VPL"
depends on VPL_BINMAN_SYMBOLS
default n if ARCH_IMX8M || ARCH_IMX9
default n if ARCH_IMX8M || ARCH_IMX8ULP || ARCH_IMX9
default y
help
This enables use of symbols in VPL which refer to U-Boot phases,
configs/imx8ulp_evk_defconfig
+2 -1
View File
@@ -8,7 +8,7 @@ CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x400000
CONFIG_IMX_CONFIG=""
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx8ulp/imximage.cfg"
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk"
CONFIG_SPL_TEXT_BASE=0x22020000
@@ -38,6 +38,7 @@ CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx8ulp/container.cfg"
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
configs/tqma6dl_mba6_mmc_defconfig
+5 -1
View File
@@ -7,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6DL=y
CONFIG_TARGET_TQMA6=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b"
CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6dl-mba6b"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SUPPORT_RAW_INITRD=y
@@ -17,6 +17,7 @@ CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run mmcboot; run netboot; run panicboot"
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
CONFIG_SYS_PBSIZE=532
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
CONFIG_CMD_BOOTZ=y
@@ -65,5 +66,8 @@ CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_IMX_WATCHDOG=y
configs/tqma6dl_mba6_spi_defconfig
+4 -1
View File
@@ -9,7 +9,7 @@ CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_MX6DL=y
CONFIG_TARGET_TQMA6=y
CONFIG_TQMA6X_SPI_BOOT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b"
CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6dl-mba6b"
CONFIG_ENV_OFFSET_REDUND=0x90000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -69,5 +69,8 @@ CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_IMX_WATCHDOG=y
configs/tqma6q_mba6_mmc_defconfig
+4 -1
View File
@@ -7,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6Q=y
CONFIG_TARGET_TQMA6=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-mba6b"
CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6q-mba6b"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SUPPORT_RAW_INITRD=y
@@ -65,5 +65,8 @@ CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_IMX_WATCHDOG=y
configs/tqma6q_mba6_spi_defconfig
+5 -2
View File
@@ -9,7 +9,7 @@ CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_MX6Q=y
CONFIG_TARGET_TQMA6=y
CONFIG_TQMA6X_SPI_BOOT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-mba6b"
CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6q-mba6b"
CONFIG_ENV_OFFSET_REDUND=0x90000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -18,7 +18,7 @@ CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="sf probe; run mmcboot; run netboot; run panicboot"
CONFIG_DEFAULT_FDT_FILE="imx6q-mba6x.dtb"
CONFIG_DEFAULT_FDT_FILE="nxp/imx/imx6q-mba6x.dtb"
CONFIG_SYS_PBSIZE=532
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
@@ -69,5 +69,8 @@ CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_IMX_WATCHDOG=y
configs/tqma6s_mba6_mmc_defconfig
+4 -1
View File
@@ -7,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_MX6S=y
CONFIG_TARGET_TQMA6=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b"
CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6dl-mba6b"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SUPPORT_RAW_INITRD=y
@@ -65,5 +65,8 @@ CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_IMX_WATCHDOG=y
configs/tqma6s_mba6_spi_defconfig
+4 -1
View File
@@ -9,7 +9,7 @@ CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_MX6S=y
CONFIG_TARGET_TQMA6=y
CONFIG_TQMA6X_SPI_BOOT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b"
CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6dl-mba6b"
CONFIG_ENV_OFFSET_REDUND=0x90000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -69,5 +69,8 @@ CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_IMX_WATCHDOG=y
doc/board/nxp/imx8ulp_evk.rst
+79
View File
@@ -0,0 +1,79 @@
.. SPDX-License-Identifier: GPL-2.0+
imx8ulp_evk
=======================
U-Boot for the NXP i.MX 8ULP EVK board
Quick Start
-----------
- Get and Build the ARM Trusted firmware
- Get the uPower firmware
- Get the M33 firmware
- Get ahab-container.img
- Build U-Boot
- Boot
Get and Build the ARM Trusted firmware
--------------------------------------
Note: srctree is U-Boot source directory
Get ATF from: https://github.com/nxp-imx/imx-atf/
branch: lf_v2.10
.. code-block:: bash
$ unset LDFLAGS
$ make PLAT=imx8ulp bl31
$ cp build/imx8ulp/release/bl31.bin $(srctree)
Get the uPower firmware
-----------------------
.. code-block:: bash
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-upower-1.3.1.bin
$ chmod +x firmware-upower-1.3.1.bin
$ ./firmware-upower-1.3.1.bin
$ cp firmware-upower-1.3.1/upower_a1.bin $(srctree)/upower.bin
Get the M33 firmware
--------------------
.. code-block:: bash
$ wget http://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx8ulp-m33-demo-2.14.1.bin
$ chmod +x imx8ulp-m33-demo-2.14.1.bin
$ ./imx8ulp-m33-demo-2.14.1.bin
$ cp imx8ulp-m33-demo-2.14.1/imx8ulp_m33_TCM_power_mode_switch.bin $(srctree)/m33_image.bin
Get ahab-container.img
---------------------------------------
.. code-block:: bash
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-0.1.2-4ed450a.bin
$ chmod +x firmware-ele-imx-0.1.2-4ed450a.bin
$ ./firmware-ele-imx-0.1.2-4ed450a.bin
$ cp firmware-ele-imx-0.1.2-4ed450a/mx8ulpa2-ahab-container.img $(srctree)
Build U-Boot
------------
.. code-block:: bash
$ export CROSS_COMPILE=aarch64-poky-linux-
$ make imx8ulp_evk_defconfig
$ make
Burn the flash.bin to MicroSD card offset 32KB:
.. code-block:: bash
$ dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc
Boot
----
Set Boot switch to SD boot
doc/board/nxp/index.rst
+1
View File
@@ -11,6 +11,7 @@ NXP Semiconductors
imx8mp_evk
imx8mq_evk
imx8qxp_mek
imx8ulp_evk
imx93_11x11_evk
imxrt1020-evk
imxrt1050-evk
include/configs/tqma6.h
-8
View File
@@ -26,14 +26,6 @@
#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K
/* I2C Configs */
#define CFG_I2C_MULTI_BUS
#if !defined(CONFIG_DM_PMIC)
#define CFG_POWER_PFUZE100_I2C_ADDR 0x08
#define TQMA6_PFUZE100_I2C_BUS 2
#endif
/* MMC Configs */
#define CFG_SYS_FSL_ESDHC_ADDR 0
include/imx8image.h
+1
View File
@@ -162,6 +162,7 @@ enum imx8image_cmd {
enum imx8image_core_type {
CFG_CORE_INVALID,
CFG_SCU,
CFG_PWR,
CFG_M40,
CFG_M41,
CFG_A35,
tools/imx8image.c
+6 -1
View File
@@ -57,6 +57,7 @@ static table_entry_t imx8image_cmds[] = {
static table_entry_t imx8image_core_entries[] = {
{CFG_SCU, "SCU", "scu core", },
{CFG_PWR, "PWR", "uPower core", },
{CFG_M40, "M40", "M4 core 0", },
{CFG_M41, "M41", "M4 core 1", },
{CFG_A35, "A35", "A35 core", },
@@ -119,7 +120,7 @@ static void parse_cfg_cmd(image_t *param_stack, int32_t cmd, char *token,
} else if (!strncmp(token, "IMX8QM", 6)) {
soc = QM;
} else if (!strncmp(token, "ULP", 3)) {
soc = IMX9;
soc = ULP;
} else if (!strncmp(token, "IMX9", 4)) {
soc = IMX9;
} else {
@@ -181,6 +182,10 @@ static void parse_cfg_fld(image_t *param_stack, int32_t *cmd, char *token,
param_stack[p_idx].option = SCFW;
param_stack[p_idx++].filename = token;
break;
case CFG_PWR:
param_stack[p_idx].option = UPOWER;
param_stack[p_idx++].filename = token;
break;
case CFG_M40:
param_stack[p_idx].option = M40;
param_stack[p_idx].ext = 0;