Squashed 'dts/upstream/' changes from 9b6ba2666d63..8531b4b4988c

8531b4b4988c Merge tag 'v6.13-rc7-dts-raw'
4dc7423c0128 Merge tag 'char-misc-6.13-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
a8433d3afa99 Merge tag 'soc-fixes-6.13-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
232823fd4930 Merge tag 'drm-fixes-2025-01-11' of https://gitlab.freedesktop.org/drm/kernel
ddf448187a99 Merge tag 'v6.13-rockchip-dtsfixes1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
326341ea6a5a Merge tag 'mediatek-drm-fixes-20250104' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-fixes
c817d4d4421f Merge tag 'imx-fixes-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
be9c0a553356 Merge tag 'qcom-arm64-fixes-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes
6d09f4fb518a arm64: dts: rockchip: add hevc power domain clock to rk3328
d1aa06cb62af dt-bindings: net: pse-pd: Fix unusual character in documentation
5ffa3ec7f447 arm64: dts: rockchip: Fix the SD card detection on NanoPi R6C/R6S
f4dbf6bea17a Merge tag 'v6.13-rc6-dts-raw'
136084c9071b Merge tag 'drm-misc-fixes-2025-01-02' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-fixes
5f6a873e4c1f dt-bindings: display: mediatek: dp: Reference common DAI properties
6ff7bb898acb Merge tag 'v6.13-rc5-dts-raw'
f8bafac28c32 Merge tag 'sound-6.13-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
fc831d50be9f arm64: dts: qcom: sa8775p: fix the secure device bootup issue
029bcca18358 Merge tag 'v6.13-rc4-dts-raw'
f20911601a36 Merge tag 'devicetree-fixes-for-6.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
8f7fab85f2a7 Merge tag 'soc-fixes-6.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
32d1c97c87fb Merge tag 'arm-soc/for-6.13/devicetree-arm64-fixes' of https://github.com/Broadcom/stblinux into arm/fixes
691b34dd7d9f dt-bindings: display: adi,adv7533: Drop single lane support
62da87b44171 Revert "arm64: dts: qcom: x1e80100: enable OTG on USB-C controllers"
11d19fa272bb Revert "arm64: dts: qcom: x1e80100-crd: enable otg on usb ports"
afdfc5f25296 arm64: dts: broadcom: Fix L2 linesize for Raspberry Pi 5
33793000f4a4 arm64: dts: qcom: x1e80100: Fix up BAR space size for PCIe6a
5d5a71565a1c Revert "arm64: dts: qcom: x1e78100-t14s: enable otg on usb-c ports"
5f53f8bb69d2 Merge tag 'soc-fixes-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
b4d2d007bfdf Merge tag 'iio-fixes-for-6.13a' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-linus
8ffbadf01db0 ASoC: dt-bindings: realtek,rt5645: Fix CPVDD voltage comment
008abf9e254a Merge tag 'v6.13-rc3-dts-raw'
a8fc9cf94eb5 Merge tag 'arc-6.13-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
2c35fa0d488f Merge tag 'usb-6.13-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
3e232d1e666c ARC: dts: Replace deprecated snps,nr-gpios property for snps,dw-apb-gpio-port devices
f745a9511362 Merge tag 'juno-fix-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/fixes
fbf5077068b9 regulator: dt-bindings: qcom,qca6390-pmu: document wcn6750-pmu
37ab64667e47 ARM: dts: imxrt1050: Fix clocks for mmc
dab0a5e156fb arm64: dts: imx95: correct the address length of netcmix_blk_ctrl
7eae94b44a89 Merge tag 'v6.13-rc2-dts-raw'
e78a7e2b0cd7 arm64: dts: imx8-ss-audio: add fallback compatible string fsl,imx6ull-esai for esai
45813ccd2a7b dt-bindings: iio: st-sensors: Re-add IIS2MDC magnetometer
1946afa68c64 Merge tag 'pmdomain-v6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
f1f0da779072 Merge tag 'linux-watchdog-6.13-rc1' of git://www.linux-watchdog.org/linux-watchdog
d763929c7513 arm64: dts: fvp: Update PCIe bus-range property
54996f58c80e dt-bindings: phy: imx8mq-usb: correct reference to usb-switch.yaml
b1aa978c13bf dt-bindings: mtd: fixed-partitions: Fix "compression" typo
bdb818f3713b arm64: dts: rockchip: rename rfkill label for Radxa ROCK 5B
63c1a08a6ade arm64: dts: rockchip: add reset-names for combphy on rk3568
ba53ae02e092 dt-bindings: power: mediatek: Add another nested power-domain layer
07d0c70010a5 Merge tag 'v6.13-rc1-dts-raw'
5637b45be13b arm64: dts: qcom: sa8775p: Fix the size of 'addr_space' regions
9b262efab34c Merge tag 'i2c-for-6.13-rc1-part3' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
ed44ac60a90e Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
edfdcfeb9045 Merge tag 'rtc-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
a814b904106d Merge tag 'tty-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
bbb47e849ae5 Merge tag 'char-misc-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
e63bdbcacef6 Merge tag 'staging-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging
f19ac76126e4 Merge tag 'usb-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
556f16e8ae4c Merge tag 'mips_6.13_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
5e598b221885 Merge tag 'regulator-fix-v6.13-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
1206af144c4a Merge tag 'for-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply
4b78bb4b845e Merge tag 'pm-6.13-rc1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
2b75cf774b29 Merge tag 'phy-for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
ea19b796a46c Merge tag 'dmaengine-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
1133f1ec2065 Merge tag 'riscv-for-linus-6.13-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
746c372b8ad6 Merge tag 'loongarch-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
4fed1a0b1885 Merge branch 'pm-opp'
fc3ef2d2a08a Merge tag 'kvm-riscv-6.13-2' of https://github.com/kvm-riscv/linux into HEAD
211c1fea1d18 Merge tag 'riscv-for-linus-6.13-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux into HEAD
5bbcb87b4e8a dt-bindings: Unify "fsl,liodn" type definitions
11712cccac6a arm64: dts: mediatek: mt8173-elm-hana: Mark touchscreens and trackpads as fail
3412036f44ec Merge tag 'rproc-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
f6916ccc6810 Merge tag 'pci-v6.13-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
c8ac80d24539 LoongArch: dts: Add I2S support to Loongson-2K2000
78c8af2e4435 LoongArch: dts: Add I2S support to Loongson-2K1000
dd845634778c Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
c371d27c22df Merge tag 'mailbox-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox
318d6ab86b21 Merge tag 'pinctrl-v6.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
593d0bf860b6 Merge tag 'i2c-for-6.13-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
e958eeea5d92 Merge branch 'pci/controller/qcom'
801c1432c854 Merge branch 'pci/controller/microchip'
eae7c4992556 Merge tag 'input-for-v6.13-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
fe51d1a81fe8 dt-bindings: mailbox: Add thead,th1520-mailbox bindings
d117c6077557 dt-bindings: mailbox: qcom-ipcc: Add SM8750
a5d0d60dc7b1 dt-bindings: mailbox: qcom,apcs-kpss-global: correct expected clocks for fallbacks
8abe9b373f38 dt-bindings: mailbox: qcom-ipcc: Add SAR2130P compatible
81b4a2d4a0c3 dt-bindings: mailbox: mpfs: fix reg properties
a45ebe5f9f40 dt-bindings: i2c: snps,designware-i2c: declare bus capacitance and clk freq optimized
2ee96fbc8c27 dt-bindings: i2c: nomadik: support 400kHz < clock-frequency <= 3.4MHz
a0589920dc8b dt-bindings: i2c: nomadik: add mobileye,eyeq6h-i2c bindings
35d18ffaacbc dt-bindings: i2c: mv64xxx: Add Allwinner A523 compatible string
ca13487bccee MIPS: Loongson64: DTS: Really fix PCIe port nodes for ls7a
dada4910fa78 Merge tag 'iommu-updates-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux
a97f5234955e Merge tag 'thermal-6.13-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
89534c5c0ee3 Merge tag 'pm-6.13-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
eb0295acbf42 Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
c299ef125ca8 Merge tag 'backlight-next-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight
65a2f98075d6 Merge tag 'leds-next-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/leds
b6fddbbdea9e Merge tag 'mfd-next-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
590065c0905d Merge tag 'drm-next-2024-11-21' of https://gitlab.freedesktop.org/drm/kernel
dc4900bf152f Merge tag 'sound-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
5d1a70ddfc54 Merge tag 'i2c-for-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
c6ee89ab9656 Merge tag 'net-next-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next
4535ffa44df9 dt-bindings: riscv: Add Svade and Svadu Entries
c8aedfade1c8 Merge tag 'soc-drivers-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
61b798afa773 Merge tag 'soc-dt-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
37c659acf984 mips: dts: realtek: Add SPI NAND controller
94d5730e0e14 Merge tag 'media/v6.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
e6d79eee5678 Merge tag 'hid-for-linus-2024111801' of git://git.kernel.org/pub/scm/linux/kernel/git/hid/hid
f787d015b4d0 Merge tag 'devicetree-for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
bf1e79882185 Merge tag 'mmc-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
a2fa4706a249 Merge tag 'pmdomain-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
bff422d6c9a5 Merge tag 'gpio-updates-for-v6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
f198cc9328e2 Merge tag 'pwm/for-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux
b5f1623d4cf5 Merge tag 'spi-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
0fb4cce57122 Merge tag 'regulator-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
f78409f8ed71 Merge tag 'timers-core-2024-11-18' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
f9da6fbe19f3 Merge tag 'irq-core-2024-11-18' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
d899fe1de24b Merge tag 'thermal-v6.13-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/thermal/linux
2fc3f7277835 Merge tag 'opp-updates-6.13' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/vireshk/pm
7e7b0e62a08d Merge tag 'cpufreq-arm-updates-6.13' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/vireshk/pm
092aa09090cc Merge tag 'edac_updates_for_v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras
5122a15a7641 Merge tag 'hwmon-for-v6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging
3707c212dfd4 Merge tag 'v6.13-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
406bc7dd4a19 dt-bindings: regulator: qcom-labibb-regulator: document the pmi8950 labibb regulator
8c237be9ce96 arm64: dts: apm: Remove unused and undocumented "bus_num" property
013cc605fbdd arm: dts: spear13xx: Remove unused and undocumented "pl022,slave-tx-disable" property
92cd6f965727 arm64: dts: amd: Remove unused and undocumented "amd,zlib-support" property
054fb11029ed Merge tag 'sunxi-fixes-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
0813b7768a18 Merge branches 'clk-marvell', 'clk-adi', 'clk-qcom' and 'clk-devm' into clk-next
732a2ef869ae Merge branches 'clk-samsung', 'clk-microchip', 'clk-imx', 'clk-amlogic' and 'clk-allwinner' into clk-next
9c8d2f73021e Merge branches 'clk-mobileye', 'clk-twl', 'clk-nuvoton', 'clk-renesas' and 'clk-bindings' into clk-next
e5eb1f3324f9 Merge branches 'clk-cleanup', 'clk-mediatek', 'clk-kunit', 'clk-xilinx' and 'clk-fixed-gate' into clk-next
bfaae6ff9e59 Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
68283c980cd9 Merge tag 'mips_6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
79bfc7441791 Merge tag 'for-6.13/block-20241118' of git://git.kernel.dk/linux
0c01c94ca0e4 Merge tag 'ata-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/libata/linux
3a3ade96051d dt-bindings: net: renesas,ether: Drop undocumented "micrel,led-mode"
26283f99abfc Merge branch 'for-6.13/goodix' into for-linus
94a60aceafae Merge tag 'asoc-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-next
494ff953c027 Merge tag 'i2c-host-6.13-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow
c53be2ce2415 arm64: dts: qcom: sc8180x: Add a SoC-specific compatible to cpufreq-hw
2b8e420a3270 dt-bindings: cpufreq: cpufreq-qcom-hw: Add SC8180X compatible
6596841d5093 dt-bindings: i2c: Add Realtek RTL I2C Controller
bca673ba1132 dt-bindings: i2c: imx: add SoC specific compatible strings for S32G
4526cf8d2335 dt-bindings: i2c: microchip: corei2c: Add PIC64GX as compatible with driver
5aeeb0598129 dt-bindings: i2c: qcom-cci: Document SDM670 compatible
54f022df57b2 dt-bindings: usb: maxim,max33359: add usage of sink bc12 time property
1ed83030fdb3 dt-bindings: connector: Add time property for Sink BC12 detection completion
85167dc2ae25 dt-bindings: remoteproc: qcom,sm8350-pas: add SAR2130P aDSP compatible
83bca830540d dt-bindings: remoteproc: qcom,sm8550-pas: Add SM8750 ADSP
2bdefd8183a1 dt-bindings: net: dsa: microchip,ksz: Drop undocumented "id"
6eb17b2bd78c Merge tag 'for-net-next-2024-11-14' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next
2a14ef2ac5e0 Merge branch 'dt/linus' into dt/next
bae5aba3f9a3 MIPS: mobileye: eyeq6h: add OLB nodes OLB and remove fixed clocks
bc1acfc7ba28 MIPS: mobileye: eyeq5: use OLB as provider for fixed factor clocks
20d38d5ed30c Merge branches 'arm/smmu', 'mediatek', 's390', 'ti/omap', 'riscv' and 'core' into next
a0794b374609 dt-bindings: net: sff,sfp: Fix "interrupts" property typo
15f59fa95127 dt-bindings: net: mdio-mux-gpio: Drop undocumented "marvell,reg-init"
abaa833875a2 dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks
d4692890e218 dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles
8b8b3b527dd8 dt-bindings: clock: axi-clkgen: include AXI clk
0fb8688d489e Merge tag 'v6.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-bindings
8082b4609710 dt-bindings: clock: Add Marvell PXA1908 clock bindings
ec9532ca76f2 dt-bindings: clock: airoha: Update reg mapping for EN7581 SoC.
faac8e7307da dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset controllers
1ddd28078d2c dt-bindings: net: bluetooth: nxp: Add support for power save feature using GPIO
6e00e8e10462 dt-bindings: clock: actions,owl-cmu: convert to YAML
8632a52cf6bb dt-bindings: clock: ti: Convert mux.txt to json-schema
3a3d3efe9f2f ASoc: simple-mux: Allow to specify an idle-state
f1a21c9027aa ASoC: Merge up fixes
2a6f86b68aef ASoC: dt-bindings: simple-mux: add idle-state property
e57711411998 Merge tag 'at24-updates-for-v6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into i2c/for-mergewindow
c817c4dd5391 dt-bindings: net: dsa: microchip: Add LAN9646 switch support
13bd51fa1dc3 Merge tag 'wireless-next-2024-11-13' of git://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next
177c7f83ccb1 Merge tag 'at91-soc-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
3d87efe60dff Merge tag 'at91-dt-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
877c4e7469b0 dt-bindings: hwmon: isl68137: add bindings to support voltage dividers
1067dd80f2cf Merge tag 'v6.13-armsoc/drivers1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
57d263a89884 Merge tag 'qcom-drivers-for-6.13-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
166d602e19ff dt-bindings: thermal: tsens: Add MSM8937
e85bd8dc346a dt-bindings: thermal: qcom-tsens: Add SAR2130P compatible
6ec582f4202e dt-bindings: serial: Add a new compatible string for ums9632
75178b614606 regulator: dt-bindings: qcom,rpmh: Correct PM8550VE supplies
a5865ee38927 dt-bindings: pinctrl: qcom: Add sm8750 pinctrl
21b92a318c68 dt-bindings: timer: actions,owl-timer: convert to YAML
cf31a6391668 dt-bindings: input: Goodix GT7986U SPI HID Touchscreen
3e51a972eb07 Merge tag 'samsung-drivers-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
a7c4f30bb64b Merge tag 'asahi-soc-dt-6.13' of https://github.com/AsahiLinux/linux into soc/dt
a4fd8e1dfc43 Merge tag 'v6.13-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
2c162aaf86bf Merge tag 'v6.13-rockchip-dts32-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
bd05bfd61ea1 Merge tag 'sunxi-dt-for-6.13-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
b27a64825ed4 Merge tag 'riscv-dt-for-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
ba090176b165 Merge tag 'mvebu-dt64-6.13-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
6bf22927b301 Merge tag 'mvebu-dt-6.13-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
0f2aa55f6305 dt-bindings: hwmon: pwm-fan: Document start from stopped state properties
426cb331c9cc dt-bindings: hwmon: ti,tmp108: Add nxp,p3t1085 compatible string
ae309085b834 dt-bindings: hwmon: pmbus: add ti tps25990 support
5da2c2026bd2 Merge tag 'stm32-dt-for-v6.13-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
9c3899079f19 Merge tag 'ti-k3-dt-for-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
0b3cd09d6ce5 Merge tag 'amlogic-arm64-dt-for-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
f26dab644e22 Merge tag 'amlogic-arm-dt-for-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
deb57f61c6df Merge tag 'riscv-sophgo-dt-for-v6.13' of https://github.com/sophgo/linux into soc/dt
4726cfc72104 arm64: dts: lg131x: Update spi clock properties
d89970dd389d arm64: dts: seattle: Update spi clock properties
930d668738e9 Merge tag 'qcom-arm64-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
ce2d746e1530 Merge tag 'omap-for-v6.13/dt-signed-1' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/dt
f105a6053107 Merge tag 'renesas-dts-for-v6.13-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
387af474eee3 Merge tag 'mtk-dts64-for-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
53a949e36049 Merge tag 'imx-dt64-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
16f098c332bd Merge tag 'imx-dt-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
51aaab41dffd Merge tag 'imx-bindings-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
17e5fb03d215 Merge tag 'qcom-arm32-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
31626a0e0ee3 Merge tag 'socfpga_dts_updates_for_v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
152ae851dbfa Merge tag 'zynqmp-dt-for-6.13' of https://github.com/Xilinx/linux-xlnx into soc/dt
f90a49f1e27b Merge tag 'v6.13-armsoc/dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
ae55eb28a726 Merge tag 'samsung-dt64-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
3d49ae1f0a1b Merge tag 'tegra-for-6.13-arm64-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
07ff07464e33 Merge tag 'tegra-for-6.13-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
7f89fd77486c Merge tag 'ux500-dts-for-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into soc/dt
05ebe6553b4d Merge tag 'renesas-dts-for-v6.13-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
16235aeda228 Merge tag 'thead-dt-for-v6.13-p2' of https://github.com/pdp7/linux into soc/dt
6fa0b8a99183 Merge tag 'thead-dt-for-v6.13' of https://github.com/pdp7/linux into soc/dt
7e058b903582 dt-bindings: power: qcom,rpmpd: document the SM8750 RPMh Power Domains
f6a47c3457a0 dt-bindings: mfd: bd71828: Use charger resistor in mOhm instead of MOhm
4b18f1610238 Merge tag 'scmi-updates-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/drivers
dda26b78365e mips: dts: realtek: Add I2C controllers
b71367867087 mips: dts: realtek: Add syscon-reboot node
79779e7c715d dt-bindings: mfd: sprd,sc2731: Convert to YAML
5dae93564df4 dt-bindings: rtc: Add Amlogic A4 and A5 RTC
26e180301e14 dt-bindings: mfd: Add Realtek RTL9300 switch peripherals
1891c1b614b2 dt-bindings: mfd: qcom,tcsr: Add compatible for MSM8917
b1ba8faed042 dt-bindings: leds: pwm: Add default-brightness property
f399c33dfe79 dt-bindings: usb: add A523 compatible string for EHCI and OCHI
947c6f46a132 dt-bindings: usb: sunxi-musb: add Allwinner A523 compatible string
d441b40639a5 dt-bindings: ata: ahci-platform: add missing iommus property
723c65f36e60 dt-bindings: net: dsa: microchip: add mdio-parent-bus property for internal MDIO
58487abd9efe dt-bindings: net: dsa: microchip: add internal MDIO bus description
8d58a2dd6d84 dt-bindings: power: reset: Convert mode-.* properties to array
1789292f1a7c dt-bindings: power: supply: sc27xx-fg: document deprecated bat-detect-gpio
5538bdf2a501 dt-bindings: rtc: sun6i: Add Allwinner A523 support
20e517ff0e61 Merge patch series "Zacas/Zabha support and qspinlocks"
123d509ffce3 dt-bindings: riscv: Add Ziccrse ISA extension description
9442e2221b50 dt-bindings: riscv: Add Zabha ISA extension description
19eeccaea220 arm64: dts: rockchip: use less broad pinctrl for pcie3x1 on Radxa E25
f80689fcef4b arm64: dts: rockchip: add Radxa ROCK 5C
cf73817a27fe dt-bindings: arm: rockchip: add Radxa ROCK 5C
6f9651cdd68b arm64: dts: rockchip: orangepi-5-plus: Enable GPU
0969ba564561 arm64: dts: rockchip: enable USB3 on NanoPC-T6
d0831b4f29fa arm64: dts: rockchip: adapt regulator nodenames to preferred form
5b243675290c arm64: dts: rockchip: Enable HDMI display for rk3588 Cool Pi GenBook
23fd319073ff arm64: dts: rockchip: Enable HDMI display for rk3588 Cool Pi 4B
3900aca0874b arm64: dts: rockchip: Enable HDMI0 for rk3588 Cool Pi CM5 EVB
2c753fe0da98 arm64: dts: rockchip: Enable HDMI on NanoPi R6C/R6S
8e4a55566af5 arm64: dts: rockchip: Enable GPU on NanoPi R6C/R6S
7b1c800bcde2 arm64: dts: rockchip: Enable HDMI on Hardkernel ODROID-M2
c436bbae9ee0 arm64: dts: rockchip: Remove non-removable flag from sdmmc on rk3576-sige5
1980d45b0897 ASoC: dt-bindings: stm32: add missing port property
2893b7f5fb7a Merge tag 'icc-6.13-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
b32a9156b890 Merge tag 'v6.12-rc7' into __tmp-hansg-linux-tags_media_atomisp_6_13_1
c7134866aa26 Merge tag 'drm-misc-next-2024-11-08' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
9c04f56979b1 dt-bindings: Add SY24655 to ina2xx devicetree bindings
5ff094ad6592 dt-bindings: hwmon: ltc2978: add support for ltc7841
d9ef63ef8a11 dt-bindings: hwmon: Add NCT7363Y documentation
c0471d92c15c dt-bindings: hwmon: pmbus: Add bindings for Vicor pli1209bc
d5eaf6b6924f dt-bindings: hwmon: pmbus: Add bindings for MPS MP297x
cdad7d08ac3b dt-bindings: hwmon: add renesas,isl28022
cfd9365d2a13 dt-bindings: hwmon: add support for ti,amc6821
ddc5f672209b dt-bindings: rtc: mpfs-rtc: remove Lewis from maintainers
2865159e6810 dt-bindings: spmi: qcom,x1e80100-spmi-pmic-arb: Add SAR2130P compatible
c50dfc3a2aab dt-bindings: spmi: spmi-mtk-pmif: Add compatible for MT8188
a190753f88d0 arm64: dts: allwinner: a100: perf1: Add eMMC and MMC node
4991141770ff arm64: dts: allwinner: pinephone: Add mount matrix to accelerometer
e4b43ce62e72 dt-bindings: rng: add binding for BCM74110 RNG
941365ad45c2 ARM: dts: rockchip: adapt regulator nodenames to preferred form
bf61fdbdcb67 arm64: dts: rockchip: Enable HDMI0 on FriendlyElec CM3588 NAS
b20c5c1134f6 arm64: dts: rockchip: add Banana Pi P2 Pro board
e25bd251aa0e dt-bindings: arm: rockchip: add Banana Pi P2 Pro board
be5707904383 arm64: dts: rockchip: Add new SoC dtsi for the RK3566T variant
5490c2e7cf29 arm64: dts: rockchip: Prepare RK356x SoC dtsi files for per-variant OPPs
446fb0e5e919 arm64: dts: rockchip: Update CPU OPP voltages in RK356x SoC dtsi
a0399eec38f1 arm64: dts: rockchip: Add OPP voltage ranges to RK3399 OP1 SoC dtsi
edc6a2d078cf arm64: dts: rockchip: Enable HDMI0 on Indiedroid Nova
b212feea5740 arm64: dts: rockchip: Enable GPU on Indiedroid Nova
55b9ba0d6a3f arm64: dts: rockchip: correct analog audio name on Indiedroid Nova
067743d4f0ba dt-bindings: iio: adc: ad7380: add adaq4370-4 and adaq4380-4 compatible parts
86b95e793090 Merge commit '9365f0de4303f82ed4c2db1c39d3de824b249d80' into HEAD
f330887620af ASoC: stm32: i2s: add stm32mp25 support
3739109e0b30 dt-bindings: interrupt-controller: qcom,pdc: Add SAR2130P compatible
62ad47978cfe dt-bindings: Enable dtc "interrupt_provider" warnings
8aec8212bc90 ASoC: dt-bindings: add stm32mp25 support for i2s
ddcb952e0d83 ASoC: dt-bindings: add stm32mp25 support for sai
6533ea7e371c media: dt-bindings: Add qcom,msm8953-camss
0400a923076e media: dt-bindings: adv7180: Document 'adi,force-bt656-4'
cad71a536128 dt-bindings: pinctrl: sx150xq: allow gpio line naming
4fc4402b096a dt-bindings: pinctrl: pinctrl-single: add marvell,pxa1908-padconf compatible
957318c990d9 dt-bindings: pinctrl: correct typo of description for cv1800
964a6e882b70 dt-bindings: pinctrl: qcom,pmic-mpp: Document PM8937 compatible
6f8ca0d8db72 dt-bindings: pinctrl: qcom,pmic-gpio: add PM8937
f1565113396b Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
08d9d0f1c1f1 Add a driver for the Iron Device SMA1307 Amp
f2f280762a9e arm64: dts: sun50i-a64-pinephone: Add mount-matrix for PinePhone magnetometers
6a0f30875a00 arm64: dts: sun50i-a64-pinephone: Add AF8133J to PinePhone
19a5f6136083 dt-bindings: PCI: microchip,pcie-host: Add reg for Root Port 2
55fb5e5b420f dt-bindings: watchdog: Document ExynosAutoV920 watchdog bindings
054c654fe1f3 dt-bindings: watchdog: fsl-imx-wdt: Add missing 'big-endian' property
8ea12deded37 dt-bindings: watchdog: Document Qualcomm QCS8300
730c3664636b media: dt-bindings: Add OmniVision OV08X40
f9a3c027aa9d media: dt-bindings: Remove assigned-clock-* from various schema
7566186de0e0 riscv: dts: thead: Add TH1520 ethernet nodes
386669413e02 dt-bindings: interrupt-controller: Add T-HEAD C900 ACLINT SSWI device
1646cca4d199 ASoC: dt-bindings: maxim,max98390: Reference common DAI properties
ee6c807e70e1 spi: dt-bindings: apple,spi: Add binding for Apple SPI controllers
876cffaa982c ASoC: dt-bindings: irondevice,sma1307: Add initial DT
160064141ff7 Merge tag 'exynos-drm-next-for-v6.13-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next
fc688470a160 dt-bindings: net: Add T-HEAD dwmac support
9b1f83707883 dt-bindings: net: snps,dwmac: add support for Arria10
460309ffbb0c Merge branch '20240822-qcs8300-gcc-v2-1-b310dfa70ad8@quicinc.com' into clk-for-6.13
23cfc4f08cb1 dt-bindings: clock: qcom: Add GCC clocks for QCS8300
f3d1192d6712 dt-bindings: arm: qcom,ids: add SoC ID for IPQ5424/IPQ5404
42d048cdf864 Merge branch '20241028060506.246606-3-quic_srichara@quicinc.com' into clk-for-6.13
fafe71156483 dt-bindings: clock: Add Qualcomm IPQ5424 GCC binding
7e1403abe239 Merge branch '20241027-sar2130p-clocks-v5-0-ecad2a1432ba@linaro.org' into clk-for-6.13
2defff84b795 dt-bindings: clk: qcom,sm8450-gpucc: add SAR2130P compatibles
3894d09b6e84 dt-bindings: clock: qcom,sm8550-dispcc: Add SAR2130P compatible
a72e5c09c7f4 dt-bindings: clock: qcom,sm8550-tcsr: Add SAR2130P compatible
28f260417c06 dt-bindings: clock: qcom: document SAR2130P Global Clock Controller
60cc5850fdfc dt-bindings: clock: qcom,rpmhcc: Add SAR2130P compatible
df87984c1613 dt-bindings: display: samsung,exynos7-decon: add exynos7870 compatible
d50643ee756b Merge tag 'drm-msm-next-2024-11-04' of https://gitlab.freedesktop.org/drm/msm into drm-next
b3e4ab4f064e dt-bindings: firmware: qcom,scm: Document sm8750 SCM
463a6ef40f74 dt-bindings: PCI: snps,dw-pcie: Drop "#interrupt-cells" from example
03102039e316 Merge tag 'mediatek-drm-next-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next
34a8c575f1c8 ASoC: codecs: Add aw88081 amplifier driver
8f4e264ce11e ASoC: dt-bindings: everest,es8326: Document interrupt property
4e44f374d949 ASoC: dt-bindings: mediatek,mt8188-mt6359: Add mediatek,adsp property
6f4ed65f7dd8 arm64: dts: marvell: Drop undocumented SATA phy names
7b21455daa8f ASoC: dt-bindings: fsl-esai: allow fsl,imx8qm-esai fallback to fsl,imx6ull-esai
8c018a0ee4a8 ASoC: dt-bindings: qcom,sm8250: Add SM8750 sound card
8a48011ba43b ASoC: dt-bindings: sprd,sc9860-mcdt: convert to YAML
7b4ce90e74f0 ASoC: dt-bindings: sprd,pcm-platform: convert to YAML
5823f4fe0659 ASoC: dt-bindings: fsl_spdif: Document imx6sl/sx compatible fallback
7e14eb16d5b3 dt-bindings: usb: qcom,dwc3: Add SAR2130P compatible
51bf70618e24 Merge branch 'for-linus' into for-next
22f3676ff712 ARM: dts: microchip: sam9x75_curiosity: add sam9x75 curiosity board
47d31036aa61 dt-bindings: arm: add sam9x75 curiosity board
0501f23b39df ARM: dts: at91: sam9x7: add device tree for SoC
d5a9f68a0aea dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
70e9f6df13a8 dt-bindings: display: Document dual-link LVDS display common properties
6934292e075c dt-bindings: display: lvds-data-mapping: Add 30-bit RGB pixel data mappings
6f27127c4a26 dt-bindings: watchdog: airoha: document watchdog for Airoha EN7581
daa8216ec644 Merge v6.12-rc6 into usb-next
056bfa125b25 Merge 6.12-rc6 into char-misc-next
4161d4c159eb dt-bindings: input: rotary-encoder: Fix "rotary-encoder,rollover" type
a687918c0646 dt-bindings: nvmem: sprd,sc2731-efuse: convert to YAML
1aa204d6b806 dt-bindings: nvmem: sprd,ums312-efuse: convert to YAML
d1d8d849187e dt-bindings: nvmem: convert zii,rave-sp-eeprom.txt to yaml format
17763c48b366 dt-bindings: fuse: Move renesas,rcar-{efuse,otp} to nvmem
9654bb88a716 Merge branch 'icc-sar2130p' into icc-next
dd017956b3ce Merge branch 'icc-qcs615' into icc-next
a17c617ee41c Merge branch 'icc-qcs8300' into icc-next
8370d645f4b6 Merge tag 'mtk-soc-for-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into arm/drivers
53631c4ff314 Merge tag 'drm-msm-next-2024-10-28' of https://gitlab.freedesktop.org/drm/msm into drm-next
c904ffa3b82b ARM: dts: omap4-kc1: fix twl6030 power node
2155689ca359 ARM: dts: am335x-bone-common: Increase MDIO reset deassert delay to 50ms
8dc422e35be3 ARM: dts: turris-omnia: Add global LED brightness change interrupt
607ccd1474a1 ARM: dts: marvell: kirkwood: Fix at24 EEPROM node name
346a3de67692 Merge tag 'qcom-drivers-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers
ba19144661e0 arm64: dts: ti: k3-am62: use opp_efuse_table for opp-table syscon
598a4d98663f Merge tag 'memory-controller-drv-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers
17e8e3195ac5 dt-bindings: watchdog: Document Qualcomm QCS615 watchdog
11e178dc255e arm64: dts: mediatek: mt8183-kukui: Drop bogus fixed regulators
f77f82632596 arm64: dts: mediatek: mt8183-kukui-jacuzzi: Add supplies for fixed regulators
24fc1ae800ba arm64: dts: mediatek: mt8183-kukui-jacuzzi: Fix DP bridge supply names
f5b0e5328756 arm64: dts: mediatek: mt6358: fix dtbs_check error
d5140dfa5ec4 arm64: dts: mediatek: mt8186-corsola: Fix IT6505 reset line polarity
d9e000034473 dt-bindings: net: add bindings for NETC blocks control
9fe0d2d4fd4b dt-bindings: net: add i.MX95 ENETC support
826299f01c00 dt-bindings: net: add compatible string for i.MX95 EMDIO
d1dd8567ae0f arm64: dts: freescale: imx8mp-verdin: Fix SD regulator startup delay
d490130f1b5b arm64: dts: freescale: imx8mm-verdin: Fix SD regulator startup delay
9e74cfa8aed7 arm64: dts: imx8mp-verdin: add single-master property to all i2c nodes
e311a676d575 arm64: dts: imx8mm-verdin: add single-master property to all i2c nodes
7ca54a28453d arm64: dts: imx95: Add missing vendor string to SCMI property
1e0645252385 arm64: dts: imx8mp-navqp: Add HDMI support
f69334422236 arm64: dts: imx8qm-ss-hsio: fix PCI and SATA clock indices
52db967c6836 arm64: dts: imx8qm-ss-hsio: fix interrupt-map indent under pci* nodes
4ad8c25409b5 arm64: dts: imx8qxp-mek: replace hardcode 0 with IMX_LPCG_CLK_0
9c1b6d13e36e arm64: dts: imx8mn-tqma8mqnl-mba8mx-usbot: fix coexistence of output-low and output-high in GPIO
9b2e30519b00 arm64: dts: layerscape: remove en25s64 and only keep jedec,spi-nor compatible string
112a2f10e385 arm64: dts: imx8mp-kontron-dl: change touchscreen power-supply to AVDD28-supply
0f08165e91f7 arm64: dts: imx8mp: Add Boundary Device Nitrogen8MP Universal SMARC Carrier Board
64e784a46469 arm64: dts: imx8: move samsung,burst-clock-frequency to imx8mn and imx8mm mba8mx board file
83fb50675bc3 arm64: dts: mba8mx: remove undocumented 'data-lanes' at panel
0e24192fd5df arm64: dts: imx: Add i.MX8M Plus Gateworks GW82XX-2X support
37833e2088f6 arm64: dts: imx8ulp-evk: Add spdif sound card support
750ba00a205a arm64: dts: imx8ulp-evk: Add bt-sco sound card support
7d99d457b93d arm64: dts: imx8ulp: Add audio device nodes
f4b3c64c0244 arm64: dts: imx8qm-mek: enable dsp node for rproc usage
1caf91ab383e arm64: dts: imx8qm: add node for VPU dsp
fbc00480351a arm64: dts: imx8qm: drop dsp node from audio_subsys bus
28f0a4fda11f arm64: dts: imx8qxp-mek: add dsp rproc-related mem regions
5d166eadac0c arm64: dts: imx8-ss-audio: configure dsp node for rproc usage
e5e252f95438 Merge tag 'v6.12-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into gpio/for-next
4c2e02e65cdd ARM: dts: imx: Add devicetree for Kobo Clara 2E
6b94da0ee5dd dt-bindings: arm: fsl: add compatible strings for Kobo Clara 2E
202c40aec2b8 Backmerge v6.12-rc6 of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into drm-next
b103f56c1313 dt-bindings: cache: qcom,llcc: Document the QCS8300 LLCC
1cb298e50005 dt-bindings: cache: qcom,llcc: Document the QCS615 LLCC
d1a15a60e3dd dt-bindings: cache: qcom,llcc: document SAR2130P and SAR1130P
b5252d8ac17a dt-bindings: serial: samsung: Add samsung,exynos8895-uart compatible
150da36dbb3e dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2044 uarts
8d33fdaef0c9 dt-bindings: serial: snps,dw-apb-uart: merge duplicate compatible entry.
0221e5a00939 dt-bindings: usb: Describe TUSB1046 crosspoint switch
9ced24730a60 dt-bindings: usb: add TUSB73x0 PCIe
9f0df430d226 dt-bindings: net: snps,dwmac: Fix "snps,kbbe" type
d37a18c3359d dt-bindings: iio: magnetometer: document the Allegro MicroSystems ALS31300 3-D Linear Hall Effect Sensor
89d25ea2ca64 dt-bindings: vendor-prefixes: Add Allegro MicroSystems, Inc
67d497917b1c dt-bindings: iio: light: veml6075: document vishay,rset-ohms
42fa3119d0f6 dt-bindings: iio: dac: ad5791: Add required voltage supplies
17ed50b8e5b2 dt-bindings: iio: dac: ad5791: Add optional reset, clr and ldac gpios
b8c3bcba7006 dt-bindings: PCI: qcom,pcie-x1e80100: Add 'global' interrupt
3f1c84e16a83 dt-bindings: PCI: qcom: Move OPP table to qcom,pcie-common.yaml
8be0ac5e2035 dt-bindings: PCI: qcom: Document the IPQ9574 PCIe controller
b6b07e2734ce arm64: dts: renesas: rzg3s-smarc-som: Enable RTC
77fef08ac39f arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB
4279f7bfeca0 arm64: dts: renesas: r9a08g045: Add RTC node
c662c8fd62d0 arm64: dts: renesas: r9a08g045: Add VBATTB node
3b4ff03ddadd Merge tag 'renesas-r9a08g045-dt-binding-defs-tag3' into renesas-dts-for-v6.13
b574ea7102f4 arm64: dts: renesas: white-hawk-cpu-common: Add pin control for DSI-eDP IRQ
b1b4b25b826b ARM: dts: renesas: r7s72100: Add DMA support to MMCIF
d9254ef42935 ARM: dts: renesas: r7s72100: Add DMAC node
24f9da7ff499 arm64: dts: renesas: hihope: Drop #sound-dai-cells
a1c74be440b4 dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
ddbfd89adc2b arm64: dts: ti: k3-am62p5-sk: add 1.4ghz opp entry
ea0e401633cb arm64: dts: ti: k3-am62p: add opp frequencies
ff729dee84ac arm64: dts: ti: k3-am62a7-sk: add 1.4ghz opp entry
bb3fd30ebdc2 arm64: dts: ti: k3-am62a: add opp frequencies
4e946fcedb0a arm64: dts: ti: k3-am62-verdin: Add Ivy carrier board
3c9f7ab0f160 arm64: dts: ti: k3-am62-verdin: add label to som adc node
331663639dd4 dt-bindings: arm: ti: Add verdin am62 ivy board
a5ed55d5f102 dt-bindings: PCI: qcom,pcie-sm8550: Add SAR2130P compatible
3c02cd885435 arm64: allwinner: a100: Add MMC related nodes
5d066483a0d1 arm64: dts: allwinner: a100: add usb related nodes
036fcc436587 dt-bindings: usb: sunxi-musb: Add A100 compatible string
146dcab6bf5d dt-bindings: usb: Add A100 compatible string
9c1f15141146 dt-bindings: phy: sun50i-a64: add a100 compatible
75547bc28cb8 arm64: dts: allwinner: a100: add watchdog node
d54b845fdacb arm64: dts: allwinner: A100: Add PMU mode
aca70dbb9197 riscv: dts: sophgo: Add emmc support for Huashan Pi
42878e08ab97 riscv: dts: sophgo: Add sdio configuration for Huashan Pi
eb07cad87c26 riscv: dts: sophgo: fix pinctrl base-address
8e37388c023b ARM: dts: imx6sll: Improve gpc description
b8bd0f9f429f dt-bindings: power: fsl,imx-gpc: Document fsl,imx6sll-gpc
f4ecbd3601e6 ARM: dts: imx6sl: Pass tempmon #thermal-sensor-cells
ba6c85227642 ARM: dts: imx6sx: Fix tempmon description
331a16df15a3 ARM: dts: imx6sll: Remove regulator-3p0 unit address
47c8e9173f81 dt-bindings: soc: imx: fsl,imx-anatop: Add additional regulators
3ae26b145a89 dt-bindings: soc: imx: fsl,imx-anatop: Fix the i.MX7 irq number
255ba77d9c2d ARM: dts: imx6sll: Fix the last SPDIF clock name
c42453e6426e dt-bindings: mfd: aspeed: Support for AST2700
2a73067c2a22 dt-bindings: mfd: qcom,spmi-pmic: Document PMICs added in SM8750
5397edc4d601 dt-bindings: iio: dac: adi-axi-dac: add ad3552r axi variant
9caf7607e387 dt-bindings: iio: dac: ad3552r: add iio backend support
763816eac739 dt-bindings: iio: imu: bmi270: Add Bosch BMI260
713fa6540db4 dt-bindings: iio: light: veml6030: add veml3235
dba57ae0cfce ASoC: dt-bindings: Add schema for "awinic,aw88081"
a19f983c0d5c arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Add cma heap for libcamera softisp support
28471dd8f4a6 arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: Add cma heap for libcamera softisp support
b9629dab901b arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: Drop redundant clock-lanes from camera@1a
1ddecd567632 arm64: dts: qcom: sc8280xp-x13s: Drop redundant clock-lanes from camera@10
be774e8d2ab8 arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Convert mezzanine riser to dtso
3f2133c08066 ARM: dts: imx7ulp: Remove incorrect mmc fallback compatible
7506bc6cb797 ARM: dts: imx6sl: Remove incorrect mmc fallback compatible
28933a53f55c ARM: dts: imx6sx: Remove incorrect mmc fallback compatible
1f840a106c30 ARM: dts: imx6sl/sll: Add the "fsl,imx6dl-gpt" fallback
a894fbc7d9c2 dt-bindings: arm: fsl: Add Boundary Device Nitrogen8MP Universal SMARC Carrier Board
fba51fea7ab6 dt-bindings: arm: fsl: Add Gateworks GW82XX-2x dev kit
6e1ac4df7d84 dt-bindings: dsp: fsl,dsp: fix power domain count
3fb0f7f167d1 ARM: dts: imx6ul: Drop duplicate space in iomux node groups
db27e15bb568 ARM: dts: imx6sx: Align pin config nodes with bindings
abb4de37ca85 ARM: dts: imx6sl: imx6sll: Align pin config nodes with bindings
36f077eedcaf ARM: dts: imx6qp: Align pin config nodes with bindings
39f669d0e202 ARM: dts: imx6qdl: Align pin config nodes with bindings
98bf72bdd507 ARM: dts: imx6q: Align pin config nodes with bindings
cbdbce56bc99 ARM: dts: imx6dl: Align pin config nodes with bindings
1b47588d2862 ARM: dts: imx53: Align pin config nodes with bindings
d6f94f6b81c9 ARM: dts: imx51: Align pin config nodes with bindings
96f9d558ff37 ARM: dts: imx50: Align pin config nodes with bindings
028df26bebec ARM: dts: imx35: Align pin config nodes with bindings
3beb7b7a5c8e arm64: dts: imx8mm-venice-gw73xx: remove compatible in overlay file
52d3e69f3742 arm64: dts: imx93: Add LPSPI alias
8299fb97f122 arm64: dts: imx8ulp: Add LPSPI alias
b7d284ff717f arm64: dts: imx8dxl: Add LPSPI alias
8beff2148426 arm64: dts: imx8qm: Add LPSPI alias
512aedaf436b arm64: dts: imx8qxp: Add LPSPI alias
6ef56051d213 ARM: dts: imx6qdl: convert fsl,tx-d-cal to correct value
ec366f90d9bb arm64: dts: imx8qxp: change usbphy1 compatible
cea897ccd54b arm64: dts: imx8qm: change usbphy1 compatible
874df11138be arm64: dts: imx8dxl-ss-conn: change usbphy1 compatible
02bb93887167 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
561ec2dba20c dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RTCA-3 IP
5f24de097e7e dt-bindings: mfd: x-powers,axp152: Document AXP323
fdd7b26f4e12 dt-bindings: leds: pca955x: Convert text bindings to YAML
f25661476440 Merge tag 'ath-next-20241030' of git://git.kernel.org/pub/scm/linux/kernel/git/ath/ath
62e231406590 riscv: dts: starfive: add DeepComputing FML13V01 board device tree
32165b14e52d dt-bindings: riscv: starfive: add deepcomputing,fml13v01
d7219d674223 dt-bindings: vendor: add deepcomputing
6ff04cefd0f8 riscv: dts: starfive: jh7110-common: move usb0 config to board dts
dca4975af2f1 riscv: dts: starfive: jh7110-common: revised device node
08c161cb09dd dt-bindings: spi: sprd,sc9860-spi: convert to YAML
0071bdbd8c4a dt-bindings: display: panel: Add Samsung S6E88A0-AMS427AP24
ca71b2ee5303 dt-bindings: display: panel: Move flip properties to panel-common
885d588105ef dt-bindings: net: qcom,ethqos: add description for qcs8300
30c9a2f24d08 dt-bindings: net: qcom,ethqos: add description for qcs615
716fa1e7ccdf dt-bindings: net: renesas,ether: Add iommus property
3f4eb4ad0e43 dt-bindings: net: add compatible strings for lan969x targets
383b9d96b4a7 MIPS: mobileye: eyeq6h-epm6: Use eyeq6h in the board device tree
2c23682394f8 mips: bmips: bcm6358/6368: define required brcm,bmips-cbr-reg
fca10e05179a Merge remote-tracking branch 'drm-misc/drm-misc-next' into msm-next
e360d40c1957 ASoC: renesas, rsnd: Update file path
fcc8d656b01e dt-bindings: mfd: Add support for Airoha EN7581 GPIO System Controller
7f06843a8e70 dt-bindings: pwm: airoha: Add EN7581 pwm
cf0edabd92c5 dt-bindings: pinctrl: airoha: Add EN7581 pinctrl
e6aaee853312 dt-bindings: arm: airoha: Add the chip-scu node for EN7581 SoC
f0cd86a71bc4 Merge tag 'wireless-next-2024-10-25' of git://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next
797a67e6b014 ARM: dts: ti/omap: omap4-epson-embt2ws: add charger
7efc9f8883cb ARM: dts: omap36xx: declare 1GHz OPP as turbo again
fb2d1cd36043 ARM: ti/omap: omap3-gta04a5: add Bluetooth
ede8f302a975 ARM: dts: ti/omap: dra7: fix redundant clock divider definition
368aa5565758 ARM: dts: ti/omap: use standard node name for twl4030 charger
fff64bcb9e7d ARM: dts: omap: omap4-epson-embt2ws: add GPIO expander
95bd176683f3 ARM: dts: omap: omap4-epson-embt2ws: add unknown gpio outputs
c54ce42be317 ARM: dts: omap: omap4-epson-embt2ws: wire up regulators
f9a228320349 ARM: dts: omap: omap4-epson-embt2ws: define GPIO regulators
7c132391322b dt-bindings: cache: qcom,llcc: Fix X1E80100 reg entries
e87d66603200 arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: Convert mezzanine riser to dtbo
0e47b353b366 arm64: dts: qcom: sm8450-hdk: model the PMU of the on-board wcn6855
0da5e2831b5f arm64: dts: qcom: sc8280xp-x13s: model the PMU of the on-board wcn6855
b144f43b00c6 arm64: dts: qcom: sc8280xp-crd: enable bluetooth
71dd0754900a arm64: dts: qcom: sc8280xp-crd: model the PMU of the on-board wcn6855
db6231faa8ef arm64: dts: qcom: qcs9100: Add support for the QCS9100 Ride and Ride Rev3 boards
6db2df13d51b dt-bindings: arm: qcom: Document qcs9100-ride and qcs9100-ride Rev3
939575bddd9e dt-bindings: arm: qcom,ids: add SoC ID for QCS9100
37f62a041104 dt-bindings: soc: qcom,aoss-qmp: Document the QCS8300 AOSS channel
2b6367dc7663 dt-bindings: soc: qcom: add qcom,qcs8300-imem compatible
921d4a5b59ca dt-bindings: firmware: qcom,scm: document SCM on QCS8300 SoCs
b056fb0da587 dt-bindings: arm: qcom: add the SoC ID for SA8255P
353c843385dd dt-bindings: soc: qcom: aoss-qmp: document support for SA8255p
eb757c1154d7 dt-bindings: firmware: qcom,scm: document support for SA8255p
023f9687db26 arm64: dts: qcom: x1e80100: Update C4/C5 residency/exit numbers
26e54f2b420b arm64: dts: qcom: x1e80100-crd: describe HID supplies
e13fc809cbc2 dt-bindings: arm-smmu: document QCS615 APPS SMMU
d883086fe6d0 arm64: dts: st: add DMA support on SPI instances of stm32mp25
293e556c3b71 arm64: dts: st: add DMA support on I2C instances of stm32mp25
a6d1ed648360 arm64: dts: st: add DMA support on U(S)ART instances of stm32mp25
b6492a99f4d4 arm64: dts: st: add RNG node on stm32mp251
789463f5f6f9 arm64: dts: ti: k3-am642-phyboard-electra-rdk: Enable trickle charger
da365b4af0fd arm64: dts: st: enable RTC on stm32mp257f-ev1 board
58372f2d5992 arm64: dts: st: add RTC on stm32mp25x
7967e3f18c68 ARM: dts: stm32: add support of WLAN/BT on stm32mp135f-dk
31603dbb73ed ARM: dts: stm32: add support of WLAN/BT on stm32mp157c-dk2
765429189582 ARM: dts: stm32: rtc, add LSCO to WLAN/BT module on stm32mp135f-dk
dff35cb83ba2 ARM: dts: stm32: rtc, add LSCO to WLAN/BT module on stm32mp157c-dk2
0c7155f0410d ARM: dts: stm32: rtc, add pin to provide LSCO on stm32mp13
b45457addbd1 ARM: dts: stm32: rtc, add pin to provide LSCO on stm32mp15
3c483aafdf06 ARM: dts: stm32: Describe M24256E write-lockable page in DH STM32MP13xx DHCOR SoM DT
139d492884d8 arm64: dts: qcom: msm8998-lenovo-miix-630: add WiFi calibration variant
cdfae05f1158 arm64: dts: qcom: msm8998-clamshell: enable resin/VolDown
64e0ef2c06b2 arm64: dts: qcom: msm8998-lenovo-miix-630: enable VolumeUp button
9f95673168b0 arm64: dts: qcom: msm8998-lenovo-miix-630: enable aDSP and SLPI
a5bac521fc24 arm64: dts: qcom: msm8998-lenovo-miix-630: enable touchscreen
a8515049c066 ARM: dts: stm32: Add IWDG2 EXTI interrupt mapping and mark as wakeup source
eddd3e969925 ASoC: dt-bindings: document the adau1373 Codec
470374aa96c5 dt-bindings: arm: pmu: Add Samsung Mongoose core compatible
6834ae6fe43e Merge tag 'samsung-pinctrl-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel
65f56eb13285 dt-bindings: iommu: riscv: Add bindings for RISC-V IOMMU
2a9e11d084c6 dt-bindings: cpufreq: cpufreq-qcom-hw: Add SAR2130P compatible
b194ce2eb3b8 dt-bindings: cpufreq: add virtual cpufreq device
8bc748b3aced dt-bindings: connector: Add properties to define time values
605f85ff9e6f dt-bindings: iio: adc: adi,ad7606: document AD760{7,8,9} parts
6a89ae47b092 dt-bindings: iio: light: opt3001: add compatible for opt3002
70299596e737 dt-bindings: nfc: nxp,nci: Document PN553 compatible
fdd8e743e28d dt-bindings: watchdog: convert zii,rave-sp-wdt.txt to yaml format
01f9cc33c847 dt-bindings: input: convert zii,rave-sp-pwrbutton.txt to yaml
b854e49c0d99 arm64: dts: ti: k3-am64-phycore-som: Add M4F remoteproc nodes
39fc4e8d0c96 arm64: dts: ti: k3-am62-phycore-som: Add M4F remoteproc nodes
98100a4d2f27 arm64: dts: ti: minor whitespace cleanup
b7a07b589550 arm64: dts: ti: k3-am62x-phyboard-lyra: Fix indentation in audio-card
ecf01fc92c51 arm64: dts: ti: k3-am642-phyboard-electra-rdk: Fix bus-width property in MMC nodes
b8c71de468cb arm64: dts: ti: k3-am64-phycore-som: Fix bus-width property in MMC nodes
2d697a33eea7 arm64: dts: ti: k3-am642-evm: Add overlay for PCIe0 EP mode
b2eb2eb13dff arm64: dts: ti: k3-j7200-evm: Add overlay for PCIE1 Endpoint Mode
012f0b98adb5 arm64: dts: ti: k3-am62-main: Update otap/itap values
0f5c0fbac643 arm64: dts: ti: k3-am625-beagleplay: Enable MikroBUS PWM
4a83eccaf4bb arm64: dts: ti: k3-am62-verdin: Fix SD regulator startup delay
2b93c69971f5 arm64: dts: ti: k3-am62-verdin: Fix SoM ADC compatible
7b41e5063d24 arm64: dts: ti: k3-am625-verdin: add TPM device
d5934e5672b3 arm64: dts: ti: k3-j721s2: Fix clock IDs for MCSPI instances
5259ea65769a arm64: dts: ti: k3-j721e: Fix clock IDs for MCSPI instances
1aa6fec1bf7f arm64: dts: ti: k3-j7200: Fix clock ids for MCSPI instances
05dadccc1d6e arm64: dts: ti: k3-j7200: Fix register map for main domain pmx
b5e4fcb6a6a4 arm64: dts: ti: k3-j7200-evm*: Add bootph-* properties
23d8a29be7cf arm64: dts: ti: k3-j721e-sk*: Add bootph-* properties
8939387ec242 arm64: dts: ti: k3-j721e-evm*: Add bootph-* properties
1ebacb4afd7d arm64: dts: ti: k3-am68-sk*: Add bootph-* properties
59290b7acdb1 arm64: dts: ti: k3-j721s2-evm*: Add bootph-* properties
96b67eddd9d8 arm64: dts: ti: k3-j784s4-j742s2-evm-common: Remove parent nodes bootph-*
6fc66a1cbbf9 arm64: dts: ti: k3-j7200: Add bootph-* properties
4e700078c990 arm64: dts: ti: k3-j721e: Add bootph-* properties
24856781f185 arm64: dts: ti: k3-j721s2: Add bootph-* properties
5ea5f859d657 arm64: dts: ti: k3-j784s4: Add bootph-* properties
7fe1e46095c4 arm64: dts: ti: k3-j784s4-j742s2-mcu-wakeup: Remove parent nodes bootph-*
1853b9579d48 arm64: dts: ti: k3-j784s4-j742s2-mcu-wakeup: Move bootph from mcu_timer1 to mcu_timer0
114be30a95ab dt-bindings: firmware: arm,scmi: Introduce more transport properties
4a611cd4cf42 dt-bindings: sram: Document reg-io-width property
c548ac9c74e2 dt-bindings: pinctrl: convert pinctrl-mcp23s08.txt to yaml format
cf6826771639 dt-bindings: crypto: qcom-qce: document the SA8775P crypto engine
2b8c1030e8c0 dt-bindings: rng: add support for Airoha EN7581 TRNG
58a715d54f20 dt-bindings: rng: add st,stm32mp25-rng support
6670c8049523 dt-bindings: rng: Add Marvell Armada RNG support
15cd3ba66a63 dt-bindings: soc: rockchip: add rk3588 mipi dcphy syscon
43d7d295f50a dt-bindings: pinctrl: samsung: Add compatible for exynos9810-wakeup-eint
25dc3ef6afee dt-bindings: pinctrl: samsung: Add compatible for Exynos9810 SoC
0b4611bbe9bb dt-bindings: arm: samsung: Document Exynos9810 and starlte board binding
3478405a22cc dt-bindings: soc: samsung: exynos-pmu: Add exynos9810 compatible
5391365435bc dt-bindings: arm: cpus: Add Samsung Mongoose M3
5f722ff65658 dt-bindings: hwinfo: samsung,exynos-chipid: Add Samsung exynos9810 compatible
bb0089d8c302 dt-bindings: display/msm/gmu: Add Adreno 663 GMU
39e708dc0fb1 arm64: dts: exynos8895: Add spi_0/1 nodes
0cf148b180b1 arm64: dts: exynos8895: Add Multi Core Timer (MCT) node
f799b809d6c7 arm64: dts: exynos8895: Add clock management unit nodes
b4fa09099517 dt-bindings: timer: exynos4210-mct: Add samsung,exynos8895-mct compatible
6325725ea9a3 Merge branch 'for-v6.13/clk-dt-bindings' into next/dt64
8da2e616237d Merge branch 'for-v6.13/clk-dt-bindings' into next/clk
eeba38da05de dt-bindings: clock: samsung: Add Exynos8895 SoC
87e26426dfdb ARM: dts: sunxi: add support for RerVision A33-Vstar board
55be2d52b761 dt-bindings: arm: sunxi: document RerVision A33-Vstar board
b53ca4b51fbb arm64: dts: allwinner: Add disable-wp for boards with micro SD card
9f4b1c04a628 ARM: dts: cubieboard4: Fix DCDC5 regulator constraints
556bf94aa7b1 arm64: dts: allwinner: h313/h616/h618/h700: Enable audio codec for all supported boards
4da8ded9f0cc arm64: dts: allwinner: h616: Add audio codec node
f419b2caa850 arm64: dts: apple: Add A11 devices
bcf1afc654cc arm64: dts: apple: Add A10X devices
84201093d52b arm64: dts: apple: Add A10 devices
513b4af7b994 arm64: dts: apple: Add A9X devices
1e48996186f2 arm64: dts: apple: Add A9 devices
718683c792c8 arm64: dts: apple: Add A8X devices
2ba5d138f134 arm64: dts: apple: Add A8 devices
0d01c7eaa9e2 arm64: dts: apple: Add A7 devices
f2291bedf412 dt-bindings: arm: apple: Add A11 devices
6777f8463609 dt-bindings: arm: apple: Add A10X devices
b4ff47625083 dt-bindings: arm: apple: Add A10 devices
ce790688aa46 dt-bindings: arm: apple: Add A9X devices
0472420f025e dt-bindings: arm: apple: Add A9 devices
340a25ae66bc dt-bindings: arm: apple: Add A8X devices
25411031e69f dt-bindings: arm: apple: Add A8 devices
bc22115c3571 dt-bindings: arm: apple: Add A7 devices
6018a7f4ceca dt-bindings: pinctrl: apple,pinctrl: Add A7-A11 compatibles
176a45e1572d dt-bindings: watchdog: apple,wdt: Add A7-A11 compatibles
79f0d9d12ef3 dt-bindings: arm: cpus: Add Apple A7-A11 CPU cores
bfaae9b422dd dt-bindings: mmc: Add sdhci compatible for QCS615
34d505c80e75 dt-bindings: mmc: sdhci-msm: Add SAR2130P compatible
d6f153d7cb45 dt-bindings: mmc: mtk-sd: Add mt7988 SoC
22f0ba9af4bb dt-bindings: mmc: mtk-sd: Add support for MT8196
4c1518fa641b dt-bindings: pwm: adi,axi-pwmgen: Increase #pwm-cells to 3
a1e6619cb6c6 dt-bindings: pwm: amlogic: Document C3 PWM
4e4e741cb376 arm64: dts: mt8183: Damu: add i2c2's i2c-scl-internal-delay-ns
030f50a89855 arm64: dts: mt8183: cozmo: add i2c2's i2c-scl-internal-delay-ns
94427cb3877f arm64: dts: mt8183: burnet: add i2c2's i2c-scl-internal-delay-ns
eef73802f2c2 arm64: dts: mt8183: fennel: add i2c2's i2c-scl-internal-delay-ns
abff5effb653 dt-bindings: clock: r9a08g045-cpg: Add power domain ID for RTC
cde5a517b243 dt-bindings: pinctrl: qcom,sm8650-lpass-lpi-pinctrl: Add SM8750
b8ddbab4b1d5 arm64: dts: renesas: r9a09g057: Add OPP table
60d1484c7f80 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
ac3aa417c4d3 arm64: dts: rockchip: Add rk3588-orangepi-5b device tree
d041fe91c4a5 dt-bindings: arm: rockchip: Add Orange Pi 5b enum to Orange Pi 5 entry
911221b5def9 arm64: dts: rockchip: refactor common Orange Pi 5 board
621631b891ca arm64: dts: rockchip: Remove 'enable-active-low' from two boards
4e8ec18efa34 arm64: dts: rockchip: add HDMI support to rk3588-jaguar
77c83d44d09e arm64: dts: rockchip: add HDMI support to rk3588-tiger-haikou
adcae16b7116 arm64: dts: rockchip: add HDMI pinctrl to rk3588-tiger SoM
3e97951ad0a6 dt-bindings: riscv: Add pointer masking ISA extensions
b41aa6a575a1 ASoC: add CS42L84 codec driver
7192e70b9e3a arm64: tegra: smaug: Declare cros-ec extcon
8934d4046bdc arm64: tegra: Add SDMMC sdr104-offsets for Tegra X1
ea318ab24a38 arm64: dts: nvidia: tegra210-smaug: Add TMP451 temperature sensor node
898f0df845bd arm64: dts: nvidia: tegra210-smaug: Add touchscreen node
befe34729281 arm64: tegra: p2180: Add mandatory compatible for WiFi node
de0d275642cc arm64: dts: qcom: qcs6490-rb3gen2: Add PCIe nodes
144450a673fc ASoC: dt-bindings: Add CS42L84 codec
24c8f63fb336 arm64: dts: qcom: x1e80100-dell-xps13-9345: fix nvme regulator boot glitch
5a2877e8f17f arm64: dts: qcom: x1e80100-dell-xps13-9345: route edp-panel enable gpio
5fe874b7e3ee ARM: dts: qcom: ipq4019: use nvmem-layout
665e55a6885b dt-bindings: iommu: arm,smmu: Add Qualcomm SAR2130P compatible
f7103f8dbe23 ASoC: dt-bindings: allwinner: add H616 sun4i audio codec binding
85cdd8af34ad dt-bindings: perf: fsl-imx-ddr: Add i.MX91 compatible
f50caff43d6a arm64: dts: rockchip: reorder mmc aliases for NanoPi R3S
2775a2d6f7b4 arm64: dts: rockchip: enable eMMC HS200 mode for NanoPi R3S
1df9ef3a764c arm64: dts: rockchip: sort props in pmu_io_domains node for NanoPi R3S
092d7aa6b26a arm64: dts: rockchip: replace deprecated snps,reset props for NanoPi R3S
451daf1e7781 arm64: dts: rockchip: fix model name for FriendlyElec NanoPi R3S
5500fa4c0d21 arm64: dts: rockchip: Enable HDMI0 on rock-5a
47f18a03a79a arm64: dts: rockchip: Enable HDMI0 on rk3588-nanopc-t6
309958c5385c arm64: dts: rockchip: pwm-leds for Orange Pi 5
7341cdb87808 arm64: dts: rockchip: reorder audio/hdmi nodes in Orange Pi 5
fed07cae4bda dt-bindings: clock: Add i.MX91 clock support
64f251acccf2 dt-bindings: clock: imx93: Drop IMX93_CLK_END macro definition
c3a0967a0ade dt-bindings: clock: qcom: gcc-ipq9574: remove q6 bring up clock macros
e5866abf2fc0 dt-bindings: clock: qcom: gcc-ipq5332: remove q6 bring up clock macros
6013f4f7ebe6 arm64: dts: qcom: Use 'ufshc' as the node name for UFS controller nodes
7e734080860e dt-bindings: memory: fsl: Add compatible string nxp,imx9-memory-controller
1aa0676d2d4b dt-bindings: pinctrl: fsl,imx6ul-pinctrl: Convert i.MX35/5x/6 to YAML
1ee7a76a6c50 dt-bindings: soc: qcom,aoss-qmp: Add SAR2130P compatible
940defd6ddc2 dt-bindings: firmware: qcom,scm: Add SAR2130P compatible
af94817fdc9b dt-bindings: arm: qcom,ids: add SoC ID for SAR2130P and SAR1130P
4bbc500f1da4 arm64: dts: qcom: qcm6490-idp: Add UFS nodes
3434afeaf4be dt-bindings: soc: qcom: aoss-qmp: Add SM8750
cb1aae17d00a dt-bindings: arm: qcom,ids: add SoC ID for QCS615
f46702301869 arm64: dts: qcom: change labels to lower-case
9cc41c2a3917 arm64: dts: qcom: sdm: change labels to lower-case
7f90ace59631 arm64: dts: qcom: sm: change labels to lower-case
424546162d92 arm64: dts: qcom: sm8650: change labels to lower-case
5187737d5a40 arm64: dts: qcom: sm8550: change labels to lower-case
fd28693b7ec7 arm64: dts: qcom: sm8450: change labels to lower-case
a83c84ed92db arm64: dts: qcom: sm8350: change labels to lower-case
e9bdee2539b8 arm64: dts: qcom: sm8250: change labels to lower-case
f98c362c10a4 arm64: dts: qcom: sm8150: change labels to lower-case
bd4eb7f2c86e arm64: dts: qcom: sm6350: change labels to lower-case
136ffc3dabc1 arm64: dts: qcom: sm6115: change labels to lower-case
78ec42322ffe arm64: dts: qcom: sc: change labels to lower-case
7bae058d8dfe ARM: dts: qcom: change labels to lower-case
d0bf57f2868c arm64: dts: qcom: sc8280xp: change labels to lower-case
a4a1c355ae9d arm64: dts: qcom: sc7180: change labels to lower-case
0d8dff827b33 arm64: dts: qcom: msm8992-libra: drop unused regulators labels
12d665984756 arm64: dts: qcom: msm: change labels to lower-case
c3f0be5bbb93 arm64: dts: qcom: ipq: change labels to lower-case
3f59ee4054f6 arm64: dts: qcom: sm8450: Add 'global' interrupt to the PCIe RC node
009d588e0380 arm64: dts: qcom: sa8775p: Add 'linux,pci-domain' to PCIe EP controller nodes
e9d262a12a51 ARM: dts: qcom: sdx65: Add 'linux,pci-domain' to PCIe EP controller node
d510764cf6fe ARM: dts: qcom: sdx55: Add 'linux,pci-domain' to PCIe EP controller node
a5ff6758bf1c arm64: dts: qcom: sa8775p: Add TCSR halt register space
b1d366cdfe38 arm64: dts: qcom: sa8775p-ride: add WiFi/BT nodes
45ac1e08b402 arm64: dts: qcom: sa8775p: add QCrypto nodes
066c8b7de678 Merge branch '20241011-sa8775p-mm-v4-resend-patches-v5-0-4a9f17dc683a@quicinc.com' into arm64-for-6.13
19bf5adbc0ac Merge branch '20241011-sa8775p-mm-v4-resend-patches-v5-0-4a9f17dc683a@quicinc.com' into clk-for-6.13
448c23dea476 dt-bindings: clock: qcom: Add SA8775P display clock controllers
62a4544b801a dt-bindings: clock: qcom: Add SA8775P camera clock controller
655ad47c87f6 dt-bindings: clock: qcom: Add SA8775P video clock controller
3164172f31e5 regulator: init_data handling update
b4501c58ccd3 arm64: dts: qcom: sm7325: Add device-tree for Nothing Phone 1
6690dd9829c2 dt-bindings: arm: qcom: Add SM7325 Nothing Phone 1
a0e6a2b73511 dt-bindings: vendor-prefixes: Add Nothing Technology Limited
166a45c90a81 arm64: dts: qcom: Add SM7325 device tree
c0f8f7275e0e dt-bindings: arm: cpus: Add qcom kryo670 compatible
5a5f297992a8 arm64: dts: qcom: sa8775p: Add GPI configuration
48e01bb5863b regulator: dt-bindings: qcom,qca6390-pmu: add more properties for wcn6855
fc22539a553f regulator: dt-bindings: lltc,ltc3676: convert to YAML
9fd1b7244de8 dt-bindings: clock: nxp,imx95-blk-ctl: Add compatible string for i.MX95 HSIO BLK CTRL
2d6147baff0c dt-bindings: mmc: Document support for partition table in mmc-card
6966ae169e9c arm64: dts: rockchip: analog audio on Orange Pi 5
54d1879aeb79 arm64: dts: rockchip: Add dtsi file for RK3399S SoC variant
d31105e3a752 arm64: dts: rockchip: Convert dts files used as parents to dtsi files
a198185b9b55 arm64: dts: rockchip: fix the pcie refclock oscillator on Rock 5 ITX
cf9235a8b9cf arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board
cefc739ed7fd dt-bindings: arm: rockchip: Add FriendlyARM NanoPi R3S
22c62b410a76 arm64: dts: rockchip: Enable HDMI0 on Orange Pi 5
309d3c431657 arm64: dts: rockchip: add and enable gpu node for Radxa ROCK 5A
08d6b7cea0b0 arm64: dts: rockchip: Enable HDMI0 on orangepi-5-plus
6c98a7bb55d5 arm64: dts: rockchip: Enable HDMI0 on rk3588-evb1
7c442cba59d1 arm64: dts: rockchip: Enable HDMI0 on rock-5b
a839348380c2 arm64: dts: rockchip: Add HDMI0 node to rk3588
5bfa747aa6cc arm64: dts: rockchip: Add Radxa e20c board
6f220d3a1243 arm64: dts: rockchip: Add base DT for rk3528 SoC
02c7df878deb dt-bindings: arm: rockchip: Add Radxa E20C board
844b572cc629 arm64: dts: rockchip: Add rk3576-armsom-sige5 board
e472bbb96d8d arm64: dts: rockchip: Add rk3576 SoC base DT
39f0871081fe dt-bindings: arm: rockchip: Add ArmSoM Sige 5
83489bf1ecfb arm64: dts: rockchip: Drop rockchip prefix of s-p-c PMIC prop from rk356x
39eaee8ff5dd arm64: dts: rockchip: Drop rockchip prefix of s-p-c PMIC prop from rk3399
6da1af61e5d0 arm64: dts: rockchip: Drop rockchip prefix of s-p-c PMIC prop from rk3368
6638fa4733b1 arm64: dts: rockchip: Drop rockchip prefix of s-p-c PMIC prop from rk3328
320af665b061 arm64: dts: rockchip: Drop rockchip prefix of s-p-c PMIC prop from px30
94c457e83260 ASoC: dt-bindings: qcom: Add SM8750 LPASS macro codecs
3e3c77d7ec1a dt-bindings: pinctrl : qcom: document SAR2130P TLMM
4fa57881d207 dt-bindings: pinctrl: describe qcs8300-tlmm
db77b8421e31 ASoC: dt-bindings: everest,es8328: Document audio graph port
db78cbd4db87 dt-bindings: power: Add binding for MediaTek MT6735 power controller
12a5b0df8288 dt-bindings: power: rpmpd: Add SAR2130P compatible
155d58a9a5ea dt-bindings: interconnect: qcom-bwmon: Document QCS8300 bwmon compatibles
2d1656d763ba dt-bindings: interconnect: qcom: document SAR2130P NoC
fe75fe7f8010 dt-bindings: arm: mediatek: mmsys: Add OF graph support for board path
143cdfb176c5 dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in QCS615 SoC
c7dbf07a745f dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in QCS8300 SoC
cc849602f015 arm64: dts: imx8qxp-mek: add cm4 and related nodes
5c260f3d0e7d arm64: dts: imx8qxp-mek: add usbotg1 and related node
a3454d3d7fa5 arm64: dts: imx8qxp-mek: add flexcan1 and flexcan2
02a69f98c668 arm64: dts: imx8qxp-mek: enable jpeg encode and decode
17e2c887c738 arm64: dts: imx8qxp-mek: add esai, cs42888 and related node
adda0b1a447a arm64: dts: imx8qxp-mek: add bluetooth audio codec
bb041d03e14f dt-bindings: at24: add ST M24256E Additional Write lockable page support
c52e0b44f52d ARM: dts: imx6sll: fix anatop thermal dtbs_check warnings
0ad8c197e84e arm64: dts: imx8m*-venice-gw75xx: add Accelerometer device
f3e374f020bd arm64: dts: imx8qm-mek: Add PCIe and SATA
ae0cdc268451 arm64: dts: imx8qxp-mek: Add PCIe support
0dfe113f6196 arm64: dts: imx8dxl-evk: Add PCIe support
1f04693e298f arm64: dts: imx8-ss-hsio: Add PCIe and SATA support
0b1f674ef893 arm64: dts: colibri-imx8x: Fix typo "rewritting"
ed688466bd31 arm64: dts: imx93-9x9-qsb: Add PDM microphone sound card support
5581f5e11eae arm64: dts: imx93-9x9-qsb: add bt-sco sound card support
dbdd22ddfac2 arm64: dts: imx93-9x9-qsb: Enable sound-wm8962 sound card
d3e21971c3b5 ARM: dts: imx6dl: Add support for i.MX6DL DHCOM SoM on PDK2 carrier board
b11b5832eb54 dt-bindings: arm: fsl: Document i.MX6DL DHCOM SoM on PDK2 carrier board
3036f98efd20 riscv: sophgo: dts: add power key for pioneer box
382306fd81b9 ARM: dts: imx6qdl-dhcom-pdk2: Fill in missing panel power-supply
df4f89b32581 ARM: dts: imx6qdl-dhcom-pdk2: Drop incorrect size-cells in GPIO keys
9b1b00bff3b1 ARM: dts: imx6qdl-dhcom-som: Drop bogus regulator-suspend-mem-microvolt
177785b48e6b arm64: dts: imx95-19x19-evk: add lpi2c[5,6] and sub-nodes
6912c8892abb arm64: dts: imx95-19x19-evk: add nxp,ctrl-ids property
ff37f6cca13c arm64: dts: imx95: enable A55 cpuidle
6fba8c16af61 arm64: dts: imx95: add anamix temperature thermal zone and cooling node
51124be16359 arm64: dts: imx95: update a55 thermal trip points
4d2b2f1d0695 arm64: dts: imx95: add bbm/misc/syspower scmi nodes
fbfc377ba7a8 arm64: dts: imx95: set max-rx-timeout-ms
0c5a7fb42610 ARM: dts: imx7-colibri: Update audio card name
06df2ef8a492 ARM: dts: imx6qdl-colibri: Update audio card name
06a6941c0f78 ARM: dts: imx6qdl-apalis: Update audio card name
2b4ed3fd4960 arm64: dts: imx8mm-kontron: Add DL (Display-Line) overlay with LVDS support
09d68d473bf6 arm64: dts: imx8mm-kontron: Add support for display bridges on BL i.MX8MM
c7bd4069275a riscv: dts: sophgo: Add SARADC description for Sophgo CV1800B
f197a8728a5f riscv: dts: sophgo: Add LicheeRV Nano board device tree
b4f7d900d99a riscv: dts: sophgo: Add initial SG2002 SoC device tree
05309c2c85c7 Realtek SPI-NAND controller
734f739458e7 dt-bindings: phy: sparx5: document lan969x
92a719586c26 dt-bindings: phy: bcm-ns-usb2-phy: drop deprecated variant
85d7821330e4 dt-bindings: iio: adc: add ad7779 doc
219811555bd9 dt-bindings: iio: adc: ad7606: Add iio backend bindings
746f361d888c dt-bindings: iio: adc: ad7606: Remove spi-cpha from required
7bb5b0ef1349 dt-bindings: iio: pressure: bmp085: Add interrupts for BMP3xx and BMP5xx devices
0900965dffb4 dt-bindings: iio: imu: smi240: add Bosch smi240
50057515bdfa dt-bindings: phy: Add QMP UFS PHY compatible for QCS8300
e438761375e2 dt-bindings: phy: qcom: snps-eusb2: Add SAR2130P compatible
84892869e473 dt-bindings: dma: sifive pdma: Add PIC64GX to compatibles
eb53a9f1aad0 dt-bindings: dma: stm32-dma3: prevent additional transfers
db5d78da359b dt-bindings: dma: stm32-dma3: prevent packing/unpacking mode
01a6a247a537 dt-bindings: dma: qcom,gpi: Add SAR2130P compatible
d3c8498b6a47 dt-bindings: soc: rockchip: add rk3576 usb2phy syscon
3c7b4436a3ef dt-bindings: soc: rockchip: add rk3576 vo1-grf syscon
716b379a0e4e arm64: dts: mediatek: mt8186-corsola: Fix GPU supply coupling max-spread
a1bdc8d588cf arm64: dts: mediatek: mt8195-cherry: Use correct audio codec DAI
7b256ed28e8b arm64: dts: mediatek: mt8188: Fix USB3 PHY port default status
e2809c3e4393 arm64: dts: mediatek: mt8173-elm-hana: Add vdd-supply to second source trackpad
a93b20e4e56c arm64: dts: mediatek: mt8186-corsola-voltorb: Merge speaker codec nodes
c5a57299769e dt-bindings: soc: mediatek: Add DVFSRC bindings for MT8183 and MT8195
a18fd2bcdfce arm64: dts: mediatek: mt8390-genio-700-evk: Enable ethernet
d9d3b66f2926 arm64: dts: mediatek: mt8188: Add ethernet node
6c459245f516 arm64: tegra: Create SKU8 AGX Orin board file
0e227df92387 dt-bindings: arm: Tegra234 Industrial Module
6e567b53df79 dt-bindings: display: bridge: sil,sii9022: Add bus-width
31a6dad2157f dt-bindings: display: bridge: tc358768: switch to bus-width
e52b8f328e65 dt-bindings: display: mediatek: Add OF graph support for board path
a5b8bc18db9d spi: dt-bindings: samsung: Add a compatible for samsung,exynos8895-spi
fcb56ba369e5 dt-bindings: spi: Add realtek,rtl9301-snand
3b3e464afa21 ARM: dts: Reconfigure the MC2 eMMC interface
a9ef1eb7ced8 ARM: dts: ux500: Add touchkeys to Codinas
ea8b05f87b2e dt-bindings: display/msm: Document the DPU for SA8775P
dd02bc215d76 dt-bindings: display/msm: Document MDSS on SA8775P
37d89b0da653 dt-bindings: display/msm: merge SM8550 DPU into SC7280
7901f24ee5fd dt-bindings: display/msm: merge SM8450 DPU into SC7280
ecfbf7ca3ff2 dt-bindings: display/msm: merge SM8350 DPU into SC7280
c23d5cbb9118 dt-bindings: display/msm: merge SM8250 DPU into SM8150
9f2c304f24e6 dt-bindings: display/msm: merge SC8280XP DPU into SC7280
7b235a5fe2b6 dt-bindings: display: msm: dp-controller: document SA8775P compatible
ec37fc180ec1 arm64: dts: layerscape: remove cooling-max-state and cooling-min-state
b2a0c2f4cdaf ARM: dts: imx6qdl-dhcom: Fix model typo for i.MX6 DHSOM
11747d9128af arm64: dts: imx8mp: add cpuidle state "cpu-pd-wait"
61c72c95b163 ARM: dts: imx6qdl-tx6: Fix 'fixed-clock' description
561a8b0f511b ARM: dts: imx6qdl-tx6: Remove 'turn-on-delay-ms'
a3da9407fea4 arm64: dts: imx8mp-evk: add PCIe Endpoint function overlay file
3ff668119d88 dt-bindings: input: mediatek,pmic-keys: Add compatible for MT6359 keys
e835158c65f4 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
6cc32685e36f Merge 6.12-rc4 into usb-next
745c9a7e2695 Merge 6.12-rc4 into tty-next
b73d66e9e6f9 Merge 6.12-rc4 into char-misc-next
97079da3b2c4 arm64: dts: ti: k3-am64: Add ti,pa-stats property
ddeec60183dd arm64: dts: ti: k3-am64-main: Add ti,pruss-pa-st node
7ab873810d8e arm64: dts: ti: k3-am654-icssg2: Add ti,pa-stats property
cac55bdc6b45 arm64: dts: ti: k3-am65-main: Add ti,pruss-pa-st node
aea8579d9280 arm64: dts: ti: k3-am62a7-phyboard-lyra-rdk: Update ethernet internal delay
a62ec33e597a arm64: dts: ti: k3-am62x-phyboard-lyra: Drop unnecessary McASP AFIFOs
b31d5fc38d27 arm64: dts: ti: k3-am64x-sk: Enable eQEP
572891e2ea8b arm64: dts: ti: k3-am64-main: Add eQEP nodes
a278dcec62b7 arm64: dts: ti: k3-am62p-main: Add eQEP nodes
5d37c1118395 arm64: dts: ti: k3-am62a-main: Add eQEP nodes
5e8af74c8ba7 arm64: dts: ti: k3-am62-main: Add eQEP nodes
17e308cc0b97 arm64: dts: ti: k3-am642-evm: Add M4F remoteproc node
8e4ca5fe2c46 arm64: dts: ti: k3-am642-sk: Add M4F remoteproc node
8fc6f5415c54 arm64: dts: ti: k3-am64: Add M4F remoteproc node
50abc117a20d arm64: dts: ti: k3-am625-sk: Add M4F remoteproc node
48e8505beee9 arm64: dts: ti: k3-am62: Add M4F remoteproc node
0309d6086f00 Revert "arm64: dts: ti: am62-phyboard-lyra: Add overlay to increase cpu frequency to 1.4 GHz"
f434f5970ce1 arm64: dts: ti: am62-phycore-som: Increase cpu frequency to 1.4 GHz
3063860fde37 Merge tag 'renesas-pinctrl-for-v6.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
ceb22b29c581 dt-bindings: pinctrl: spacemit: add support for K1 SoC
22ccb431ff16 dt-bindings: display: panel-simple: Document support for Microchip AC69T88A
2ecb2de40a66 dt-bindings: clock: ti: Convert divider.txt to json-schema
6de19d8f0ff4 dt-bindings: clock: ti: Convert interface.txt to json-schema
eb274205dc9f dt-bindings: imx-rng: Allow passing only "fsl,imx31-rnga"
6215e0dd208e dt-bindings: display: Add Sharp Memory LCD bindings
4497ec169a33 dt-bindings: gpio-mmio: Add ngpios property
0fa8dc3b05bb arm64: dts: fsl-lx2160a: add rev2 support
9405a41d0c9e arm64: dts: imx8mp: Add support for DH electronics i.MX8M Plus DHCOM PicoITX
a18f1526ea4f dt-bindings: arm: fsl: Document DH electronics i.MX8M Plus DHCOM PicoITX
a40b650b9c6c arm64: dts: imx8mp-phyboard-pollux-rdk: update gpio-line-names
efe0961bcc0d arm64: dts: imx8mp: Add DH i.MX8MP DHCOM SoM on DRC02 carrier board
4067f5c56da6 dt-bindings: arm: fsl: Document DH i.MX8MP DHCOM SoM on DRC02 carrier board
dca2a70961bd dt-bindings: reset: npcm: add clock properties
7cbf7b89f442 dt-bindings: interrupt-controller: Add support for ASPEED AST27XX INTC
4f112cd1aebd dt-bindings: clock: Add MediaTek MT6735 clock and reset bindings
5fffc63d2ac3 dt-bindings: clock: add Mobileye EyeQ6L/EyeQ6H clock indexes
72170e5b5797 Revert "dt-bindings: clock: mobileye,eyeq5-clk: add bindings"
3995b2076704 dt-bindings: wireless: wilc1000: Document WILC3000 compatible string
4f86698e3e4f dt-bindings: phy: ti,tcan104x-can: Document Microchip ATA6561
954430d0eac8 dt-bindings: phy: add NXP PTN3222 eUSB2 to USB2 redriver
bf20defea7b3 dt-bindings: phy: mxs-usb-phy: add imx8qxp compatible
f836468e82c9 dt-bindings: phy: rk3228-hdmi-phy: convert to yaml
d4931423cede spi: dt-bindings: brcm,bcm2835-aux-spi: Convert to dtschema
9e084dc5e189 dt-bindings: phy: mediatek: tphy: add a property for power-domains
b2a6f3584847 dt-bindings: phy: Add eDP PHY compatible for sa8775p
40b48a871c03 dt-bindings: phy: rockchip-usbdp: add rk3576
9cad4b12d670 dt-bindings: display: rockchip: Add schema for RK3588 HDMI TX Controller
d1b1c09ad1dc dt-bindings: phy: rockchip,inno-usb2phy: add rk3576
4decea3b16e6 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x8
cd2ee82322fa dt-bindings: phy: Add QMP UFS PHY comptible for QCS615
b3be38224e6a dt-bindings: phy: describe the Qualcomm SGMII PHY
5b6622add587 ASoC: Merge up fixes
9e8eedb5aca9 arm64: dts: imx: Add imx8mp-iota2-lumpy board
001e26a4496f dt-bindings: arm: Add i.MX8MP IOTA2 Lumpy board
9cdd6ca350d1 arm64: dts: freescale: imx8mp-verdin: Add Ivy carrier board
bcf5eb264359 arm64: dts: freescale: imx8mp-verdin: add labels to som nodes
7a813c060658 dt-bindings: arm: freescale: Add verdin imx8mp ivy board
9a4d53bcb000 dt-bindings: arm: freescale: Add verdin imx8mm ivy board
babe9c9bc350 arm64: dts: freescale: imx8mm-verdin: Add Ivy carrier board
7fe5efbbfc73 arm64: dts: freescale: imx8mm-verdin: add label to som adc node
439c1b519a0a arm64: dts: imx8mp-phyboard-pollux-rdk: add gpio-fan
d3a155830740 ARM: dts: amlogic: meson8/8b: remove invalid pinctrl reg
70dfe5f6b6d7 arm64: dts: exynos: Add initial support for Samsung Galaxy Note20 5G (c1s)
1fb33fff8bdf arm64: dts: exynos: Add initial support for the Exynos 990 SoC
54c9c140f62f dt-bindings: arm: samsung: samsung-boards: Add bindings for Exynos 990 boards
9380c4ca2ed5 dt-bindings: arm: cpus: Add Samsung Mongoose M5
875a598c29c8 dt-bindings: hwinfo: exynos-chipid: Add compatible for Exynos 990 chipid
3b8da126b7d6 dt-bindings: pinctrl: samsung: Add exynos990-wakeup-eint compatible
d05da361a158 dt-bindings: pinctrl: samsung: Add exynos990-pinctrl compatible
e6ad38f15ef1 dt-bindings: usb: add rk3576 compatible to rockchip,dwc3
172cff4b0fe5 dt-bindings: power/supply: qcom,pmi8998-charger: Drop incorrect "#interrupt-cells" from example
f608622a4c61 arm64: dts: qcom: x1e80100: Resize GIC Redistributor register region
7605dbdc0eb3 dt-bindings: reset: syscon-reboot: Add reg property
c8f503143d90 dt-bindings: power: supply: Add TI TWL603X charger
2e03d81a95fe arm64: dts: qcom: x1e80100: rename vph-pwr regulator nodes
3b3a1e7fc62e arm64: dts: mediatek: mt8188: Add eDP and DP TX nodes
e4257c23f0e0 arm64: dts: mediatek: mt8188: Add DP-INTF nodes
9a5bd28490fd arm64: dts: mediatek: mt8188: Add display nodes for vdosys1
ea1c3e87fddb arm64: dts: mediatek: mt8188: Add display nodes for vdosys0
1042ce37df70 arm64: dts: mediatek: mt8188: Add JPEG decoder and encoder nodes
422075bb8edd arm64: dts: mediatek: mt8188: Add video decoder and encoder nodes
1c67a339a469 arm64: dts: mediatek: mt8188: Add MIPI DSI nodes
13d97b6e2d15 arm64: dts: mediatek: mt8188: Add PCIe nodes
bb8ed945f116 arm64: dts: mediatek: mt8188: Assign GCE aliases
28e7afea2b36 arm64: dts: mediatek: mt8390-genio-700-evk: add keys and USB HUB
3afc934beaf9 arm64: dts: mediatek: mt8390-genio-700-evk: update regulator names
98405216faa7 arm64: dts: mediatek: mt8390-genio-700-evk: enable pcie
e1e0053cf4dd arm64: dts: mt8183: kukui: Fix the address of eeprom at i2c4
8a4fb1889563 arm64: dts: mt8183: krane: Fix the address of eeprom at i2c4
1d315aee39e4 arm64: dts: mediatek: mt7988: add efuse block
f2fbf857fb76 arm64: dts: mediatek: mt7988: add UART controllers
b210c250e291 arm64: dts: mt8183: Add encoder node
49b0cdb0196e arm64: dts: mediatek: mt8395-genio-1200-evk: Enable GPU
0d6269b04bd8 arm64: dts: mediatek: mt8188: Add socinfo nodes
0bd19540e3c1 arm64: dts: mediatek: mt8188: Add audio support
40f680fa96e6 ARM: dts: nxp: imx6ull: add dma support for uart8
026fba088d6c ARM: dts: nxp: imx6ul: add dma support for all uarts
22403370729e dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: Add support for QCS615
1b46afcf7db2 dt-bindings: phy: qcom,qusb2: Add bindings for QCS615
0e32ff673a5a ARM: dts: imx6q-lxr: Add board support
08e95b0325e7 dt-bindings: arm: fsl: Document the Comvetia LXR board
26ce50e7d8b2 dt-bindings: vendor-prefixes: Add an entry for ComVetia AG
00c30e415792 dt-bindings: display: panel: Add Samsung AMS581VF01
927f00825fba dt-bindings: mfd: mediatek: mt6397: Add ADC, CODEC and Regulators for MT6359
c4a0a08b93f2 dt-bindings: mfd: mediatek: mt6397: Add start-year property to RTC
bd1251bec9e4 dt-bindings: mfd: Convert zii,rave-sp.txt to yaml format
c658eb03f5ec dt-bindings: mfd: twl: Add charger node also for TWL603x
9c6b9e05ec76 dt-bindings: mfd: syscon: Document the non simple-mfd syscon on PolarFire SoC
90d7e910eb9f dt-bindings: mfd: Add support for the samsung,s2dos05
87d6133346a0 dt-bindings: mfd: qcom,tcsr: Add compatible for qcs615
f7d8e2a8fa7f dt-bindings: mfd: qcom,tcsr: Add compatible for QCS8300
34d22c52efc5 dt-bindings: mfd: qcom,tcsr: Document support for SA8255p
31e89d05e127 dt-bindings: mfd: mediatek: mt6397: Convert to DT schema format
9548ef611f9a arm64: dts: colibri-imx8x: Add ad7879_ts label to touchscreen controller
4801934a1531 dt-bindings: media: Add bindings for raspberrypi,rp1-cfe
0a4f497ae4ee dt-bindings: media: renesas,isp: Add binding for V4M
91d41465acda dt-bindings: media: renesas,isp: Add Gen4 family fallback
c2e69b242813 dt-bindings: i2c: maxim,max96712: Add compatible for MAX96724
1c90953be33b dt-bindings: media: renesas,csi2: Add binding for V4M
68bd2cb51490 arm64: dts: imx8mm-venice-*: add RTC aliases
5e5a7e406f64 arm64: dts: imx93-9x9-qsb: add I3C overlay file
0c66bf12b173 dt-bindings: pinctrl: samsung: Add missing constraint for Exynos8895 interrupts
13b53cabe1fa dt-bindings: pinctrl: samsung: Fix interrupt constraint for variants with fallbacks
171713151ac8 arm64: dts: imx8mp-venice-gw74xx: add M2SKT_GPIO10 gpio configuration
3234e35dd74b arm64: dts: freescale: minor whitespace cleanup
29ef9ee273ac arm64: dts: Add support for Kontron i.MX8MP SMARC module and eval carrier
966e25fa019d arm64: dts: Add support for Kontron OSM-S i.MX8MP SoM and BL carrier board
669e05743d3b dt-bindings: arm: fsl: Add Kontron i.MX8MP OSM-S based boards
8e60288ef257 arm64: dts: imx93-11x11-evk: Enable sound-wm8962 sound card
f7899e2eb04d arm64: dts: imx93-11x11-evk: add flexcan support
0c059ea2b317 arm64: dts: imx93-11x11-evk: add io-expander adi,adp5585-01
27a12bb96f4a arm64: dts: imx93-11x11-evk: remove redundant "sleep" pinctrl in lpi2c2 node
ce488aac6011 dt-bindings: clocks: add binding for gated-fixed-clocks
a52fb79b0ede arm64: dts: renesas: r9a09g057: Add ICU node
c70b39c7804c dt-bindings: interrupt-controller: Add Renesas RZ/V2H(P) Interrupt Controller
6b2ee6f97f03 dt-bindings: iio: light: veml6030: add veml7700
809b7c6f70ab riscv: dts: thead: remove enabled property for spi0
6b7745f477d0 riscv: dts: thead: Add missing GPIO clock-names
90e90f2cfc80 riscv: dtb: thead: Add BeagleV Ahead LEDs
844db5464ff5 riscv: dts: thead: Add TH1520 pinctrl settings for UART0
36270053083a riscv: dts: thead: Add Lichee Pi 4M GPIO line names
73fb6b2c50d6 riscv: dts: thead: Adjust TH1520 GPIO labels
339c9346dc4a riscv: dts: thead: Add TH1520 GPIO ranges
fc28f97249d5 riscv: dts: thead: Add TH1520 pin control nodes
d15a1d47fc59 dt-bindings: vendor-prefixes: add spacemit
16c7c623dee2 dt-bindings: backlight: Convert zii,rave-sp-backlight.txt to yaml
d42ad23dcba4 dt-bindings: leds: Add 'active-high' property
52c7513233d2 dt-bindings: net: tja11xx: add "nxp,rmii-refclk-out" property
786b481a9829 arm64: dts: imx8mm-emtop-baseboard: Add Peripherals Support
b71ca16e750e arm64: dts: imx8-apalis: Add usb4 host support
2394fd72d428 arm64: dts: imx8-apalis: Add nau8822 audio-codec to apalis eval v1.2
e3c292d1f737 arm64: dts: imx8-apalis: Add audio support
c96165670fbd arm64: dts: imx8-apalis: Set thermal thresholds
1db463a2e954 arm64: dts: imx8qm: Remove adma pwm
c035becefc62 arm64: dts: qcom: sa8775p: extend the register range for UFS ICE
7ff7071f9f43 arm64: dts: qcom: sm8550: extend the register range for UFS ICE
889c773c3f84 arm64: dts: qcom: sm8650: extend the register range for UFS ICE
555a22db63da arm64: dts: qcom: sa8775p: Populate additional UART DT nodes
b21f6a0e8035 arm64: dts: qcom: x1e80100-t14s: add another trackpad support
c6d16d152204 arm64: dts: qcom: Add support for X1-based Dell XPS 13 9345
bcddc55313a4 dt-bindings: arm: qcom: Add Dell XPS 13 9345
75acf9f43361 arm64: dts: qcom: x1e78100-t14s: enable otg on usb-c ports
4ce3cb7331f1 arm64: dts: qcom: x1e80100-crd: enable otg on usb ports
3d1e606e47ea arm64: dts: qcom: x1e80100: enable OTG on USB-C controllers
b9303b525b4b arm64: dts: qcom: x1e80100-vivobook-s15: Drop orientation-switch from USB SS[0-1] QMP PHYs
c51166f8ad48 arm64: dts: qcom: x1e80100-slim7x: Drop orientation-switch from USB SS[0-1] QMP PHYs
37e90c03b449 arm64: dts: qcom: Drop undocumented domain "idle-state-name"
aeb29cc23669 arm64: dts: qcom: sc7280: Add 0x81 Adreno speed bin
3c5b615079b4 arm64: dts: qcom: x1e80100: enable GICv3 ITS for PCIe
f9ab469e781d dt-bindings: dma: rz-dmac: Document RZ/A1H SoC
423821e8b5cf dt-bindings: rtc: mpfs-rtc: Properly name file
8c9723a68cf6 dt-bindings: mmc: sdhci-msm: Document the X1E80100 SDHCI Controller
1d51903da4ef dt-bindings: mmc: sdhci-msm: add IPQ5424 compatible
20e9a1c8d97c dt-bindings: mmc: cdns,sdhci: ref sdhci-common.yaml
70c9390cfaa7 dt-bindings: mmc: cdns: document Microchip PIC64GX MMC/SDHCI controller
ca5d807bbbdf ARM: dts: rockchip: Add Relfor Saib board
38159d2940cf dt-bindings: arm: rockchip: Add Relfor Saib board
c7f8baab2a0c dt-bindings: vendor-prefixes: Add Relfor labs
46ba63fe482f ARM: dts: rockchip: Add watchdog node for RV1126
1e35f91de25d dt-bindings: watchdog: rockchip: Add rockchip,rv1126-wdt string
5c092b1d7063 arm64: dts: renesas: rzg3s-smarc: Use interrupts-extended for gpio-keys
b1ff59620ae1 arm64: dts: renesas: beacon-renesom: Use interrupts-extended for touchscreen
3434d2b8e224 arm64: dts: renesas: Use interrupts-extended for WLAN
224f6a584251 arm64: dts: renesas: Use interrupts-extended for video decoders
4cde4936ee89 arm64: dts: renesas: Use interrupts-extended for USB muxes
21837e846ca6 arm64: dts: renesas: Use interrupts-extended for PMICs
08ab7120e63b arm64: dts: renesas: Use interrupts-extended for I/O expanders
80b32a671718 arm64: dts: renesas: Use interrupts-extended for HDMI bridges
8c17f11e2b8a arm64: dts: renesas: Use interrupts-extended for Ethernet PHYs
561722cb17bb arm64: dts: renesas: Use interrupts-extended for DisplayPort bridges
aa4687349f31 ARM: dts: renesas: kzm9g: Use interrupts-extended for sensors
65b548334a98 ARM: dts: renesas: kzm9g: Use interrupts-extended for I/O expander
276f27402851 ARM: dts: renesas: r8a7742-iwg21m: Use interrupts-extended for RTC
a4e199acde95 ARM: dts: renesas: iwg22d-sodimm: Use interrupts-extended for port expander
87a105b8df5c ARM: dts: renesas: Use interrupts-extended for video decoders
3a7481a6911d ARM: dts: renesas: Use interrupts-extended for touchpanels
007b9bf3c590 ARM: dts: renesas: Use interrupts-extended for PMICs
ec9235ef00d3 ARM: dts: renesas: Use interrupts-extended for HDMI bridges
34f3321ec6df ARM: dts: renesas: Use interrupts-extended for Ethernet PHYs
2ad74334f74f ARM: dts: renesas: Use interrupts-extended for Ethernet MACs
25c3332c9796 dt-bindings: gpio: aspeed,ast2400-gpio: Support ast2700
93d9a41cf53a Merge tag 'v6.12-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into gpio/for-next
6800013270c4 Merge 6.12-rc3 into usb-next
ae776265ffc9 dt-bindings: clock: add support for lan969x
e1975abaca46 ARM: dts: microchip: Rename LED sub nodes name
8f0592fd90d9 ARM: dts: microchip: Rename the pmic node
19694a10b460 ARM: dts: microchip: Rename the eeprom nodename
803e741b26b4 ARM: dts: microchip: sama7g5ek: Add power monitor support
369739ce16a1 ARM: dts: microchip: sama7g54_curiosity: Add power monitor support
9db788660aa1 ARM: dts: microchip: sama5d2_icp: Add power monitor support
c904ffbc3092 ARM: dts: microchip: sam9x60ek: Add power monitor support
b7f7646bf617 ARM: dts: microchip: Unify rng node names
7bcf27db3e0e ARM: dts: microchip: Add trng labels for all at91 SoCs
d349c4f85ddc ARM: dts: microchip: sam9x60: Add missing property atmel,usart-mode
1572a7cd3baf dt-bindings: microchip: atmel,at91rm9200-tcb: add sam9x7 compatible
82fd17cf9cca arm64: dts: ti: Add support for J742S2 EVM board
3fbb4e71ee4a arm64: dts: ti: Introduce J742S2 SoC family
9200229331e7 dt-bindings: arm: ti: Add bindings for J742S2 SoCs and Boards
5ad7086348b1 arm64: dts: ti: Refactor J784s4-evm to a common file
61116717b2c8 arm64: dts: ti: Refactor J784s4 SoC files to a common file
081c45d86c97 dt-bindings: media: ti,j721e-csi2rx-shim: Update maintainer email
e97c92a1288d dt-bindings: iio: adc: add AD762x/AD796x ADCs
bb8c9c2a684f Merge tag 'v6.12-rc2' into test2
d4a1153e08d3 dt-bindings: net: emaclite: Add clock support
2d4c608b14c2 dt-bindings: rtc: mpfs-rtc: Add PIC64GX compatibility
82fb791a0b4f dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: Add QCS8300 compatible
a006ae08f18c dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for QCS8300
2a47837a6a43 dt-bindings: usb: qcom,dwc3: Add QCS8300 to USB DWC3 bindings
e8276f3d76ac dt-bindings: leds: bcm63138: Add shift register bits
1c98277621a1 dt-bindings: serial: snps-dw-apb-uart: Document Rockchip RK3528
4591ac9bf944 dt-bindings: serial: snps-dw-apb-uart: Add Rockchip RK3576
0c0550d3439e dt-bindings: serial: rs485: Fix rs485-rts-delay property
bc03157c4989 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
1552fc04c8e3 Merge tag 'drm-misc-next-2024-10-09' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
7641349eb174 arm64: dts: exynosautov920: add peric1, misc and hsi0/1 clock DT nodes
d9318718df7e Merge branch 'for-v6.13/clk-dt-bindings' into next/dt64
045dbca8dfe9 Merge branch 'for-v6.13/clk-dt-bindings' into next/clk
c6057e9c7a9e dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions
49395d036a58 dt-bindings: leds: Document "rc-feedback" trigger
68abe5c0bbec dt-bindings: clock: xilinx: describe whether dynamic reconfig is enabled
4ce301971c64 ASoC: dt-bindings: Add Loongson I2S controller
871ccd03f57e ASoC: dt-bindings: Add NXP uda1342 Codec
e2c119138d31 ASoC: dt-bindings: Add Everest ES8323 Codec
e7152c3acca2 arm64: dts: renesas: r8a779h0: Add OTP_MEM node
65a521f35063 arm64: dts: renesas: r8a779g0: Add OTP_MEM node
04cdb59fe3ff arm64: dts: renesas: r8a779f0: Add E-FUSE node
4195489a94de arm64: dts: renesas: r8a779a0: Add E-FUSE node
1113149692ef arm64: dts: renesas: beacon: Add SD/OE pin properties
58ef1410262d arm64: dts: renesas: hihope: Add SD/OE pin properties
5e1e0dfe606a arm64: dts: renesas: salvator-x: Add SD/OE pin properties
2f6df7189b2d arm64: dts: renesas: ulcb: Add SD/OE pin properties
9fca3436586b arm64: dts: renesas: salvator-xs: Add SD/OE pin properties
5412125ac591 ARM: dts: renesas: genmai: Enable MMCIF
c3e40a9b9efb ARM: dts: renesas: genmai: Enable SDHI0
dccdee817ccc arm64: dts: renesas: rz{g2l,g2lc}-smarc-som: Update partition table for spi-nor flash
78a979f6cfd9 arm64: dts: renesas: rzg2ul-smarc-som: Enable serial NOR flash
348e61ec8d0d dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow schmitt and open drain properties
edcb99a82f7e Merge wireless-next into staging-next
a71be37b5de8 arm64: dts: amlogic: Add Amlogic C3 PWM
200722693564 dt-bindings: display: panel: Add Samsung AMS639RQ08
043a4e837c78 dt-bindings: panel: add Samsung s6e3ha8
282c7dde11e3 dt-bindings: display: panel-lvds: Add compatible for Jenson BL-JT60050-01A
99d670ed3553 dt-bindings: vendor-prefixes: Add Jenson Display
259161dcea8e Merge net-next/main to resolve conflicts
e693d5afac4a Merge tag 'drm-misc-next-2024-09-26' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
2955a2febba6 dt-bindings: net: marvell,aquantia: add property to override MDI_CFG
c3f883a9e9bf Merge tag 'drm-misc-next-2024-09-20' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
b0a2a71ee7b7 dt-bindings: clock: convert rockchip,rk3328-cru.txt to YAML
a5b48af0bb34 arm64: rockchip: add clocks property to cru node rk3328
95f747b4f658 arm64: dts: rockchip: fix compatible string rk3328 cru node
8378a03b73ae dt-bindings: writing-schema: Add details on YAML text blocks
2a556c7c3f8a regulator: dt-bindings: vctrl-regulator: convert to YAML
09d320f523bf dt-bindings: net: fec: add pps channel property
9d2430d75454 ARM: dts: imx7ulp: add "nxp,sim" property for usbphy1
b6098914fba3 arm64: dts: s32g2: Disable support for SD/eMMC UHS mode
e25af93c7f88 arm64: dts: s32g: Add S32G2/S32G3 uSDHC pinmux
1fe5abb81f67 ARM: dts: imx28-apx4devkit: Fix the rtc compatible
ca76f55fc4ff dt-bindings: net: ethernet-phy: Add timing-role role property for ethernet PHYs
420663585109 ARM: dts: imx6qdl-mba6: Add reserved memory area for CMA memory
7f8a95299bd0 arm64: dts: imx8mm: Add dbi2 and atu reg for i.MX8MM PCIe EP
44e6d98d4cc6 arm64: dts: imx8mp: Add dbi2 and atu reg for i.MX8MP PCIe EP
a2021b75e127 arm64: dts: imx8mq: Add dbi2 and atu reg for i.MX8MQ PCIe EP
dc211561776b dt-bindings: net: realtek: Use proper node names
cd6d97f59761 arm64: dts: qcom: qcs6490-rb3gen2: Enable PWR/VOL keys
ebbe6a9c33fe arm64: dts: qcom: qcs6490-rb3gen2: Specify i2c1 clock frequency
5a588983eab1 ASoC: dt-bindings: rockchip,rk3036-codec: convert to yaml
2b7c81f060b6 ASoC: Merge up v6.12
d820555c1f28 spi: Merge up v6.12
f650903e3b7f ARM: dts: renesas: rcar-gen2: Switch HS-USB to renesas,enable-gpios
39bee53dfd9e ARM: dts: renesas: r7s72100: 'bus-width' is a board property
eb9f07d9e4f4 arm64: dts: renesas: beacon-renesom: Switch to mic-det-gpios
9e4ebc4803d2 ARM: dts: renesas: Use proper node names for keys
bb139ec6c060 ARM: dts: renesas: r8a7778: Rename 'bsc' to 'lbsc'
b8e0085e6650 ARM: dts: renesas: Add proper node names to (L)BSC devices
f71cb63ecb03 dt-bindings: phy: cadence-sierra: Allow PHY types QSGMII and SGMII
a1a280e3c562 dt-bindings: phy: Add STM32MP25 COMBOPHY bindings
1cce969a3069 arm64: dts: qcom: sda660-ifc6560: enable mDSP and WiFi devices
385f3a706daf arm64: dts: qcom: sdm630: add WiFI device node
ba24d1324aa0 arm64: dts: qcom: sdm630: enable A2NOC and LPASS SMMU
b4f0cdb93361 arm64: dts: qcom: sda660-ifc6560: fix l10a voltage ranges
08516c3836c6 arm64: dts: qcom: sda660-ifc6560: enable GPU
ef67aa0a21f7 arm64: dts: qcom: sdm630: enable GPU SMMU and GPUCC
981d78b61dce dt-bindings: iio: light: veml6030: add veml6035
e0d7b63c359e dt-bindings: iio: light: veml6030: add vdd-supply property
659a221815d7 dt-bindings: iio: dac: ad3552r: fix maximum spi speed
89bd84e00d20 dt-bindings: iio: imu: migrate InvenSense email to TDK group domain
9f2f8b13c6ec dt-bindings: iio: adc: Add the GE HealthCare PMC ADC
332a4726d46d dt-bindings: vendor-prefixes: Add an entry for GE HealthCare
7d0dcec5cf2b arm64: dts: qcom: qcm6490-fairphone-fp5: Add thermistor for UFS/RAM
9faee8d13bbb arm64: dts: qcom: sm6350: Fix GPU frequencies missing on some speedbins
59021fcbaea7 arm64: dts: qcom: sc8280xp: Add Microsoft Surface Pro 9 5G
f941eb9e840d arm64: dts: qcom: sc8280xp: Add uart18
58766bb02b1a dt-bindings: arm: qcom: Document Microsoft Surface Pro 9 5G
d2a8bd12a58a arm64: dts: qcom: minor whitespace cleanup
650341209ce1 arm64: dts: qcom: drop underscore in node names
87dafc2af9bf ARM: dts: qcom: minor whitespace cleanup
68ba7e3093c4 ARM: dts: qcom: drop underscore in node names
f0e620731d60 arm64: dts: qcom: x1e80100-romulus: Set up USB Multiport controller
15693801706e arm64: dts: qcom: x1e80100-romulus: Add lid switch
3ac1117ff640 dt-bindings: clock: qcom,sm8450-camcc: Add SM8475 CAMCC bindings
10088f897c56 dt-bindings: clock: qcom,sm8450-videocc: Add SM8475 VIDEOCC bindings
583c833f335a dt-bindings: clock: qcom,sm8450-gpucc: Add SM8475 GPUCC bindings
90455163e2d5 dt-bindings: clock: qcom,sm8450-dispcc: Add SM8475 DISPCC bindings
7931a601e1a3 dt-bindings: clock: qcom,gcc-sm8450: Add SM8475 GCC bindings
4bd022291a79 arm64: dts: qcom: sc7280: Fix PMU nodes for Cortex A55 and A78
d2f949857a37 arm64: dts: qcom: x1e80100: Add debug uart to Lenovo Yoga Slim 7x
d6b8df3106b0 arm64: dts: qcom: x1e80100: describe tcsr download mode register
731c1cb1f4d5 arm64: dts: qcom: qcs6460-rb3gen2: enable venus node
e9720dc3afbb arm64: dts: qcom: x1e80100: Affirm IDR0.CCTW on apps_smmu
06424041d32a arm64: dts: qcom: sm8450: Affirm IDR0.CCTW on apps_smmu
47ccab6fcc0b arm64: dts: qcom: sm8350: Affirm IDR0.CCTW on apps_smmu
e45dd32195c3 arm64: dts: qcom: sm8150: Affirm IDR0.CCTW on apps_smmu
8f3c1d70a169 arm64: dts: qcom: sm6350: Affirm IDR0.CCTW on apps_smmu
df39a8050659 arm64: dts: qcom: sdm845: Affirm IDR0.CCTW on apps_smmu
270061a6fab8 arm64: dts: qcom: sdm670: Affirm IDR0.CCTW on apps_smmu
29387ce4c082 arm64: dts: qcom: sc8280xp: Affirm IDR0.CCTW on apps_smmu
7a314949e604 arm64: dts: qcom: sc8180x: Affirm IDR0.CCTW on apps_smmu
435e35553ca3 arm64: dts: qcom: sc7180: Affirm IDR0.CCTW on apps_smmu
8a7b76025358 arm64: dts: qcom: qdu1000: Affirm IDR0.CCTW on apps_smmu
ec6f718f9ab9 arm64: dts: qcom: qcs6490-rb3gen2: Add SD Card node
31437b048a52 arm64: dts: qcom: sm8650-qrd: remove status property from dispcc device tree node
57ad38d9eb28 arm64: dts: qcom: sm8650-mtp: remove status property from dispcc device tree node
8132697f573a arm64: dts: qcom: sm8650-hdk: remove status property from dispcc device tree node
84ca17adb974 arm64: dts: qcom: sm8650: don't disable dispcc by default
79a12df8a93d arm64: dts: qcom: sm8450-hdk: remove status property from dispcc device tree node
08f0740fbe38 arm64: dts: qcom: sm8450: don't disable dispcc by default
6a5d2b07a1c2 arm64: dts: qcom: sm8450-sony-xperia-nagara: disable dispcc on derived boards
f90b98759450 arm64: dts: qcom: sm8450-qrd: explicitly disable dispcc on the board
000a8024c143 arm64: dts: qcom: sm8350-hdk: remove a blank overwrite of dispcc node status
8fa4a6d46ef3 arm64: dts: qcom: msm8998: add HDMI nodes
6a7fdd43be12 arm64: dts: rockchip: Switch to hp-det-gpios
110fc4fc8fbf arm64: dts: rockchip: Switch to simple-audio-card,hp-det-gpios
ce578767c731 dt-bindings: iio: light: vishay,veml6075: add vishay,veml6070
29868b055c92 dt-bindings: iio: imu: mpu6050: Add iam20680ht/hp bindings to mpu6050
359080581950 ASoC: Clean up {hp,mic}-det-gpio handling
0df63b22c8f6 ARM: dts: ti: dra7: Remove double include of clock bindings
0283571a7331 ARM: dts: ti: omap3434-sdp: drop linux,mtd-name from onenand node
00b214888af5 ARM: dts: ti: omap: am335x-baltos: drop "gpmc,device-nand" from NAND node
f8150d134ba2 ARM: dts: ti: drop linux,mtd-name from NAND nodes
de6fed174a79 ARM: dts: ti/omap: Fix at24 EEPROM node names
18d97d6cc1c4 dt-bindings: usb: dwc3-imx8mp: add compatible string for imx95
2a4990169e34 dt-bindings: phy: imx8mq-usb: add compatible "fsl,imx95-usb-phy"
fb1256fa92bc dt-bindings: usb: renesas,usbhs: Deprecate renesas,enable-gpio
787d98ae3b39 dt-bindings: usb: add PIC64GX compatibility to mpfs-musb driver
f381d0e73e2b dt-bindings: usb: cypress,cypd4226: Drop Tegra specific GPIO defines
300bb4269d7b dt-bindings: usb: genesys,gl850g: allow downstream device subnodes
c989019ae660 riscv: dts: sophgo: cv1812h: add pinctrl support
b991927c7c78 riscv: dts: sophgo: cv1800b: add pinctrl support
5ea06508d59d scsi: ufs: ufs: qcom: dt-bindings: Document the QCS8300 UFS Controller
ecac4d7c7cc8 dt-bindings: fpga: altr,fpga-passive-serial: Convert to yaml
2403f95db3f8 ASoC: dt-bindings: Deprecate {hp,mic}-det-gpio
87fe2b600252 arm64: dts: qcom: msm8998: add HDMI GPIOs
c7e517c97fb1 dt-bindings: PCI: mediatek-gen3: Allow exact number of clocks only
585c45d07807 dt-bindings: gpio: st,nomadik-gpio: Add missing "#interrupt-cells" to example
e53b6c7b8261 dt-bindings: interrupt-controller: Add support for sam9x7 aic
8da717b8063d dt-bindings: power: qcom,rpmpd: document qcs615 RPMh power domains
4c93f97cdc68 dt-bindings: power: qcom,rpmpd: document qcs8300 RPMh power domains
3812a499aa89 arm64: dts: mediatek: mt8188: Add SPMI support for PMIC control
45b1e1440500 arm64: dts: mediatek: mt8188: Add PWM nodes for display backlight
adecb482d783 arm64: dts: mediatek: mt8188: Add SMI/LARB/IOMMU support
5c2395ccf030 arm64: dts: mediatek: mt8188: Add CPU performance controller for CPUFreq
15509164371c arm64: dts: mt8183: Add port node to dpi node
8b07a795fc1c arm64: dts: mt8192-asurada-spherion: Add Synaptics trackpad support
69967111e2b7 arm64: dts: mediatek: mt8186: add FHCTL node
5469dabf6e10 arm64: dts: mediatek: mt8183-pumpkin: add HDMI support
5b01d93025d9 arm64: dts: mediatek: mt8183-kukui: Disable DPI display interface
3bf7adce8f91 arm64: dts: mt8195: Fix dtbs_check error for infracfg_ao node
3eb5b79226ac arm64: dts: mt8195: Fix dtbs_check error for mutex node
79d5a4c7c8b5 arm64: dts: mediatek: mt8395-genio-1200-evk: Fix dtbs_check error for phy
f7e4d69ece47 arm64: dts: mediatek: mt8188: Move SPI NOR *-cells properties
5311cb9de085 arm64: dts: mediatek: mt8188: Move vdec1 power domain under vdec0
41b85940d81e arm64: dts: mediatek: mt8188: Update vppsys node names to syscon
372ce47e0e06 arm64: dts: mediatek: mt8188: Add missing dma-ranges to soc node
288630890bef arm64: dts: mediatek: mt8390-genio-700-evk: Enable Mali GPU
f6802405f4e0 arm64: dts: mediatek: mt8188: Fix wrong clock provider in MFG1 power domain
d4805550924b arm64: dts: rockchip: Enable all 3 USBs on Turing RK1
c9b0d499654d arm64: dts: rockchip: Add Powkiddy RGB20SX
c5b382a594f3 dt-bindings: arm: rockchip: Add Powkiddy RGB20SX
39e90c62b050 arm64: dts: rockchip: Add power button for puma-haikou
b531c25e8e6a dt-bindings: hwinfo: samsung,exynos-chipid: add exynos8895 compatible
fe24d3cdfab3 arm64: dts: exynos: Add initial support for Samsung Galaxy S8
09bf72ba53d2 arm64: dts: exynos: Add initial support for exynos8895 SoC
24af01abacf8 dt-bindings: soc: samsung: exynos-pmu: Add exynos8895 compatible
4ef6f9244f74 dt-bindings: arm: samsung: Document dreamlte board binding
7218905e111f dt-bindings: pinctrl: samsung: add exynos8895-wakeup-eint compatible
41f5d2a15643 dt-bindings: pinctrl: samsung: Add compatible for Exynos8895 SoC
4f59ba89a4a4 dt-bindings: arm: cpus: Add Samsung Mongoose M2
4a89b93976ca arm64: zynqmp: Add thermal zones
11a1b40f2a46 arm64: zynqmp: Expose AMS to userspace as HWMON
9c79137dfa71 arm64: zynqmp: Enable AMS for all boards
4297cfaff763 ARM: dts: socfpga: Fix at24 EEPROM node names
1a8e565ffe0b dt-bindings: Fix array property constraints
c1848318abfe dt-bindings: interrupt-controller: fsl,mu-msi: Drop "interrupt-controller" property
1ec511ef069d dt-bindings: interrupt-controller: ti,sci-inta: Add missing "#interrupt-cells" to example
74424e7f23bb dt-bindings: trivial-devices: add onnn,adt7462
63357e975889 dt-bindings: pinctrl: document the QCS615 Top Level Mode Multiplexer
9f689f9f85b1 ASoC: Add NTP8918 and NTP8835 codecs support
d083bbb62bec dt-bindings: pinctrl: amlogic,meson-pinctrl: lower gpio-line-names minItems for meson8b
edd8d8764671 dt-bindings: pinctrl: Add support for canaan,k230 SoC
6a4f33926064 ARM: dts: renesas: rskrza1: Enable watchdog timer
2a6957e1269c arm64: dts: renesas: rcar-gen4: Switch PCIe to reset-gpios
2ba8c4a5d5d8 ARM: dts: renesas: rza2mevb: Use interrupts-extended for gpio-keys
f7a030d3b38b ARM: dts: renesas: rskrza1: Use interrupts-extended for gpio-keys
aaecea0f8bd4 ARM: dts: renesas: marzen: Use interrupts-extended for gpio-keys
2f03ec558600 ARM: dts: renesas: Remove 'reg-io-width' properties from MMCIF nodes
fff0ddf2bce0 ARM: dts: renesas: Genmai: Update audio codec device node
d8679d2be154 ARM: dts: renesas: genmai: Define keyboard switch
fbb0e65b243d ARM: dts: renesas: genmai: Sort nodes
ea18b054bf65 ARM: dts: renesas: genmai: Enable OS timer modules
68f8258dbf51 ARM: dts: renesas: genmai: Enable watchdog
c733788f6999 ARM: dts: renesas: genmai: Fix partition size for QSPI NOR Flash
36d49e7ae7cc arm64: dts: renesas: r8a779h0: gray-hawk-single: Enable PCIe Host
0d0c88a036b8 arm64: dts: renesas: r8a779h0: Add PCIe Host and Endpoint nodes
d909bff40dfc dt-bindings: pinctrl: qcom: add IPQ5424 pinctrl
28dc5229ae20 Merge branch 'ib-thead-th1520' into devel
33380f1c1ff3 dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings
259cd8c48685 dt-bindings: ocelot: document lan969x-pinctrl
8a571eac3232 dt-bindings: pinctrl: Add SA8255p TLMM
af7be1413d12 dt-bindings: pinctrl: Add support for Xilinx Versal platform
c78de6d3a962 dt-bindings: opp: operating-points-v2-ti-cpu: Describe opp-supported-hw
ec5754987a33 dt-bindings: cpufreq: qcom-hw: document support for SA8255p
ba56c1c064ae arm64: dts: qcom: qcm6490-rb3gen2: enable WiFi
ef14321de506 arm64: dts: qcom: qcm6490-idp: enable WiFi
600a06a3b099 arm64: dts: qcom: sc7280: don't enable GPU on unsupported devices
54debad84f18 arm64: dts: qcom: qcs6390-rb3gen2: use modem.mbn for modem DSP
1031c2c08dea ASoC: dt-bindings: mt6359: Update generic node name and dmic-mode
892d16539671 arm64: dts: rockchip: add LED_FUNCTION_STATUS for RGB LEDs on Radxa E25
c832f8ac3bdc arm64: dts: rockchip: Add AP6275P wireless support to Khadas Edge 2
43840031417b arm64: dts: rockchip: Enable GPU on Turing RK1
3e0e636a275b arm64: dts: rockchip: Enable automatic fan control on Turing RK1
36cf08da66a0 arm64: dts: rockchip: Fix Turing RK1 PCIe3 hang
0764ad8c0518 dt-bindings: clock: samsung: remove define with number of clocks for FSD
3754b2afab7e dt-bindings: memory-controllers: fsl,ifc: split child node differences
8713425fa162 arm64: dts: rockchip: Split up RK3588's PCIe pinctrls
da10f3b08e0f arm64: dts: rockchip: Add RK3588S EVB1 board
33d6b7f1ff4c dt-bindings: arm: rockchip: Add RK3588S EVB1 board
e19e92e9272b arm64: dts: rockchip: Add ArmSoM W3 board
25b187da6e7e arm64: dts: rockchip: Add ArmSoM LM7 SoM
9dad170bea61 dt-bindings: arm: rockchip: Add ArmSoM LM7 SoM
c80b7eba6833 dt-bindings: clock: convert amlogic,meson8b-clkc.txt to dtschema
e5b590f7e262 arm64: dts: rockchip: enable automatic fan control on Orange Pi 5+
5f528a6fedb9 Merge drm/drm-next into drm-misc-next
da705300feb6 arm64: dts: rockchip: add attiny_rst_gate to Ringneck
ee185d62e14c arm64: dts: rockchip: add tsd,mule-i2c-mux on px30-ringneck
12d6e10731a4 arm64: dts: rockchip: add tsd,mule-i2c-mux on rk3588-tiger
2dc1a4182c54 arm64: dts: rockchip: add tsd,mule-i2c-mux on rk3399-puma
f3e1990f27da arm64: dts: rockchip: add tsd,mule-i2c-mux on rk3588-jaguar
d61cebb06ff5 dt-bindings: iio: adc: add docs for AD7606C-{16,18} parts
51789d5e7711 dt-bindings: iio: adc: document diff-channels corner case for some ADCs
5e6cfa1a03fb dt-bindings: iio: adc: amlogic,meson-saradc: also allow meson8-saradc to have amlogic,hhi-sysctrl property
970192b0e4c8 dt-bindings: iio: dac: add docs for ad8460
f952c57b067c dt-bindings: iio: light: veml6030: rename to add manufacturer
0cc281b14ca3 dt-bindings: iio: imu: add bmi270 bindings
2b6408921687 dt-bindings: iio: temperature: tmp006: document interrupt
458e2c6fa81b dt-bindings: adc: ad7173: add support for ad4113
da37218f1f2c ARM: dts: amlogic: meson8b-ec100: add missing gpio-line-names entry
68910695abce ARM: dts: amlogic: meson8b-ec100: add missing clocks property in sound card
5dc11b8ed550 ARM: dts: amlogic: meson8-minix-neo-x8: fix invalid pnictrl-names
e9810e32f796 ARM: dts: amlogic: add missing phy-mode in ethmac node
9245aa5c751f ARM: dts: amlogic: meson8: use correct pinctrl bank node name
98b22e41c153 ARM: dts: amlogic: fix /memory node name
4b92b8bf2966 ARM: dts: amlogic: meson8b-odroidc1: fix invalid reset-gpio
6566ba1b4784 ARM: dts: amlogic: meson6: remove support for ATV1200 board
9af30064241f ARM: dts: amlogic: meson8: fix ao_arc_sram node name
0a7a4881969f ARM: dts: amlogic: meson8: fix soc thermal-zone node name
65b134aa3213 ARM: dts: amlogic: meson6: fix clk81 node name
7044f82e12d9 arm64: dts: meson-g12-common: fix uart-ao-a typo
d3b5013b44d4 arm64: dts: meson: a1: bind power domain to temperature sensor
21e260e3efc5 arm64: dts: meson: a1: add definitions for meson PWM
0af71311758b dt-bindings: input: document Novatek NVT touchscreen controller
e3b7e5dc666b dt-bindings: spi: zynqmp-qspi: Include two 'reg' properties only for the Zynq UltraScale QSPI
18838fc29859 ASoC: dt-bindings: realtek,rt5640: Convert to dtschema
45a46ecc03be ASoC: dt-bindings: fsl-esai: Add power-domains for fsl,imx8qm-esai
7cc0672d511b ASoC: dt-bindings: Add NeoFidelity NTP8835
fe920ac500b5 ASoC: dt-bindings: Add NeoFidelity NTP8918
d1100655b714 dt-bindings: vendor-prefixes: Add NeoFidelity, Inc
1dc6b237e2cb dt-bindings: net: ath11k: document the inputs of the ath11k on WCN6855
30556a11ec4f dt-bindings: lcdif: Document the dmas/dma-names properties
d8fb8bc2cda5 dt-bindings: net: wireless: brcm4329-fmac: add clock description for AP6275P
e479085c013c dt-bindings: net: wireless: brcm4329-fmac: add pci14e4,449d
7ad9cb0fdd60 Merge drm/drm-next into drm-misc-next
f3263e455928 dt-bindings: gpu: Add rockchip,rk3576-mali compatible
ab5d13f0b89f dt-bindings: display: bridge: add TI TDP158
a696036bd331 dt-bindings: display: imx/ldb: drop ddc-i2c-bus property
0bf2495489f6 dt-bindings: display: fsl-imx-drm: drop edid property support

git-subtree-dir: dts/upstream
git-subtree-split: 8531b4b4988c2c9bddc90ea74f2d3e2dca9d5056

Bindings/Makefile

@@ -56,7 +56,6 @@ DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_all_cmd)))
 override DTC_FLAGS := \
 	-Wno-avoid_unnecessary_addr_size \
 	-Wno-graph_child_address \
-	-Wno-interrupt_provider \
 	-Wno-unique_unit_address \
 	-Wunique_unit_address_if_enabled
 

Bindings/arm/airoha,en7581-chip-scu.yaml

@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/airoha,en7581-chip-scu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha Chip SCU Controller for EN7581 SoC
+
+maintainers:
+  - Lorenzo Bianconi <lorenzo@kernel.org>
+
+description:
+  The airoha chip-scu block provides a configuration interface for clock,
+  io-muxing and other functionalities used by multiple controllers (e.g. clock,
+  pinctrl, ecc) on EN7581 SoC.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - airoha,en7581-chip-scu
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+      syscon@1fa20000 {
+        compatible = "airoha,en7581-chip-scu", "syscon";
+        reg = <0x0 0x1fa20000 0x0 0x388>;
+      };
+    };

Bindings/arm/apple.yaml

@@ -12,7 +12,58 @@ maintainers:
 description: |
   ARM platforms using SoCs designed by Apple Inc., branded "Apple Silicon".
 
-  This currently includes devices based on the "M1" SoC:
+  This currently includes devices based on the "A7" SoC:
+
+  - iPhone 5s
+  - iPad Air (1)
+  - iPad mini 2
+  - iPad mini 3
+
+  Devices based on the "A8" SoC:
+
+  - iPhone 6
+  - iPhone 6 Plus
+  - iPad mini 4
+  - iPod touch 6
+  - Apple TV HD
+
+  Device based on the "A8X" SoC:
+
+  - iPad Air 2
+
+  Devices based on the "A9" SoC:
+
+  - iPhone 6s
+  - iPhone 6s Plus
+  - iPhone SE (2016)
+  - iPad 5
+
+  Devices based on the "A9X" SoC:
+
+  - iPad Pro (9.7-inch)
+  - iPad Pro (12.9-inch)
+
+  Devices based on the "A10" SoC:
+
+  - iPhone 7
+  - iPhone 7 Plus
+  - iPod touch 7
+  - iPad 6
+  - iPad 7
+
+  Devices based on the "A10X" SoC:
+
+  - Apple TV 4K (1st generation)
+  - iPad Pro (2nd Generation) (10.5 Inch)
+  - iPad Pro (2nd Generation) (12.9 Inch)
+
+  Devices based on the "A11" SoC:
+
+  - iPhone 8
+  - iPhone 8 Plus
+  - iPhone X
+
+  Devices based on the "M1" SoC:
 
   - Mac mini (M1, 2020)
   - MacBook Pro (13-inch, M1, 2020)
@@ -65,6 +116,113 @@ properties:
     const: "/"
   compatible:
     oneOf:
+      - description: Apple A7 SoC based platforms
+        items:
+          - enum:
+              - apple,j71  # iPad Air (Wi-Fi)
+              - apple,j72  # iPad Air (Cellular)
+              - apple,j73  # iPad Air (Cellular, China)
+              - apple,j85  # iPad mini 2 (Wi-Fi)
+              - apple,j85m # iPad mini 3 (Wi-Fi)
+              - apple,j86  # iPad mini 2 (Cellular)
+              - apple,j86m # iPad mini 3 (Cellular)
+              - apple,j87  # iPad mini 2 (Cellular, China)
+              - apple,j87m # iPad mini 3 (Cellular, China)
+              - apple,n51  # iPhone 5s (GSM)
+              - apple,n53  # iPhone 5s (LTE)
+          - const: apple,s5l8960x
+          - const: apple,arm-platform
+
+      - description: Apple A8 SoC based platforms
+        items:
+          - enum:
+              - apple,j42d # Apple TV HD
+              - apple,j96  # iPad mini 4 (Wi-Fi)
+              - apple,j97  # iPad mini 4 (Cellular)
+              - apple,n56  # iPhone 6 Plus
+              - apple,n61  # iPhone 6
+              - apple,n102 # iPod touch 6
+          - const: apple,t7000
+          - const: apple,arm-platform
+
+      - description: Apple A8X SoC based platforms
+        items:
+          - enum:
+              - apple,j81 # iPad Air 2 (Wi-Fi)
+              - apple,j82 # iPad Air 2 (Cellular)
+          - const: apple,t7001
+          - const: apple,arm-platform
+
+      - description: Apple Samsung A9 SoC based platforms
+        items:
+          - enum:
+              - apple,j71s # iPad 5 (Wi-Fi) (S8000)
+              - apple,j72s # iPad 5 (Cellular) (S8000)
+              - apple,n66  # iPhone 6s Plus (S8000)
+              - apple,n69u # iPhone SE (S8000)
+              - apple,n71  # iPhone 6S (S8000)
+          - const: apple,s8000
+          - const: apple,arm-platform
+
+      - description: Apple TSMC A9 SoC based platforms
+        items:
+          - enum:
+              - apple,j71t # iPad 5 (Wi-Fi) (S8003)
+              - apple,j72t # iPad 5 (Cellular) (S8003)
+              - apple,n66m # iPhone 6s Plus (S8003)
+              - apple,n69  # iPhone SE (S8003)
+              - apple,n71m # iPhone 6S (S8003)
+          - const: apple,s8003
+          - const: apple,arm-platform
+
+      - description: Apple A9X SoC based platforms
+        items:
+          - enum:
+              - apple,j127 # iPad Pro (9.7-inch) (Wi-Fi)
+              - apple,j128 # iPad Pro (9.7-inch) (Cellular)
+              - apple,j98a # iPad Pro (12.9-inch) (Wi-Fi)
+              - apple,j99a # iPad Pro (12.9-inch) (Cellular)
+          - const: apple,s8001
+          - const: apple,arm-platform
+
+      - description: Apple A10 SoC based platforms
+        items:
+          - enum:
+              - apple,d10  # iPhone 7 (Qualcomm)
+              - apple,d11  # iPhone 7 (Intel)
+              - apple,d101 # iPhone 7 Plus (Qualcomm)
+              - apple,d111 # iPhone 7 Plus (Intel)
+              - apple,j71b # iPad 6 (Wi-Fi)
+              - apple,j72b # iPad 6 (Cellular)
+              - apple,j171 # iPad 7 (Wi-Fi)
+              - apple,j172 # iPad 7 (Cellular)
+              - apple,n112 # iPod touch 7
+          - const: apple,t8010
+          - const: apple,arm-platform
+
+      - description: Apple A10X SoC based platforms
+        items:
+          - enum:
+              - apple,j105a # Apple TV 4K (1st Generation)
+              - apple,j120  # iPad Pro 2 (12.9-inch) (Wi-Fi)
+              - apple,j121  # iPad Pro 2 (12.9-inch) (Cellular)
+              - apple,j207  # iPad Pro 2 (10.5-inch) (Wi-Fi)
+              - apple,j208  # iPad Pro 2 (10.5-inch) (Cellular)
+          - const: apple,t8011
+          - const: apple,arm-platform
+
+      - description: Apple A11 SoC based platforms
+        items:
+          - enum:
+              - apple,d20  # iPhone 8 (Global)
+              - apple,d21  # iPhone 8 Plus (Global)
+              - apple,d22  # iPhone X (Global)
+              - apple,d201 # iPhone 8 (GSM)
+              - apple,d211 # iPhone 8 Plus (GSM)
+              - apple,d221 # iPhone X (GSM)
+          - const: apple,t8015
+          - const: apple,arm-platform
+
       - description: Apple M1 SoC based platforms
         items:
           - enum:

Bindings/arm/atmel-at91.yaml

@@ -106,6 +106,12 @@ properties:
           - const: microchip,sam9x60
           - const: atmel,at91sam9
 
+      - description: Microchip SAM9X7 Evaluation Boards
+        items:
+          - const: microchip,sam9x75-curiosity
+          - const: microchip,sam9x7
+          - const: atmel,at91sam9
+
       - description: Nattis v2 board with Natte v2 power board
         items:
           - const: axentia,nattis-2

Bindings/arm/cpus.yaml

@@ -87,8 +87,14 @@ properties:
     enum:
       - apple,avalanche
       - apple,blizzard
-      - apple,icestorm
+      - apple,cyclone
       - apple,firestorm
+      - apple,hurricane-zephyr
+      - apple,icestorm
+      - apple,mistral
+      - apple,monsoon
+      - apple,twister
+      - apple,typhoon
       - arm,arm710t
       - arm,arm720t
       - arm,arm740t
@@ -202,10 +208,14 @@ properties:
       - qcom,kryo560
       - qcom,kryo570
       - qcom,kryo660
+      - qcom,kryo670
       - qcom,kryo685
       - qcom,kryo780
       - qcom,oryon
       - qcom,scorpion
+      - samsung,mongoose-m2
+      - samsung,mongoose-m3
+      - samsung,mongoose-m5
 
   enable-method:
     $ref: /schemas/types.yaml#/definitions/string

Bindings/arm/fsl.yaml

@@ -379,7 +379,9 @@ properties:
 
       - description: i.MX6Q PHYTEC phyFLEX-i.MX6
         items:
-          - const: phytec,imx6q-pbab01    # PHYTEC phyFLEX carrier board
+          - enum:
+              - comvetia,imx6q-lxr        # Comvetia LXR board
+              - phytec,imx6q-pbab01       # PHYTEC phyFLEX carrier board
           - const: phytec,imx6q-pfla02    # PHYTEC phyFLEX-i.MX6 Quad
           - const: fsl,imx6q
 
@@ -523,9 +525,11 @@ properties:
           - const: dfi,fs700e-m60
           - const: fsl,imx6dl
 
-      - description: i.MX6DL DHCOM PicoITX Board
+      - description: i.MX6DL DHCOM based Boards
         items:
-          - const: dh,imx6dl-dhcom-picoitx
+          - enum:
+              - dh,imx6dl-dhcom-pdk2         # i.MX6DL DHCOM SoM on PDK2 board
+              - dh,imx6dl-dhcom-picoitx      # i.MX6DL DHCOM SoM on PicoITX board
           - const: dh,imx6dl-dhcom-som
           - const: fsl,imx6dl
 
@@ -620,6 +624,14 @@ properties:
               - kobo,librah2o
           - const: fsl,imx6sll
 
+      - description: i.MX6SLL Kobo Clara 2e Rev. A/B
+        items:
+          - enum:
+              - kobo,clara2e-a
+              - kobo,clara2e-b
+          - const: kobo,clara2e
+          - const: fsl,imx6sll
+
       - description: i.MX6SX based Boards
         items:
           - enum:
@@ -995,6 +1007,7 @@ properties:
               - menlo,mx8menlo                       # Verdin iMX8M Mini Module on i.MX8MM Menlo board
               - toradex,verdin-imx8mm-nonwifi-dahlia # Verdin iMX8M Mini Module on Dahlia
               - toradex,verdin-imx8mm-nonwifi-dev    # Verdin iMX8M Mini Module on Verdin Development Board
+              - toradex,verdin-imx8mm-nonwifi-ivy    # Verdin iMX8M Mini Module on Ivy
               - toradex,verdin-imx8mm-nonwifi-mallow # Verdin iMX8M Mini Module on Mallow
               - toradex,verdin-imx8mm-nonwifi-yavia  # Verdin iMX8M Mini Module on Yavia
           - const: toradex,verdin-imx8mm-nonwifi     # Verdin iMX8M Mini Module without Wi-Fi / BT
@@ -1006,6 +1019,7 @@ properties:
           - enum:
               - toradex,verdin-imx8mm-wifi-dahlia # Verdin iMX8M Mini Wi-Fi / BT Module on Dahlia
               - toradex,verdin-imx8mm-wifi-dev    # Verdin iMX8M Mini Wi-Fi / BT M. on Verdin Development B.
+              - toradex,verdin-imx8mm-wifi-ivy    # Verdin iMX8M Mini Wi-Fi / BT Module on Ivy
               - toradex,verdin-imx8mm-wifi-mallow # Verdin iMX8M Mini Wi-Fi / BT Module on Mallow
               - toradex,verdin-imx8mm-wifi-yavia  # Verdin iMX8M Mini Wi-Fi / BT Module on Yavia
           - const: toradex,verdin-imx8mm-wifi     # Verdin iMX8M Mini Wi-Fi / BT Module
@@ -1082,12 +1096,14 @@ properties:
               - gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
               - gateworks,imx8mp-gw74xx   # i.MX8MP Gateworks Board
               - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board
+              - gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board
               - skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel
               - skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel
               - skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel
               - toradex,verdin-imx8mp     # Verdin iMX8M Plus Modules
               - toradex,verdin-imx8mp-nonwifi  # Verdin iMX8M Plus Modules without Wi-Fi / BT
               - toradex,verdin-imx8mp-wifi  # Verdin iMX8M Plus Wi-Fi / BT Modules
+              - ysoft,imx8mp-iota2-lumpy  # Y Soft i.MX8MP IOTA2 Lumpy Board
           - const: fsl,imx8mp
 
       - description: Avnet (MSC Branded) Boards with SM2S i.MX8M Plus Modules
@@ -1097,11 +1113,19 @@ properties:
           - const: avnet,sm2s-imx8mp              # SM2S-IMX8PLUS SoM
           - const: fsl,imx8mp
 
+      - description: Boundary Device Nitrogen8MP Universal SMARC Carrier Board
+        items:
+          - const: boundary,imx8mp-nitrogen-smarc-universal-board
+          - const: boundary,imx8mp-nitrogen-smarc-som
+          - const: fsl,imx8mp
+
       - description: i.MX8MP DHCOM based Boards
         items:
           - enum:
+              - dh,imx8mp-dhcom-drc02        # i.MX8MP DHCOM SoM on DRC02 board
               - dh,imx8mp-dhcom-pdk2         # i.MX8MP DHCOM SoM on PDK2 board
               - dh,imx8mp-dhcom-pdk3         # i.MX8MP DHCOM SoM on PDK3 board
+              - dh,imx8mp-dhcom-picoitx      # i.MX8MP DHCOM SoM on PicoITX board
           - const: dh,imx8mp-dhcom-som       # i.MX8MP DHCOM SoM
           - const: fsl,imx8mp
 
@@ -1112,6 +1136,19 @@ properties:
           - const: engicam,icore-mx8mp             # i.MX8MP Engicam i.Core MX8M Plus SoM
           - const: fsl,imx8mp
 
+      - description: Kontron i.MX8MP OSM-S SoM based Boards
+        items:
+          - const: kontron,imx8mp-bl-osm-s  # Kontron BL i.MX8MP OSM-S Board
+          - const: kontron,imx8mp-osm-s     # Kontron i.MX8MP OSM-S SoM
+          - const: fsl,imx8mp
+
+      - description: Kontron i.MX8MP SMARC based Boards
+        items:
+          - const: kontron,imx8mp-smarc-eval-carrier  # Kontron i.MX8MP SMARC Eval Carrier
+          - const: kontron,imx8mp-smarc               # Kontron i.MX8MP SMARC Module
+          - const: kontron,imx8mp-osm-s               # Kontron i.MX8MP OSM-S SoM
+          - const: fsl,imx8mp
+
       - description: PHYTEC phyCORE-i.MX8MP SoM based boards
         items:
           - const: phytec,imx8mp-phyboard-pollux-rdk # phyBOARD-Pollux RDK
@@ -1137,6 +1174,7 @@ properties:
           - enum:
               - toradex,verdin-imx8mp-nonwifi-dahlia # Verdin iMX8M Plus Module on Dahlia
               - toradex,verdin-imx8mp-nonwifi-dev    # Verdin iMX8M Plus Module on Verdin Development Board
+              - toradex,verdin-imx8mp-nonwifi-ivy    # Verdin iMX8M Plus Module on Ivy
               - toradex,verdin-imx8mp-nonwifi-mallow # Verdin iMX8M Plus Module on Mallow
               - toradex,verdin-imx8mp-nonwifi-yavia  # Verdin iMX8M Plus Module on Yavia
           - const: toradex,verdin-imx8mp-nonwifi     # Verdin iMX8M Plus Module without Wi-Fi / BT
@@ -1148,6 +1186,7 @@ properties:
           - enum:
               - toradex,verdin-imx8mp-wifi-dahlia # Verdin iMX8M Plus Wi-Fi / BT Module on Dahlia
               - toradex,verdin-imx8mp-wifi-dev    # Verdin iMX8M Plus Wi-Fi / BT M. on Verdin Development B.
+              - toradex,verdin-imx8mp-wifi-ivy    # Verdin iMX8M Plus Wi-Fi / BT Module on Ivy
               - toradex,verdin-imx8mp-wifi-mallow # Verdin iMX8M Plus Wi-Fi / BT Module on Mallow
               - toradex,verdin-imx8mp-wifi-yavia  # Verdin iMX8M Plus Wi-Fi / BT Module on Yavia
           - const: toradex,verdin-imx8mp-wifi     # Verdin iMX8M Plus Wi-Fi / BT Module

Bindings/arm/mediatek/mediatek,mmsys.yaml

@@ -93,6 +93,34 @@ properties:
   '#reset-cells':
     const: 1
 
+  port:
+    $ref: /schemas/graph.yaml#/properties/port
+    description:
+      Output port node. This port connects the MMSYS/VDOSYS output to
+      the first component of one display pipeline, for example one of
+      the available OVL or RDMA blocks.
+      Some MediaTek SoCs support multiple display outputs per MMSYS.
+    properties:
+      endpoint@0:
+        $ref: /schemas/graph.yaml#/properties/endpoint
+        description: Output to the primary display pipeline
+
+      endpoint@1:
+        $ref: /schemas/graph.yaml#/properties/endpoint
+        description: Output to the secondary display pipeline
+
+      endpoint@2:
+        $ref: /schemas/graph.yaml#/properties/endpoint
+        description: Output to the tertiary display pipeline
+
+    anyOf:
+      - required:
+          - endpoint@0
+      - required:
+          - endpoint@1
+      - required:
+          - endpoint@2
+
 required:
   - compatible
   - reg

Bindings/arm/pmu.yaml

@@ -74,6 +74,7 @@ properties:
           - qcom,krait-pmu
           - qcom,scorpion-pmu
           - qcom,scorpion-mp-pmu
+          - samsung,mongoose-pmu
 
   interrupts:
     # Don't know how many CPUs, so no constraints to specify

Bindings/arm/qcom.yaml

@@ -45,6 +45,7 @@ description: |
         qcs8550
         qcm2290
         qcm6490
+        qcs9100
         qdu1000
         qrb2210
         qrb4210
@@ -76,6 +77,7 @@ description: |
         sm6375
         sm7125
         sm7225
+        sm7325
         sm8150
         sm8250
         sm8350
@@ -821,6 +823,7 @@ properties:
       - items:
           - enum:
               - lenovo,thinkpad-x13s
+              - microsoft,arcata
               - qcom,sc8280xp-crd
               - qcom,sc8280xp-qrd
           - const: qcom,sc8280xp
@@ -912,6 +915,13 @@ properties:
               - qcom,sa8775p-ride-r3
           - const: qcom,sa8775p
 
+      - items:
+          - enum:
+              - qcom,qcs9100-ride
+              - qcom,qcs9100-ride-r3
+          - const: qcom,qcs9100
+          - const: qcom,sa8775p
+
       - items:
           - enum:
               - google,cheza
@@ -989,6 +999,11 @@ properties:
               - fairphone,fp4
           - const: qcom,sm7225
 
+      - items:
+          - enum:
+              - nothing,spacewar
+          - const: qcom,sm7325
+
       - items:
           - enum:
               - microsoft,surface-duo
@@ -1058,6 +1073,7 @@ properties:
       - items:
           - enum:
               - asus,vivobook-s15
+              - dell,xps13-9345
               - lenovo,yoga-slim7x
               - microsoft,romulus13
               - microsoft,romulus15

Bindings/arm/rockchip.yaml

@@ -49,11 +49,23 @@ properties:
               - anbernic,rg-arc-s
           - const: rockchip,rk3566
 
+      - description: ArmSoM Sige5 board
+        items:
+          - const: armsom,sige5
+          - const: rockchip,rk3576
+
       - description: ArmSoM Sige7 board
         items:
           - const: armsom,sige7
           - const: rockchip,rk3588
 
+      - description: ArmSoM LM7 SoM
+        items:
+          - enum:
+              - armsom,w3
+          - const: armsom,lm7
+          - const: rockchip,rk3588
+
       - description: Asus Tinker board
         items:
           - const: asus,rk3288-tinker
@@ -232,6 +244,11 @@ properties:
               - friendlyarm,nanopi-r2s-plus
           - const: rockchip,rk3328
 
+      - description: FriendlyElec NanoPi R3S
+        items:
+          - const: friendlyarm,nanopi-r3s
+          - const: rockchip,rk3566
+
       - description: FriendlyElec NanoPi4 series boards
         items:
           - enum:
@@ -760,6 +777,7 @@ properties:
         items:
           - enum:
               - powkiddy,rgb10max3
+              - powkiddy,rgb20sx
               - powkiddy,rgb30
               - powkiddy,rk2023
               - powkiddy,x55
@@ -789,6 +807,11 @@ properties:
           - const: radxa,cm3i
           - const: rockchip,rk3568
 
+      - description: Radxa E20C
+        items:
+          - const: radxa,e20c
+          - const: rockchip,rk3528
+
       - description: Radxa Rock
         items:
           - const: radxa,rock
@@ -872,6 +895,11 @@ properties:
           - const: radxa,rock-5b
           - const: rockchip,rk3588
 
+      - description: Radxa ROCK 5C
+        items:
+          - const: radxa,rock-5c
+          - const: rockchip,rk3588s
+
       - description: Radxa ROCK S0
         items:
           - const: radxa,rock-s0
@@ -884,6 +912,11 @@ properties:
               - radxa,zero-3w
           - const: rockchip,rk3566
 
+      - description: Relfor SAIB board
+        items:
+          - const: relfor,saib
+          - const: rockchip,rv1109
+
       - description: Rikomagic MK808 v1
         items:
           - const: rikomagic,mk808
@@ -978,6 +1011,11 @@ properties:
           - const: rockchip,rk3588-evb1-v10
           - const: rockchip,rk3588
 
+      - description: Rockchip RK3588S Evaluation board
+        items:
+          - const: rockchip,rk3588s-evb1-v10
+          - const: rockchip,rk3588s
+
       - description: Rockchip RV1108 Evaluation board
         items:
           - const: rockchip,rv1108-evb
@@ -1051,7 +1089,9 @@ properties:
 
       - description: Xunlong Orange Pi 5
         items:
-          - const: xunlong,orangepi-5
+          - enum:
+              - xunlong,orangepi-5
+              - xunlong,orangepi-5b
           - const: rockchip,rk3588s
 
       - description: Zkmagic A95X Z2
@@ -1069,6 +1109,11 @@ properties:
           - const: rockchip,rk3568-evb1-v10
           - const: rockchip,rk3568
 
+      - description: Sinovoip RK3308 Banana Pi P2 Pro
+        items:
+          - const: sinovoip,rk3308-bpi-p2pro
+          - const: rockchip,rk3308
+
       - description: Sinovoip RK3568 Banana Pi R2 Pro
         items:
           - const: sinovoip,rk3568-bpi-r2pro

Bindings/arm/samsung/samsung-boards.yaml

@@ -224,6 +224,24 @@ properties:
               - winlink,e850-96                 # WinLink E850-96
           - const: samsung,exynos850
 
+      - description: Exynos8895 based boards
+        items:
+          - enum:
+              - samsung,dreamlte                # Samsung Galaxy S8 (SM-G950F)
+          - const: samsung,exynos8895
+
+      - description: Exynos9810 based boards
+        items:
+          - enum:
+              - samsung,starlte                 # Samsung Galaxy S9 (SM-G960F)
+          - const: samsung,exynos9810
+
+      - description: Exynos990 based boards
+        items:
+          - enum:
+              - samsung,c1s                     # Samsung Galaxy Note20 5G (SM-N981B)
+          - const: samsung,exynos990
+
       - description: Exynos Auto v9 based boards
         items:
           - enum:

Bindings/arm/sunxi.yaml

@@ -846,6 +846,12 @@ properties:
           - const: allwinner,sun50i-h64
           - const: allwinner,sun50i-a64
 
+      - description: RerVision A33-Vstar (with A33-Core1 SoM)
+        items:
+          - const: rervision,a33-vstar
+          - const: rervision,a33-core1
+          - const: allwinner,sun8i-a33
+
       - description: RerVision H3-DVK
         items:
           - const: rervision,h3-dvk

Bindings/arm/tegra.yaml

@@ -217,6 +217,11 @@ properties:
           - const: nvidia,p3737-0000+p3701-0000
           - const: nvidia,p3701-0000
           - const: nvidia,tegra234
+      - description: Jetson AGX Orin Developer Kit with Industrial Module
+        items:
+          - const: nvidia,p3737-0000+p3701-0008
+          - const: nvidia,p3701-0008
+          - const: nvidia,tegra234
       - description: NVIDIA IGX Orin Development Kit
         items:
           - const: nvidia,p3740-0002+p3701-0008

Bindings/arm/ti/k3.yaml

@@ -56,6 +56,7 @@ properties:
           - enum:
               - toradex,verdin-am62-nonwifi-dahlia # Verdin AM62 Module on Dahlia
               - toradex,verdin-am62-nonwifi-dev    # Verdin AM62 Module on Verdin Development Board
+              - toradex,verdin-am62-nonwifi-ivy    # Verdin AM62 Module on Ivy
               - toradex,verdin-am62-nonwifi-mallow # Verdin AM62 Module on Mallow
               - toradex,verdin-am62-nonwifi-yavia  # Verdin AM62 Module on Yavia
           - const: toradex,verdin-am62-nonwifi     # Verdin AM62 Module without Wi-Fi / BT
@@ -67,6 +68,7 @@ properties:
           - enum:
               - toradex,verdin-am62-wifi-dahlia # Verdin AM62 Wi-Fi / BT Module on Dahlia
               - toradex,verdin-am62-wifi-dev    # Verdin AM62 Wi-Fi / BT M. on Verdin Development B.
+              - toradex,verdin-am62-wifi-ivy    # Verdin AM62 Wi-Fi / BT Module on Ivy
               - toradex,verdin-am62-wifi-mallow # Verdin AM62 Wi-Fi / BT Module on Mallow
               - toradex,verdin-am62-wifi-yavia  # Verdin AM62 Wi-Fi / BT Module on Yavia
           - const: toradex,verdin-am62-wifi     # Verdin AM62 Wi-Fi / BT Module
@@ -144,6 +146,12 @@ properties:
               - ti,j722s-evm
           - const: ti,j722s
 
+      - description: K3 J742S2 SoC
+        items:
+          - enum:
+              - ti,j742s2-evm
+          - const: ti,j742s2
+
       - description: K3 J784s4 SoC
         items:
           - enum:

Bindings/ata/ahci-platform.yaml

@@ -84,6 +84,9 @@ properties:
     minItems: 1
     maxItems: 3
 
+  iommus:
+    maxItems: 1
+
 patternProperties:
   "^sata-port@[0-9a-f]+$":
     $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port

Bindings/cache/l2c2x0.yaml

@@ -100,9 +100,8 @@ properties:
       filter. Addresses in the filter window are directed to the M1 port. Other
       addresses will go to the M0 port.
     $ref: /schemas/types.yaml#/definitions/uint32-array
-    items:
-      minItems: 2
-      maxItems: 2
+    minItems: 2
+    maxItems: 2
 
   arm,io-coherent:
     description: indicates that the system is operating in an hardware

Bindings/cache/qcom,llcc.yaml

@@ -20,8 +20,12 @@ description: |
 properties:
   compatible:
     enum:
+      - qcom,qcs615-llcc
+      - qcom,qcs8300-llcc
       - qcom,qdu1000-llcc
       - qcom,sa8775p-llcc
+      - qcom,sar1130p-llcc
+      - qcom,sar2130p-llcc
       - qcom,sc7180-llcc
       - qcom,sc7280-llcc
       - qcom,sc8180x-llcc
@@ -39,11 +43,11 @@ properties:
 
   reg:
     minItems: 2
-    maxItems: 9
+    maxItems: 10
 
   reg-names:
     minItems: 2
-    maxItems: 9
+    maxItems: 10
 
   interrupts:
     maxItems: 1
@@ -67,6 +71,33 @@ allOf:
         compatible:
           contains:
             enum:
+              - qcom,sar1130p-llcc
+              - qcom,sar2130p-llcc
+    then:
+      properties:
+        reg:
+          items:
+            - description: LLCC0 base register region
+            - description: LLCC1 base register region
+            - description: LLCC broadcast OR register region
+            - description: LLCC broadcast AND register region
+            - description: LLCC scratchpad broadcast OR register region
+            - description: LLCC scratchpad broadcast AND register region
+        reg-names:
+          items:
+            - const: llcc0_base
+            - const: llcc1_base
+            - const: llcc_broadcast_base
+            - const: llcc_broadcast_and_base
+            - const: llcc_scratchpad_broadcast_base
+            - const: llcc_scratchpad_broadcast_and_base
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,qcs615-llcc
               - qcom,sc7180-llcc
               - qcom,sm6350-llcc
     then:
@@ -134,7 +165,6 @@ allOf:
               - qcom,qdu1000-llcc
               - qcom,sc8180x-llcc
               - qcom,sc8280xp-llcc
-              - qcom,x1e80100-llcc
     then:
       properties:
         reg:
@@ -165,6 +195,40 @@ allOf:
         compatible:
           contains:
             enum:
+              - qcom,x1e80100-llcc
+    then:
+      properties:
+        reg:
+          items:
+            - description: LLCC0 base register region
+            - description: LLCC1 base register region
+            - description: LLCC2 base register region
+            - description: LLCC3 base register region
+            - description: LLCC4 base register region
+            - description: LLCC5 base register region
+            - description: LLCC6 base register region
+            - description: LLCC7 base register region
+            - description: LLCC broadcast base register region
+            - description: LLCC broadcast AND register region
+        reg-names:
+          items:
+            - const: llcc0_base
+            - const: llcc1_base
+            - const: llcc2_base
+            - const: llcc3_base
+            - const: llcc4_base
+            - const: llcc5_base
+            - const: llcc6_base
+            - const: llcc7_base
+            - const: llcc_broadcast_base
+            - const: llcc_broadcast_and_base
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,qcs8300-llcc
               - qcom,sdm845-llcc
               - qcom,sm8150-llcc
               - qcom,sm8250-llcc

Bindings/clock/actions,owl-cmu.txt

@@ -1,52 +0,0 @@
-* Actions Semi Owl Clock Management Unit (CMU)
-
-The Actions Semi Owl Clock Management Unit generates and supplies clock
-to various controllers within the SoC. The clock binding described here is
-applicable to S900, S700 and S500 SoC's.
-
-Required Properties:
-
-- compatible: should be one of the following,
-	"actions,s900-cmu"
-	"actions,s700-cmu"
-	"actions,s500-cmu"
-- reg: physical base address of the controller and length of memory mapped
-  region.
-- clocks: Reference to the parent clocks ("hosc", "losc")
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Each clock is assigned an identifier, and client nodes can use this identifier
-to specify the clock which they consume.
-
-All available clocks are defined as preprocessor macros in corresponding
-dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h or
-actions,s500-cmu.h header and can be used in device tree sources.
-
-External clocks:
-
-The hosc clock used as input for the plls is generated outside the SoC. It is
-expected that it is defined using standard clock bindings as "hosc".
-
-Actions Semi S900 CMU also requires one more clock:
- - "losc" - internal low frequency oscillator
-
-Example: Clock Management Unit node:
-
-        cmu: clock-controller@e0160000 {
-                compatible = "actions,s900-cmu";
-                reg = <0x0 0xe0160000 0x0 0x1000>;
-                clocks = <&hosc>, <&losc>;
-                #clock-cells = <1>;
-                #reset-cells = <1>;
-        };
-
-Example: UART controller node that consumes clock generated by the clock
-management unit:
-
-        uart: serial@e012a000 {
-                compatible = "actions,s900-uart", "actions,owl-uart";
-                reg = <0x0 0xe012a000 0x0 0x2000>;
-                interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cmu CLK_UART5>;
-        };

Bindings/clock/actions,owl-cmu.yaml

@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/actions,owl-cmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Actions Semi Owl Clock Management Unit (CMU)
+
+maintainers:
+  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description: |
+  The Actions Semi Owl Clock Management Unit generates and supplies clock
+  to various controllers within the SoC.
+
+  See also:
+    include/dt-bindings/clock/actions,s500-cmu.h
+    include/dt-bindings/clock/actions,s700-cmu.h
+    include/dt-bindings/clock/actions,s900-cmu.h
+
+properties:
+  compatible:
+    enum:
+      - actions,s500-cmu
+      - actions,s700-cmu
+      - actions,s900-cmu
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Host oscillator source
+      - description: Internal low frequency oscillator source
+
+  "#clock-cells":
+    const: 1
+
+  "#reset-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - "#clock-cells"
+  - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@e0160000 {
+        compatible = "actions,s900-cmu";
+        reg = <0xe0160000 0x1000>;
+        clocks = <&hosc>, <&losc>;
+        #clock-cells = <1>;
+        #reset-cells = <1>;
+    };
+...

Bindings/clock/adi,axi-clkgen.yaml

@@ -26,9 +26,21 @@ properties:
     description:
       Specifies the reference clock(s) from which the output frequency is
       derived. This must either reference one clock if only the first clock
-      input is connected or two if both clock inputs are connected.
-    minItems: 1
-    maxItems: 2
+      input is connected or two if both clock inputs are connected. The last
+      clock is the AXI bus clock that needs to be enabled so we can access the
+      core registers.
+    minItems: 2
+    maxItems: 3
+
+  clock-names:
+    oneOf:
+      - items:
+          - const: clkin1
+          - const: s_axi_aclk
+      - items:
+          - const: clkin1
+          - const: clkin2
+          - const: s_axi_aclk
 
   '#clock-cells':
     const: 0
@@ -40,6 +52,7 @@ required:
   - compatible
   - reg
   - clocks
+  - clock-names
   - '#clock-cells'
 
 additionalProperties: false
@@ -50,5 +63,6 @@ examples:
       compatible = "adi,axi-clkgen-2.00.a";
       #clock-cells = <0>;
       reg = <0xff000000 0x1000>;
-      clocks = <&osc 1>;
+      clocks = <&osc 1>, <&clkc 15>;
+      clock-names = "clkin1", "s_axi_aclk";
     };

Bindings/clock/airoha,en7523-scu.yaml

@@ -34,8 +34,10 @@ properties:
           - airoha,en7581-scu
 
   reg:
-    minItems: 2
-    maxItems: 4
+    items:
+      - description: scu base address
+      - description: misc scu base address
+    minItems: 1
 
   "#clock-cells":
     description:
@@ -60,9 +62,7 @@ allOf:
     then:
       properties:
         reg:
-          items:
-            - description: scu base address
-            - description: misc scu base address
+          minItems: 2
 
         '#reset-cells': false
 
@@ -73,11 +73,7 @@ allOf:
     then:
       properties:
         reg:
-          items:
-            - description: scu base address
-            - description: misc scu base address
-            - description: reset base address
-            - description: pb scu base address
+          maxItems: 1
 
 additionalProperties: false
 
@@ -96,12 +92,9 @@ examples:
       #address-cells = <2>;
       #size-cells = <2>;
 
-      scuclk: clock-controller@1fa20000 {
+      scuclk: clock-controller@1fb00000 {
         compatible = "airoha,en7581-scu";
-        reg = <0x0 0x1fa20000 0x0 0x400>,
-              <0x0 0x1fb00000 0x0 0x90>,
-              <0x0 0x1fb00830 0x0 0x8>,
-              <0x0 0x1fbe3400 0x0 0xfc>;
+        reg = <0x0 0x1fb00000 0x0 0x970>;
               #clock-cells = <1>;
               #reset-cells = <1>;
       };

Bindings/clock/amlogic,meson8-clkc.yaml

@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,meson8-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Controller
+
+maintainers:
+  - Neil Armstrong <neil.armstrong@linaro.org>
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - amlogic,meson8-clkc
+          - amlogic,meson8b-clkc
+      - items:
+          - const: amlogic,meson8m2-clkc
+          - const: amlogic,meson8-clkc
+
+  clocks:
+    minItems: 2
+    maxItems: 3
+
+  clock-names:
+    minItems: 2
+    items:
+      - const: xtal
+      - const: ddr_pll
+      - const: clk_32k
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - '#reset-cells'
+
+additionalProperties: false

Bindings/clock/amlogic,meson8b-clkc.txt

@@ -1,51 +0,0 @@
-* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
-
-The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
-supplies clock to various controllers within the SoC.
-
-Required Properties:
-
-- compatible: must be one of:
-	- "amlogic,meson8-clkc" for Meson8 (S802) SoCs
-	- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
-	- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-- clocks: list of clock phandles, one for each entry in clock-names
-- clock-names: should contain the following:
-  * "xtal": the 24MHz system oscillator
-  * "ddr_pll": the DDR PLL clock
-  * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN)
-
-Parent node should have the following properties :
-- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
-- reg: base address and size of the HHI system control register space.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
-used in device tree sources.
-
-Similarly a preprocessor macro for each reset line is defined in
-dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the
-device tree sources).
-
-
-Example: Clock controller node:
-
-	clkc: clock-controller {
-		compatible = "amlogic,meson8b-clkc";
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-	};
-
-
-Example: UART controller node that consumes the clock generated by the clock
-  controller:
-
-	uart_AO: serial@c81004c0 {
-		compatible = "amlogic,meson-uart";
-		reg = <0xc81004c0 0x14>;
-		interrupts = <0 90 1>;
-		clocks = <&clkc CLKID_CLK81>;
-	};

Bindings/clock/gated-fixed-clock.yaml

@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/gated-fixed-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Gated Fixed clock
+
+maintainers:
+  - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+  compatible:
+    const: gated-fixed-clock
+
+  "#clock-cells":
+    const: 0
+
+  clock-frequency: true
+
+  clock-output-names:
+    maxItems: 1
+
+  enable-gpios:
+    description:
+      Contains a single GPIO specifier for the GPIO that enables and disables
+      the oscillator.
+    maxItems: 1
+
+  vdd-supply:
+    description: handle of the regulator that provides the supply voltage
+
+required:
+  - compatible
+  - "#clock-cells"
+  - clock-frequency
+  - vdd-supply
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-1000000000 {
+      compatible = "gated-fixed-clock";
+      #clock-cells = <0>;
+      clock-frequency = <1000000000>;
+      vdd-supply = <&reg_vdd>;
+    };
+...

Bindings/clock/imx93-clock.yaml

@@ -16,6 +16,7 @@ description: |
 properties:
   compatible:
     enum:
+      - fsl,imx91-ccm
       - fsl,imx93-ccm
 
   reg:

Bindings/clock/marvell,pxa1908.yaml

@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/marvell,pxa1908.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell PXA1908 Clock Controllers
+
+maintainers:
+  - Duje Mihanović <duje.mihanovic@skole.hr>
+
+description: |
+  The PXA1908 clock subsystem generates and supplies clock to various
+  controllers within the PXA1908 SoC. The PXA1908 contains numerous clock
+  controller blocks, with the ones currently supported being APBC, APBCP, MPMU
+  and APMU roughly corresponding to internal buses.
+
+  All these clock identifiers could be found in <include/dt-bindings/marvell,pxa1908.h>.
+
+properties:
+  compatible:
+    enum:
+      - marvell,pxa1908-apbc
+      - marvell,pxa1908-apbcp
+      - marvell,pxa1908-mpmu
+      - marvell,pxa1908-apmu
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  # APMU block:
+  - |
+    clock-controller@d4282800 {
+      compatible = "marvell,pxa1908-apmu";
+      reg = <0xd4282800 0x400>;
+      #clock-cells = <1>;
+    };

Bindings/clock/mediatek,apmixedsys.yaml

@@ -12,7 +12,8 @@ maintainers:
 
 description:
   The Mediatek apmixedsys controller provides PLLs to the system.
-  The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
+  The clock values can be found in <dt-bindings/clock/mt*-clk.h>
+  and <dt-bindings/clock/mediatek,mt*-apmixedsys.h>.
 
 properties:
   compatible:
@@ -34,6 +35,7 @@ properties:
           - enum:
               - mediatek,mt2701-apmixedsys
               - mediatek,mt2712-apmixedsys
+              - mediatek,mt6735-apmixedsys
               - mediatek,mt6765-apmixedsys
               - mediatek,mt6779-apmixed
               - mediatek,mt6795-apmixedsys

Bindings/clock/mediatek,infracfg.yaml

@@ -11,9 +11,10 @@ maintainers:
 
 description:
   The Mediatek infracfg controller provides various clocks and reset outputs
-  to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,
-  and reset values in <dt-bindings/reset/mt*-reset.h> and
-  <dt-bindings/reset/mt*-resets.h>.
+  to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>
+  and <dt-bindings/clock/mediatek,mt*-infracfg.h>, and reset values in
+  <dt-bindings/reset/mt*-reset.h>, <dt-bindings/reset/mt*-resets.h> and
+  <dt-bindings/reset/mediatek,mt*-infracfg.h>.
 
 properties:
   compatible:
@@ -22,6 +23,7 @@ properties:
           - enum:
               - mediatek,mt2701-infracfg
               - mediatek,mt2712-infracfg
+              - mediatek,mt6735-infracfg
               - mediatek,mt6765-infracfg
               - mediatek,mt6795-infracfg
               - mediatek,mt6779-infracfg_ao

Bindings/clock/mediatek,pericfg.yaml

@@ -20,6 +20,7 @@ properties:
           - enum:
               - mediatek,mt2701-pericfg
               - mediatek,mt2712-pericfg
+              - mediatek,mt6735-pericfg
               - mediatek,mt6765-pericfg
               - mediatek,mt6795-pericfg
               - mediatek,mt7622-pericfg

Bindings/clock/mediatek,syscon.yaml

@@ -28,6 +28,10 @@ properties:
               - mediatek,mt2712-mfgcfg
               - mediatek,mt2712-vdecsys
               - mediatek,mt2712-vencsys
+              - mediatek,mt6735-imgsys
+              - mediatek,mt6735-mfgcfg
+              - mediatek,mt6735-vdecsys
+              - mediatek,mt6735-vencsys
               - mediatek,mt6765-camsys
               - mediatek,mt6765-imgsys
               - mediatek,mt6765-mipi0a

Bindings/clock/mediatek,topckgen.yaml

@@ -12,7 +12,8 @@ maintainers:
 
 description:
   The Mediatek topckgen controller provides various clocks to the system.
-  The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
+  The clock values can be found in <dt-bindings/clock/mt*-clk.h> and
+  <dt-bindings/clock/mediatek,mt*-topckgen.h>.
 
 properties:
   compatible:
@@ -31,6 +32,7 @@ properties:
           - enum:
               - mediatek,mt2701-topckgen
               - mediatek,mt2712-topckgen
+              - mediatek,mt6735-topckgen
               - mediatek,mt6765-topckgen
               - mediatek,mt6779-topckgen
               - mediatek,mt6795-topckgen

Bindings/clock/microchip,lan966x-gck.yaml

@@ -16,7 +16,18 @@ description: |
 
 properties:
   compatible:
-    const: microchip,lan966x-gck
+    oneOf:
+      - enum:
+          - microchip,lan966x-gck
+          - microchip,lan9691-gck
+      - items:
+          - enum:
+              - microchip,lan9698-gck
+              - microchip,lan9696-gck
+              - microchip,lan9694-gck
+              - microchip,lan9693-gck
+              - microchip,lan9692-gck
+          - const: microchip,lan9691-gck
 
   reg:
     minItems: 1

Bindings/clock/mobileye,eyeq5-clk.yaml

@@ -1,51 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/mobileye,eyeq5-clk.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Mobileye EyeQ5 clock controller
-
-description:
-  The EyeQ5 clock controller handles 10 read-only PLLs derived from the main
-  crystal clock. It also exposes one divider clock, a child of one of the PLLs.
-  Its registers live in a shared region called OLB.
-
-maintainers:
-  - Grégory Clement <gregory.clement@bootlin.com>
-  - Théo Lebrun <theo.lebrun@bootlin.com>
-  - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
-
-properties:
-  compatible:
-    const: mobileye,eyeq5-clk
-
-  reg:
-    maxItems: 2
-
-  reg-names:
-    items:
-      - const: plls
-      - const: ospi
-
-  "#clock-cells":
-    const: 1
-
-  clocks:
-    maxItems: 1
-    description:
-      Input parent clock to all PLLs. Expected to be the main crystal.
-
-  clock-names:
-    items:
-      - const: ref
-
-required:
-  - compatible
-  - reg
-  - reg-names
-  - "#clock-cells"
-  - clocks
-  - clock-names
-
-additionalProperties: false

Bindings/clock/nxp,imx95-blk-ctl.yaml

@@ -13,9 +13,10 @@ properties:
   compatible:
     items:
       - enum:
-          - nxp,imx95-lvds-csr
-          - nxp,imx95-display-csr
           - nxp,imx95-camera-csr
+          - nxp,imx95-display-csr
+          - nxp,imx95-hsio-blk-ctl
+          - nxp,imx95-lvds-csr
           - nxp,imx95-netcmix-blk-ctrl
           - nxp,imx95-vpu-csr
       - const: syscon

Bindings/clock/qcom,gcc-sm8450.yaml

@@ -17,7 +17,9 @@ description: |
 
 properties:
   compatible:
-    const: qcom,gcc-sm8450
+    enum:
+      - qcom,gcc-sm8450
+      - qcom,sm8475-gcc
 
   clocks:
     items:

Bindings/clock/qcom,ipq5332-gcc.yaml

@@ -4,31 +4,35 @@
 $id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Qualcomm Global Clock & Reset Controller on IPQ5332
+title: Qualcomm Global Clock & Reset Controller on IPQ5332 and IPQ5424
 
 maintainers:
   - Bjorn Andersson <andersson@kernel.org>
 
 description: |
   Qualcomm global clock control module provides the clocks, resets and power
-  domains on IPQ5332.
+  domains on IPQ5332 and IPQ5424.
 
-  See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h
-
-allOf:
-  - $ref: qcom,gcc.yaml#
+  See also:
+    include/dt-bindings/clock/qcom,gcc-ipq5332.h
+    include/dt-bindings/clock/qcom,gcc-ipq5424.h
 
 properties:
   compatible:
-    const: qcom,ipq5332-gcc
+    enum:
+      - qcom,ipq5332-gcc
+      - qcom,ipq5424-gcc
 
   clocks:
+    minItems: 5
     items:
       - description: Board XO clock source
       - description: Sleep clock source
       - description: PCIE 2lane PHY pipe clock source
       - description: PCIE 2lane x1 PHY pipe clock source (For second lane)
       - description: USB PCIE wrapper pipe clock source
+      - description: PCIE 2-lane PHY2 pipe clock source
+      - description: PCIE 2-lane PHY3 pipe clock source
 
   '#power-domain-cells': false
   '#interconnect-cells':
@@ -38,6 +42,29 @@ required:
   - compatible
   - clocks
 
+allOf:
+  - $ref: qcom,gcc.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: qcom,ipq5332-gcc
+    then:
+      properties:
+        clocks:
+          maxItems: 5
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: qcom,ipq5424-gcc
+    then:
+      properties:
+        clocks:
+          minItems: 7
+          maxItems: 7
+
 unevaluatedProperties: false
 
 examples:

Bindings/clock/qcom,qcs8300-gcc.yaml

@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,qcs8300-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Global Clock & Reset Controller on QCS8300
+
+maintainers:
+  - Taniya Das <quic_tdas@quicinc.com>
+  - Imran Shaik <quic_imrashai@quicinc.com>
+
+description: |
+  Qualcomm Technologies, Inc. Global clock control module provides the clocks, resets and
+  power domains on QCS8300
+
+  See also: include/dt-bindings/clock/qcom,qcs8300-gcc.h
+
+properties:
+  compatible:
+    const: qcom,qcs8300-gcc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Sleep clock source
+      - description: PCIE 0 Pipe clock source
+      - description: PCIE 1 Pipe clock source
+      - description: PCIE Phy Auxiliary clock source
+      - description: First EMAC controller reference clock
+      - description: UFS Phy Rx symbol 0 clock source
+      - description: UFS Phy Rx symbol 1 clock source
+      - description: UFS Phy Tx symbol 0 clock source
+      - description: USB3 Phy wrapper pipe clock source
+
+required:
+  - compatible
+  - clocks
+  - '#power-domain-cells'
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    clock-controller@100000 {
+      compatible = "qcom,qcs8300-gcc";
+      reg = <0x00100000 0xc7018>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&sleep_clk>,
+               <&pcie_0_pipe_clk>,
+               <&pcie_1_pipe_clk>,
+               <&pcie_phy_aux_clk>,
+               <&rxc0_ref_clk>,
+               <&ufs_phy_rx_symbol_0_clk>,
+               <&ufs_phy_rx_symbol_1_clk>,
+               <&ufs_phy_tx_symbol_0_clk>,
+               <&usb3_phy_wrapper_gcc_usb30_prim_pipe_clk>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...

Bindings/clock/qcom,rpmhcc.yaml

@@ -19,6 +19,7 @@ properties:
     enum:
       - qcom,qdu1000-rpmh-clk
       - qcom,sa8775p-rpmh-clk
+      - qcom,sar2130p-rpmh-clk
       - qcom,sc7180-rpmh-clk
       - qcom,sc7280-rpmh-clk
       - qcom,sc8180x-rpmh-clk

Bindings/clock/qcom,sa8775p-camcc.yaml

@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sa8775p-camcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Camera Clock & Reset Controller on SA8775P
+
+maintainers:
+  - Taniya Das <quic_tdas@quicinc.com>
+
+description: |
+  Qualcomm camera clock control module provides the clocks, resets and power
+  domains on SA8775p.
+
+  See also: include/dt-bindings/clock/qcom,sa8775p-camcc.h
+
+properties:
+  compatible:
+    enum:
+      - qcom,sa8775p-camcc
+
+  clocks:
+    items:
+      - description: Camera AHB clock from GCC
+      - description: Board XO source
+      - description: Board active XO source
+      - description: Sleep clock source
+
+  power-domains:
+    maxItems: 1
+    description: MMCX power domain
+
+required:
+  - compatible
+  - clocks
+  - power-domains
+  - '#power-domain-cells'
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
+    #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
+    clock-controller@ade0000 {
+      compatible = "qcom,sa8775p-camcc";
+      reg = <0x0ade0000 0x20000>;
+      clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+               <&rpmhcc RPMH_CXO_CLK>,
+               <&rpmhcc RPMH_CXO_CLK_A>,
+               <&sleep_clk>;
+      power-domains = <&rpmhpd SA8775P_MMCX>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...

Bindings/clock/qcom,sa8775p-dispcc.yaml

@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sa8775p-dispcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Clock & Reset Controller on SA8775P
+
+maintainers:
+  - Taniya Das <quic_tdas@quicinc.com>
+
+description: |
+  Qualcomm display clock control module provides the clocks, resets and power
+  domains on SA8775P.
+
+  See also: include/dt-bindings/clock/qcom,sa8775p-dispcc.h
+
+properties:
+  compatible:
+    enum:
+      - qcom,sa8775p-dispcc0
+      - qcom,sa8775p-dispcc1
+
+  clocks:
+    items:
+      - description: GCC AHB clock source
+      - description: Board XO source
+      - description: Board XO_AO source
+      - description: Sleep clock source
+      - description: Link clock from DP0 PHY
+      - description: VCO DIV clock from DP0 PHY
+      - description: Link clock from DP1 PHY
+      - description: VCO DIV clock from DP1 PHY
+      - description: Byte clock from DSI0 PHY
+      - description: Pixel clock from DSI0 PHY
+      - description: Byte clock from DSI1 PHY
+      - description: Pixel clock from DSI1 PHY
+
+  power-domains:
+    maxItems: 1
+    description: MMCX power domain
+
+required:
+  - compatible
+  - clocks
+  - power-domains
+  - '#power-domain-cells'
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
+    #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
+    clock-controller@af00000 {
+      compatible = "qcom,sa8775p-dispcc0";
+      reg = <0x0af00000 0x20000>;
+      clocks = <&gcc GCC_DISP_AHB_CLK>,
+               <&rpmhcc RPMH_CXO_CLK>,
+               <&rpmhcc RPMH_CXO_CLK_A>,
+               <&sleep_clk>,
+               <&dp_phy0 0>,
+               <&dp_phy0 1>,
+               <&dp_phy1 2>,
+               <&dp_phy1 3>,
+               <&dsi_phy0 0>,
+               <&dsi_phy0 1>,
+               <&dsi_phy1 2>,
+               <&dsi_phy1 3>;
+      power-domains = <&rpmhpd SA8775P_MMCX>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...

Bindings/clock/qcom,sa8775p-videocc.yaml

@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sa8775p-videocc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Video Clock & Reset Controller on SA8775P
+
+maintainers:
+  - Taniya Das <quic_tdas@quicinc.com>
+
+description: |
+  Qualcomm video clock control module provides the clocks, resets and power
+  domains on SA8775P.
+
+  See also: include/dt-bindings/clock/qcom,sa8775p-videocc.h
+
+properties:
+  compatible:
+    enum:
+      - qcom,sa8775p-videocc
+
+  clocks:
+    items:
+      - description: Video AHB clock from GCC
+      - description: Board XO source
+      - description: Board active XO source
+      - description: Sleep Clock source
+
+  power-domains:
+    maxItems: 1
+    description: MMCX power domain
+
+required:
+  - compatible
+  - clocks
+  - power-domains
+  - '#power-domain-cells'
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
+    #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
+    videocc: clock-controller@abf0000 {
+      compatible = "qcom,sa8775p-videocc";
+      reg = <0x0abf0000 0x10000>;
+      clocks = <&gcc GCC_VIDEO_AHB_CLK>,
+               <&rpmhcc RPMH_CXO_CLK>,
+               <&rpmhcc RPMH_CXO_CLK_A>,
+               <&sleep_clk>;
+      power-domains = <&rpmhpd SA8775P_MMCX>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...

Bindings/clock/qcom,sar2130p-gcc.yaml

@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sar2130p-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on sar2130p
+
+maintainers:
+  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+description: |
+  Qualcomm global clock control module provides the clocks, resets and
+  power domains on sar2130p.
+
+  See also: include/dt-bindings/clock/qcom,sar2130p-gcc.h
+
+properties:
+  compatible:
+    const: qcom,sar2130p-gcc
+
+  clocks:
+    items:
+      - description: XO reference clock
+      - description: Sleep clock
+      - description: PCIe 0 pipe clock
+      - description: PCIe 1 pipe clock
+      - description: Primary USB3 PHY wrapper pipe clock
+
+  protected-clocks:
+    maxItems: 240
+
+  power-domains:
+    maxItems: 1
+
+required:
+  - compatible
+  - clocks
+  - '#power-domain-cells'
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
+
+    gcc: clock-controller@100000 {
+        compatible = "qcom,sar2130p-gcc";
+        reg = <0x100000 0x1f4200>;
+        clocks = <&rpmhcc RPMH_CXO_CLK>,
+                 <&sleep_clk>,
+                 <&pcie_0_pipe_clk>,
+                 <&pcie_1_pipe_clk>,
+                 <&usb_0_ssphy>;
+        power-domains = <&rpmhpd RPMHPD_CX>;
+
+        #clock-cells = <1>;
+        #reset-cells = <1>;
+        #power-domain-cells = <1>;
+    };
+...

Bindings/clock/qcom,sm8450-camcc.yaml

@@ -26,6 +26,7 @@ properties:
     enum:
       - qcom,sc8280xp-camcc
       - qcom,sm8450-camcc
+      - qcom,sm8475-camcc
       - qcom,sm8550-camcc
       - qcom,sm8650-camcc
       - qcom,x1e80100-camcc

Bindings/clock/qcom,sm8450-dispcc.yaml

@@ -19,6 +19,7 @@ properties:
   compatible:
     enum:
       - qcom,sm8450-dispcc
+      - qcom,sm8475-dispcc
 
   clocks:
     minItems: 3

Bindings/clock/qcom,sm8450-gpucc.yaml

@@ -14,6 +14,7 @@ description: |
   domains on Qualcomm SoCs.
 
   See also::
+    include/dt-bindings/clock/qcom,sar2130p-gpucc.h
     include/dt-bindings/clock/qcom,sm4450-gpucc.h
     include/dt-bindings/clock/qcom,sm8450-gpucc.h
     include/dt-bindings/clock/qcom,sm8550-gpucc.h
@@ -24,8 +25,10 @@ description: |
 properties:
   compatible:
     enum:
+      - qcom,sar2130p-gpucc
       - qcom,sm4450-gpucc
       - qcom,sm8450-gpucc
+      - qcom,sm8475-gpucc
       - qcom,sm8550-gpucc
       - qcom,sm8650-gpucc
       - qcom,x1e80100-gpucc

Bindings/clock/qcom,sm8450-videocc.yaml

@@ -22,6 +22,7 @@ properties:
   compatible:
     enum:
       - qcom,sm8450-videocc
+      - qcom,sm8475-videocc
       - qcom,sm8550-videocc
       - qcom,sm8650-videocc
 

Bindings/clock/qcom,sm8550-dispcc.yaml

@@ -22,6 +22,7 @@ description: |
 properties:
   compatible:
     enum:
+      - qcom,sar2130p-dispcc
       - qcom,sm8550-dispcc
       - qcom,sm8650-dispcc
       - qcom,x1e80100-dispcc

Bindings/clock/qcom,sm8550-tcsr.yaml

@@ -21,6 +21,7 @@ properties:
   compatible:
     items:
       - enum:
+          - qcom,sar2130p-tcsr
           - qcom,sm8550-tcsr
           - qcom,sm8650-tcsr
           - qcom,x1e80100-tcsr

Bindings/clock/renesas,r9a08g045-vbattb.yaml

@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas Battery Backup Function (VBATTB)
+
+description:
+  Renesas VBATTB is an always on powered module (backed by battery) which
+  controls the RTC clock (VBATTCLK), tamper detection logic and a small
+  general usage memory (128B).
+
+maintainers:
+  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
+
+properties:
+  compatible:
+    const: renesas,r9a08g045-vbattb
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: tamper detector interrupt
+
+  clocks:
+    items:
+      - description: VBATTB module clock
+      - description: RTC input clock (crystal or external clock device)
+
+  clock-names:
+    items:
+      - const: bclk
+      - const: rtx
+
+  '#clock-cells':
+    const: 1
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    items:
+      - description: VBATTB module reset
+
+  quartz-load-femtofarads:
+    description: load capacitance of the on board crystal
+    enum: [ 4000, 7000, 9000, 12500 ]
+    default: 4000
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - '#clock-cells'
+  - power-domains
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/r9a08g045-cpg.h>
+    #include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    clock-controller@1005c000 {
+        compatible = "renesas,r9a08g045-vbattb";
+        reg = <0x1005c000 0x1000>;
+        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
+        clock-names = "bclk", "rtx";
+        assigned-clocks = <&vbattb VBATTB_MUX>;
+        assigned-clock-parents = <&vbattb VBATTB_XC>;
+        #clock-cells = <1>;
+        power-domains = <&cpg>;
+        resets = <&cpg R9A08G045_VBAT_BRESETN>;
+        quartz-load-femtofarads = <12500>;
+    };

Bindings/clock/rockchip,rk3328-cru.txt

@@ -1,58 +0,0 @@
-* Rockchip RK3328 Clock and Reset Unit
-
-The RK3328 clock controller generates and supplies clock to various
-controllers within the SoC and also implements a reset controller for SoC
-peripherals.
-
-Required Properties:
-
-- compatible: should be "rockchip,rk3328-cru"
-- reg: physical base address of the controller and length of memory mapped
-  region.
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Optional Properties:
-
-- rockchip,grf: phandle to the syscon managing the "general register files"
-  If missing pll rates are not changeable, due to the missing pll lock status.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
-used in device tree sources. Similar macros exist for the reset sources in
-these files.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xin24m" - crystal input - required,
- - "clkin_i2s" - external I2S clock - optional,
- - "gmac_clkin" - external GMAC clock - optional
- - "phy_50m_out" - output clock of the pll in the mac phy
- - "hdmi_phy" - output clock of the hdmi phy pll - optional
-
-Example: Clock controller node:
-
-	cru: clock-controller@ff440000 {
-		compatible = "rockchip,rk3328-cru";
-		reg = <0x0 0xff440000 0x0 0x1000>;
-		rockchip,grf = <&grf>;
-
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-	};
-
-Example: UART controller node that consumes the clock generated by the clock
-  controller:
-
-	uart0: serial@ff120000 {
-		compatible = "snps,dw-apb-uart";
-		reg = <0xff120000 0x100>;
-		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		clocks = <&cru SCLK_UART0>;
-	};

Bindings/clock/rockchip,rk3328-cru.yaml

@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3328-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3328 Clock and Reset Unit (CRU)
+
+maintainers:
+  - Elaine Zhang <zhangqing@rock-chips.com>
+  - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+  The RK3328 clock controller generates and supplies clocks to various
+  controllers within the SoC and also implements a reset controller for SoC
+  peripherals.
+  Each clock is assigned an identifier and client nodes can use this identifier
+  to specify the clock which they consume. All available clocks are defined as
+  preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
+  used in device tree sources. Similar macros exist for the reset sources in
+  these files.
+  There are several clocks that are generated outside the SoC. It is expected
+  that they are defined using standard clock bindings with following
+  clock-output-names:
+    - "xin24m"      - crystal input                          - required,
+    - "clkin_i2s"   - external I2S clock                     - optional,
+    - "gmac_clkin"  - external GMAC clock                    - optional
+    - "phy_50m_out" - output clock of the pll in the mac phy
+    - "hdmi_phy"    - output clock of the hdmi phy pll       - optional
+
+properties:
+  compatible:
+    enum:
+      - rockchip,rk3328-cru
+
+  reg:
+    maxItems: 1
+
+  "#clock-cells":
+    const: 1
+
+  "#reset-cells":
+    const: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: xin24m
+
+  rockchip,grf:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to the syscon managing the "general register files" (GRF),
+      if missing pll rates are not changeable, due to the missing pll
+      lock status.
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+  - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    cru: clock-controller@ff440000 {
+      compatible = "rockchip,rk3328-cru";
+      reg = <0xff440000 0x1000>;
+      rockchip,grf = <&grf>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+    };

Bindings/clock/samsung,exynos8895-clock.yaml

@@ -0,0 +1,239 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos8895-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos8895 SoC clock controller
+
+maintainers:
+  - Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
+  - Chanwoo Choi <cw00.choi@samsung.com>
+  - Krzysztof Kozlowski <krzk@kernel.org>
+
+description: |
+  Exynos8895 clock controller is comprised of several CMU units, generating
+  clocks for different domains. Those CMU units are modeled as separate device
+  tree nodes, and might depend on each other. The root clock in that root tree
+  is an external clock: OSCCLK (26 MHz). This external clock must be defined
+  as a fixed-rate clock in dts.
+
+  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
+  dividers; all other clocks of function blocks (other CMUs) are usually
+  derived from CMU_TOP.
+
+  Each clock is assigned an identifier and client nodes can use this identifier
+  to specify the clock which they consume. All clocks available for usage
+  in clock consumer nodes are defined as preprocessor macros in
+  'include/dt-bindings/clock/samsung,exynos8895.h' header.
+
+properties:
+  compatible:
+    enum:
+      - samsung,exynos8895-cmu-fsys0
+      - samsung,exynos8895-cmu-fsys1
+      - samsung,exynos8895-cmu-peric0
+      - samsung,exynos8895-cmu-peric1
+      - samsung,exynos8895-cmu-peris
+      - samsung,exynos8895-cmu-top
+
+  clocks:
+    minItems: 1
+    maxItems: 16
+
+  clock-names:
+    minItems: 1
+    maxItems: 16
+
+  "#clock-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - reg
+  - "#clock-cells"
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos8895-cmu-fsys0
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CMU_FSYS0 BUS clock (from CMU_TOP)
+            - description: CMU_FSYS0 DPGTC clock (from CMU_TOP)
+            - description: CMU_FSYS0 MMC_EMBD clock (from CMU_TOP)
+            - description: CMU_FSYS0 UFS_EMBD clock (from CMU_TOP)
+            - description: CMU_FSYS0 USBDRD30 clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: bus
+            - const: dpgtc
+            - const: mmc
+            - const: ufs
+            - const: usbdrd30
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos8895-cmu-fsys1
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CMU_FSYS1 BUS clock (from CMU_TOP)
+            - description: CMU_FSYS1 PCIE clock (from CMU_TOP)
+            - description: CMU_FSYS1 UFS_CARD clock (from CMU_TOP)
+            - description: CMU_FSYS1 MMC_CARD clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: bus
+            - const: pcie
+            - const: ufs
+            - const: mmc
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos8895-cmu-peric0
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CMU_PERIC0 BUS clock (from CMU_TOP)
+            - description: CMU_PERIC0 UART_DBG clock (from CMU_TOP)
+            - description: CMU_PERIC0 USI00 clock (from CMU_TOP)
+            - description: CMU_PERIC0 USI01 clock (from CMU_TOP)
+            - description: CMU_PERIC0 USI02 clock (from CMU_TOP)
+            - description: CMU_PERIC0 USI03 clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: bus
+            - const: uart
+            - const: usi0
+            - const: usi1
+            - const: usi2
+            - const: usi3
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos8895-cmu-peric1
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CMU_PERIC1 BUS clock (from CMU_TOP)
+            - description: CMU_PERIC1 SPEEDY2 clock (from CMU_TOP)
+            - description: CMU_PERIC1 SPI_CAM0 clock (from CMU_TOP)
+            - description: CMU_PERIC1 SPI_CAM1 clock (from CMU_TOP)
+            - description: CMU_PERIC1 UART_BT clock (from CMU_TOP)
+            - description: CMU_PERIC1 USI04 clock (from CMU_TOP)
+            - description: CMU_PERIC1 USI05 clock (from CMU_TOP)
+            - description: CMU_PERIC1 USI06 clock (from CMU_TOP)
+            - description: CMU_PERIC1 USI07 clock (from CMU_TOP)
+            - description: CMU_PERIC1 USI08 clock (from CMU_TOP)
+            - description: CMU_PERIC1 USI09 clock (from CMU_TOP)
+            - description: CMU_PERIC1 USI10 clock (from CMU_TOP)
+            - description: CMU_PERIC1 USI11 clock (from CMU_TOP)
+            - description: CMU_PERIC1 USI12 clock (from CMU_TOP)
+            - description: CMU_PERIC1 USI13 clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: bus
+            - const: speedy
+            - const: cam0
+            - const: cam1
+            - const: uart
+            - const: usi4
+            - const: usi5
+            - const: usi6
+            - const: usi7
+            - const: usi8
+            - const: usi9
+            - const: usi10
+            - const: usi11
+            - const: usi12
+            - const: usi13
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos8895-cmu-peris
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CMU_PERIS BUS clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: bus
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos8895-cmu-top
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+
+        clock-names:
+          items:
+            - const: oscclk
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/samsung,exynos8895.h>
+
+    cmu_fsys1: clock-controller@11400000 {
+        compatible = "samsung,exynos8895-cmu-fsys1";
+        reg = <0x11400000 0x8000>;
+        #clock-cells = <1>;
+
+        clocks = <&oscclk>,
+                 <&cmu_top CLK_DOUT_CMU_FSYS1_BUS>,
+                 <&cmu_top CLK_DOUT_CMU_FSYS1_PCIE>,
+                 <&cmu_top CLK_DOUT_CMU_FSYS1_UFS_CARD>,
+                 <&cmu_top CLK_DOUT_CMU_FSYS1_MMC_CARD>;
+        clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";
+    };
+
+...

Bindings/clock/ti/composite.txt

@@ -16,8 +16,8 @@ merged to this clock. The component clocks shall be of one of the
 "ti,*composite*-clock" types.
 
 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/clock/ti/mux.txt
-[3] Documentation/devicetree/bindings/clock/ti/divider.txt
+[2] Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml
+[3] Documentation/devicetree/bindings/clock/ti/ti,divider-clock.yaml
 [4] Documentation/devicetree/bindings/clock/ti/gate.txt
 
 Required properties:

Bindings/clock/ti/divider.txt

@@ -1,115 +0,0 @@
-Binding for TI divider clock
-
-This binding uses the common clock binding[1].  It assumes a
-register-mapped adjustable clock rate divider that does not gate and has
-only one input clock or parent.  By default the value programmed into
-the register is one less than the actual divisor value.  E.g:
-
-register value		actual divisor value
-0			1
-1			2
-2			3
-
-This assumption may be modified by the following optional properties:
-
-ti,index-starts-at-one - valid divisor values start at 1, not the default
-of 0.  E.g:
-register value		actual divisor value
-1			1
-2			2
-3			3
-
-ti,index-power-of-two - valid divisor values are powers of two.  E.g:
-register value		actual divisor value
-0			1
-1			2
-2			4
-
-Additionally an array of valid dividers may be supplied like so:
-
-	ti,dividers = <4>, <8>, <0>, <16>;
-
-Which will map the resulting values to a divisor table by their index:
-register value		actual divisor value
-0			4
-1			8
-2			<invalid divisor, skipped>
-3			16
-
-Any zero value in this array means the corresponding bit-value is invalid
-and must not be used.
-
-The binding must also provide the register to control the divider and
-unless the divider array is provided, min and max dividers. Optionally
-the number of bits to shift that mask, if necessary. If the shift value
-is missing it is the same as supplying a zero shift.
-
-This binding can also optionally provide support to the hardware autoidle
-feature, see [2].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
-
-Required properties:
-- compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
-- #clock-cells : from common clock binding; shall be set to 0.
-- clocks : link to phandle of parent clock
-- reg : offset for register controlling adjustable divider
-
-Optional properties:
-- clock-output-names : from common clock binding.
-- ti,dividers : array of integers defining divisors
-- ti,bit-shift : number of bits to shift the divider value, defaults to 0
-- ti,min-div : min divisor for dividing the input clock rate, only
-  needed if the first divisor is offset from the default value (1)
-- ti,max-div : max divisor for dividing the input clock rate, only needed
-  if ti,dividers is not defined.
-- ti,index-starts-at-one : valid divisor programming starts at 1, not zero,
-  only valid if ti,dividers is not defined.
-- ti,index-power-of-two : valid divisor programming must be a power of two,
-  only valid if ti,dividers is not defined.
-- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock,
-  see [2]
-- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
-  see [2]
-- ti,set-rate-parent : clk_set_rate is propagated to parent
-- ti,latch-bit : latch the divider value to HW, only needed if the register
-  access requires this. As an example dra76x DPLL_GMAC H14 divider implements
-  such behavior.
-
-Examples:
-dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
-	#clock-cells = <0>;
-	compatible = "ti,divider-clock";
-	clocks = <&dpll_usb_ck>;
-	ti,max-div = <127>;
-	reg = <0x190>;
-	ti,index-starts-at-one;
-};
-
-aess_fclk: aess_fclk@4a004528 {
-	#clock-cells = <0>;
-	compatible = "ti,divider-clock";
-	clocks = <&abe_clk>;
-	ti,bit-shift = <24>;
-	reg = <0x528>;
-	ti,max-div = <2>;
-};
-
-dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
-	#clock-cells = <0>;
-	compatible = "ti,composite-divider-clock";
-	clocks = <&dpll_core_x2_ck>;
-	ti,max-div = <31>;
-	reg = <0x0134>;
-	ti,index-starts-at-one;
-};
-
-ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
-	#clock-cells = <0>;
-	compatible = "ti,composite-divider-clock";
-	clocks = <&corex2_fck>;
-	ti,bit-shift = <8>;
-	reg = <0x0a40>;
-	ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
-};

Bindings/clock/ti/interface.txt

@@ -1,55 +0,0 @@
-Binding for Texas Instruments interface clock.
-
-This binding uses the common clock binding[1]. This clock is
-quite much similar to the basic gate-clock [2], however,
-it supports a number of additional features, including
-companion clock finding (match corresponding functional gate
-clock) and hardware autoidle enable / disable.
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
-
-Required properties:
-- compatible : shall be one of:
-  "ti,omap3-interface-clock" - basic OMAP3 interface clock
-  "ti,omap3-no-wait-interface-clock" - interface clock which has no hardware
-				       capability for waiting clock to be ready
-  "ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW
-					handling
-  "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
-  "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
-  "ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling
-  "ti,omap2430-interface-clock" - interface clock with OMAP2430 specific HW
-				  handling
-- #clock-cells : from common clock binding; shall be set to 0
-- clocks : link to phandle of parent clock
-- reg : base address for the control register
-
-Optional properties:
-- clock-output-names : from common clock binding.
-- ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0)
-
-Examples:
-	aes1_ick: aes1_ick@48004a14 {
-		#clock-cells = <0>;
-		compatible = "ti,omap3-interface-clock";
-		clocks = <&security_l4_ick2>;
-		reg = <0x48004a14 0x4>;
-		ti,bit-shift = <3>;
-	};
-
-	cam_ick: cam_ick@48004f10 {
-		#clock-cells = <0>;
-		compatible = "ti,omap3-no-wait-interface-clock";
-		clocks = <&l4_ick>;
-		reg = <0x48004f10 0x4>;
-		ti,bit-shift = <0>;
-	};
-
-	ssi_ick_3430es2: ssi_ick_3430es2@48004a10 {
-		#clock-cells = <0>;
-		compatible = "ti,omap3-ssi-interface-clock";
-		clocks = <&ssi_l4_ick>;
-		reg = <0x48004a10 0x4>;
-		ti,bit-shift = <0>;
-	};

Bindings/clock/ti/mux.txt

@@ -1,78 +0,0 @@
-Binding for TI mux clock.
-
-This binding uses the common clock binding[1].  It assumes a
-register-mapped multiplexer with multiple input clock signals or
-parents, one of which can be selected as output.  This clock does not
-gate or adjust the parent rate via a divider or multiplier.
-
-By default the "clocks" property lists the parents in the same order
-as they are programmed into the register.  E.g:
-
-	clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
-
-results in programming the register as follows:
-
-register value		selected parent clock
-0			foo_clock
-1			bar_clock
-2			baz_clock
-
-Some clock controller IPs do not allow a value of zero to be programmed
-into the register, instead indexing begins at 1.  The optional property
-"index-starts-at-one" modified the scheme as follows:
-
-register value		selected clock parent
-1			foo_clock
-2			bar_clock
-3			baz_clock
-
-The binding must provide the register to control the mux. Optionally
-the number of bits to shift the control field in the register can be
-supplied. If the shift value is missing it is the same as supplying
-a zero shift.
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
-- #clock-cells : from common clock binding; shall be set to 0.
-- clocks : link phandles of parent clocks
-- reg : register offset for register controlling adjustable mux
-
-Optional properties:
-- clock-output-names : from common clock binding.
-- ti,bit-shift : number of bits to shift the bit-mask, defaults to
-  0 if not present
-- ti,index-starts-at-one : valid input select programming starts at 1, not
-  zero
-- ti,set-rate-parent : clk_set_rate is propagated to parent clock,
-  not supported by the composite-mux-clock subtype
-- ti,latch-bit : latch the mux value to HW, only needed if the register
-  access requires this. As an example, dra7x DPLL_GMAC H14 muxing
-  implements such behavior.
-
-Examples:
-
-sys_clkin_ck: sys_clkin_ck@4a306110 {
-	#clock-cells = <0>;
-	compatible = "ti,mux-clock";
-	clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
-	reg = <0x0110>;
-	ti,index-starts-at-one;
-};
-
-abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {
-	#clock-cells = <0>;
-	compatible = "ti,mux-clock";
-	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
-	ti,bit-shift = <24>;
-	reg = <0x0108>;
-};
-
-mcbsp5_mux_fck: mcbsp5_mux_fck {
-	#clock-cells = <0>;
-	compatible = "ti,composite-mux-clock";
-	clocks = <&core_96m_fck>, <&mcbsp_clks>;
-	ti,bit-shift = <4>;
-	reg = <0x02d8>;
-};

Bindings/clock/ti/ti,divider-clock.yaml

@@ -0,0 +1,193 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/ti/ti,divider-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments divider clock
+
+maintainers:
+  - Tero Kristo <kristo@kernel.org>
+
+description: |
+  This clock It assumes a register-mapped adjustable clock rate divider
+  that does not gate and has only one input clock or parent.  By default the
+  value programmed into the register is one less than the actual divisor value.
+  E.g:
+
+  register value    actual divisor value
+  0                 1
+  1                 2
+  2                 3
+
+  This assumption may be modified by the following optional properties:
+
+  ti,index-starts-at-one - valid divisor values start at 1, not the default
+  of 0.  E.g:
+  register value    actual divisor value
+  1                 1
+  2                 2
+  3                 3
+
+  ti,index-power-of-two - valid divisor values are powers of two.  E.g:
+  register value    actual divisor value
+  0                 1
+  1                 2
+  2                 4
+
+  Additionally an array of valid dividers may be supplied like so:
+
+  ti,dividers = <4>, <8>, <0>, <16>;
+
+  Which will map the resulting values to a divisor table by their index:
+  register value    actual divisor value
+  0                 4
+  1                 8
+  2                 <invalid divisor, skipped>
+  3                 16
+
+  Any zero value in this array means the corresponding bit-value is invalid
+  and must not be used.
+
+  The binding must also provide the register to control the divider and
+  unless the divider array is provided, min and max dividers. Optionally
+  the number of bits to shift that mask, if necessary. If the shift value
+  is missing it is the same as supplying a zero shift.
+
+  This binding can also optionally provide support to the hardware autoidle
+  feature, see [1].
+
+  [1] Documentation/devicetree/bindings/clock/ti/autoidle.txt
+
+properties:
+  compatible:
+    enum:
+      - ti,divider-clock
+      - ti,composite-divider-clock
+
+  "#clock-cells":
+    const: 0
+
+  clocks:
+    maxItems: 1
+
+  clock-output-names:
+    maxItems: 1
+
+  reg:
+    maxItems: 1
+
+  ti,dividers:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description:
+      array of integers defining divisors
+
+  ti,bit-shift:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      number of bits to shift the divider value
+    maximum: 31
+    default: 0
+
+  ti,min-div:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      min divisor for dividing the input clock rate, only
+      needed if the first divisor is offset from the default value (1)
+    minimum: 1
+    default: 1
+
+
+  ti,max-div:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      max divisor for dividing the input clock rate, only needed
+      if ti,dividers is not defined.
+
+  ti,index-starts-at-one:
+    type: boolean
+    description:
+      valid divisor programming starts at 1, not zero,
+      only valid if ti,dividers is not defined
+
+  ti,index-power-of-two:
+    type: boolean
+    description:
+      valid divisor programming must be a power of two,
+      only valid if ti,dividers is not defined.
+
+  ti,autoidle-shift:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      bit shift of the autoidle enable bit for the clock,
+      see [1].
+    maximum: 31
+    default: 0
+
+  ti,invert-autoidle-bit:
+    type: boolean
+    description:
+      autoidle is enabled by setting the bit to 0,
+      see [1]
+
+  ti,set-rate-parent:
+    type: boolean
+    description:
+      clk_set_rate is propagated to parent            |
+
+  ti,latch-bit:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      latch the divider value to HW, only needed if the register
+      compatible access requires this. As an example dra76x DPLL_GMAC
+      H14 divider implements such behavior.
+
+dependentSchemas:
+  ti,dividers:
+    properties:
+      ti,min-div: false
+      ti,max-div: false
+      ti,index-power-of-two: false
+      ti,index-starts-at-one: false
+
+required:
+  - compatible
+  - "#clock-cells"
+  - clocks
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    bus {
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      clock-controller@190 {
+        #clock-cells = <0>;
+        compatible = "ti,divider-clock";
+        clocks = <&dpll_usb_ck>;
+        ti,max-div = <127>;
+        reg = <0x190>;
+        ti,index-starts-at-one;
+      };
+
+      clock-controller@528 {
+        #clock-cells = <0>;
+        compatible = "ti,divider-clock";
+        clocks = <&abe_clk>;
+        ti,bit-shift = <24>;
+        reg = <0x528>;
+        ti,max-div = <2>;
+      };
+
+      clock-controller@a40 {
+        #clock-cells = <0>;
+        compatible = "ti,composite-divider-clock";
+        clocks = <&corex2_fck>;
+        ti,bit-shift = <8>;
+        reg = <0x0a40>;
+        ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+      };
+    };

Bindings/clock/ti/ti,interface-clock.yaml

@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/ti/ti,interface-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments interface clock.
+
+maintainers:
+  - Tero Kristo <kristo@kernel.org>
+
+description: |
+  This clock is quite much similar to the basic gate-clock[1], however,
+  it supports a number of additional features, including
+  companion clock finding (match corresponding functional gate
+  clock) and hardware autoidle enable / disable.
+
+  [1] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
+
+properties:
+  compatible:
+    enum:
+      - ti,omap3-interface-clock           # basic OMAP3 interface clock
+      - ti,omap3-no-wait-interface-clock   # interface clock which has no hardware
+                                           # capability for waiting clock to be ready
+      - ti,omap3-hsotgusb-interface-clock  # interface clock with USB specific HW handling
+      - ti,omap3-dss-interface-clock       # interface clock with DSS specific HW handling
+      - ti,omap3-ssi-interface-clock       # interface clock with SSI specific HW handling
+      - ti,am35xx-interface-clock          # interface clock with AM35xx specific HW handling
+      - ti,omap2430-interface-clock        # interface clock with OMAP2430 specific HW handling
+
+  "#clock-cells":
+    const: 0
+
+  clocks:
+    maxItems: 1
+
+  clock-output-names:
+    maxItems: 1
+
+  reg:
+    maxItems: 1
+
+  ti,bit-shift:
+    description:
+      bit shift for the bit enabling/disabling the clock
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+    maximum: 31
+
+required:
+  - compatible
+  - clocks
+  - '#clock-cells'
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    bus {
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      aes1_ick: clock-controller@3 {
+        #clock-cells = <0>;
+        compatible = "ti,omap3-interface-clock";
+        clocks = <&security_l4_ick2>;
+        reg = <3>;
+      };
+    };

Bindings/clock/ti/ti,mux-clock.yaml

@@ -0,0 +1,125 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/ti/ti,mux-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments mux clock
+
+maintainers:
+  - Tero Kristo <kristo@kernel.org>
+
+description: |
+  This clock assumes a register-mapped multiplexer with multiple inpt clock
+  signals or parents, one of which can be selected as output. This clock does
+  not gate or adjust the parent rate via a divider or multiplier.
+
+  By default the "clocks" property lists the parents in the same order
+  as they are programmed into the register.  E.g:
+
+    clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
+
+  Results in programming the register as follows:
+
+  register value   selected parent clock
+  0                foo_clock
+  1                bar_clock
+  2                baz_clock
+
+  Some clock controller IPs do not allow a value of zero to be programmed
+  into the register, instead indexing begins at 1.  The optional property
+  "index-starts-at-one" modified the scheme as follows:
+
+  register value   selected clock parent
+  1                foo_clock
+  2                bar_clock
+  3                baz_clock
+
+  The binding must provide the register to control the mux. Optionally
+  the number of bits to shift the control field in the register can be
+  supplied. If the shift value is missing it is the same as supplying
+  a zero shift.
+
+properties:
+  compatible:
+    enum:
+      - ti,mux-clock
+      - ti,composite-mux-clock
+
+  "#clock-cells":
+    const: 0
+
+  clocks: true
+
+  clock-output-names:
+    maxItems: 1
+
+  reg:
+    maxItems: 1
+
+  ti,bit-shift:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Number of bits to shift the bit-mask
+    maximum: 31
+    default: 0
+
+  ti,index-starts-at-one:
+    type: boolean
+    description:
+      Valid input select programming starts at 1, not zero
+
+  ti,set-rate-parent:
+    type: boolean
+    description:
+      clk_set_rate is propagated to parent clock,
+      not supported by the composite-mux-clock subtype.
+
+  ti,latch-bit:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Latch the mux value to HW, only needed if the register
+      access requires this. As an example, dra7x DPLL_GMAC H14 muxing
+      implements such behavior.
+    maximum: 31
+
+if:
+  properties:
+    compatible:
+      contains:
+        const: ti,composite-mux-clock
+then:
+  properties:
+    ti,set-rate-parent: false
+
+required:
+  - compatible
+  - "#clock-cells"
+  - clocks
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    bus {
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      clock-controller@110 {
+        compatible = "ti,mux-clock";
+        reg = <0x0110>;
+        #clock-cells = <0>;
+        clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>;
+        ti,index-starts-at-one;
+        ti,set-rate-parent;
+      };
+
+      clock-controller@120 {
+        compatible = "ti,composite-mux-clock";
+        reg = <0x0120>;
+        #clock-cells = <0>;
+        clocks = <&core_96m_fck>, <&mcbsp_clks>;
+        ti,bit-shift = <4>;
+      };
+    };

Bindings/clock/xlnx,clocking-wizard.yaml

@@ -39,6 +39,11 @@ properties:
       - const: clk_in1
       - const: s_axi_aclk
 
+  xlnx,static-config:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Indicate whether the core has been configured without support for dynamic
+      runtime reconfguration of the clocking primitive MMCM/PLL.
 
   xlnx,speed-grade:
     $ref: /schemas/types.yaml#/definitions/uint32
@@ -70,6 +75,7 @@ examples:
         compatible = "xlnx,clocking-wizard";
         reg = <0xb0000000 0x10000>;
         #clock-cells = <1>;
+        xlnx,static-config;
         xlnx,speed-grade = <1>;
         xlnx,nr-outputs = <6>;
         clock-names = "clk_in1", "s_axi_aclk";

Bindings/connector/usb-connector.yaml

@@ -253,6 +253,46 @@ properties:
 
     additionalProperties: false
 
+  sink-wait-cap-time-ms:
+    description: Represents the max time in ms that USB Type-C port (in sink
+      role) should wait for the port partner (source role) to send source caps.
+      SinkWaitCap timer starts when port in sink role attaches to the source.
+      This timer will stop when sink receives PD source cap advertisement before
+      timeout in which case it'll move to capability negotiation stage. A
+      timeout leads to a hard reset message by the port.
+    minimum: 310
+    maximum: 620
+    default: 310
+
+  ps-source-off-time-ms:
+    description: Represents the max time in ms that a DRP in source role should
+      take to turn off power after the PsSourceOff timer starts. PsSourceOff
+      timer starts when a sink's PHY layer receives EOP of the GoodCRC message
+      (corresponding to an Accept message sent in response to a PR_Swap or a
+      FR_Swap request). This timer stops when last bit of GoodCRC EOP
+      corresponding to the received PS_RDY message is transmitted by the PHY
+      layer. A timeout shall lead to error recovery in the type-c port.
+    minimum: 750
+    maximum: 920
+    default: 920
+
+  cc-debounce-time-ms:
+    description: Represents the max time in ms that a port shall wait to
+      determine if it's attached to a partner.
+    minimum: 100
+    maximum: 200
+    default: 200
+
+  sink-bc12-completion-time-ms:
+    description: Represents the max time in ms that a port in sink role takes
+      to complete Battery Charger (BC1.2) Detection. BC1.2 detection is a
+      hardware mechanism, which in some TCPC implementations, can run in
+      parallel once the Type-C connection state machine reaches the "potential
+      connect as sink" state. In TCPCs where this causes delays to respond to
+      the incoming PD messages, sink-bc12-completion-time-ms is used to delay
+      PD negotiation till BC1.2 detection completes.
+    default: 0
+
 dependencies:
   sink-vdos-v1: [ sink-vdos ]
   sink-vdos: [ sink-vdos-v1 ]
@@ -380,7 +420,7 @@ examples:
     };
 
   # USB-C connector attached to a typec port controller(ptn5110), which has
-  # power delivery support and enables drp.
+  # power delivery support, explicitly defines time properties and enables drp.
   - |
     #include <dt-bindings/usb/pd.h>
     typec: ptn5110 {
@@ -393,6 +433,10 @@ examples:
             sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)
                          PDO_VAR(5000, 12000, 2000)>;
             op-sink-microwatt = <10000000>;
+            sink-wait-cap-time-ms = <465>;
+            ps-source-off-time-ms = <835>;
+            cc-debounce-time-ms = <101>;
+            sink-bc12-completion-time-ms = <500>;
         };
     };
 

Bindings/cpufreq/cpufreq-qcom-hw.yaml

@@ -23,6 +23,7 @@ properties:
           - enum:
               - qcom,qcm2290-cpufreq-hw
               - qcom,sc7180-cpufreq-hw
+              - qcom,sc8180x-cpufreq-hw
               - qcom,sdm670-cpufreq-hw
               - qcom,sdm845-cpufreq-hw
               - qcom,sm6115-cpufreq-hw
@@ -34,7 +35,9 @@ properties:
         items:
           - enum:
               - qcom,qdu1000-cpufreq-epss
+              - qcom,sa8255p-cpufreq-epss
               - qcom,sa8775p-cpufreq-epss
+              - qcom,sar2130p-cpufreq-epss
               - qcom,sc7280-cpufreq-epss
               - qcom,sc8280xp-cpufreq-epss
               - qcom,sdx75-cpufreq-epss
@@ -107,6 +110,7 @@ allOf:
           contains:
             enum:
               - qcom,qcm2290-cpufreq-hw
+              - qcom,sar2130p-cpufreq-epss
     then:
       properties:
         reg:
@@ -130,7 +134,9 @@ allOf:
           contains:
             enum:
               - qcom,qdu1000-cpufreq-epss
+              - qcom,sa8255p-cpufreq-epss
               - qcom,sc7180-cpufreq-hw
+              - qcom,sc8180x-cpufreq-hw
               - qcom,sc8280xp-cpufreq-epss
               - qcom,sdm670-cpufreq-hw
               - qcom,sdm845-cpufreq-hw

Bindings/cpufreq/qemu,virtual-cpufreq.yaml

@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cpufreq/qemu,virtual-cpufreq.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Virtual CPUFreq
+
+maintainers:
+  - David Dai <davidai@google.com>
+  - Saravana Kannan <saravanak@google.com>
+
+description:
+  Virtual CPUFreq is a virtualized driver in guest kernels that sends performance
+  selection of its vCPUs as a hint to the host through MMIO regions. Each vCPU
+  is associated with a performance domain which can be shared with other vCPUs.
+  Each performance domain has its own set of registers for performance controls.
+
+properties:
+  compatible:
+    const: qemu,virtual-cpufreq
+
+  reg:
+    maxItems: 1
+    description:
+      Address and size of region containing performance controls for each of the
+      performance domains. Regions for each performance domain is placed
+      contiguously and contain registers for controlling DVFS(Dynamic Frequency
+      and Voltage) characteristics. The size of the region is proportional to
+      total number of performance domains.
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+      #address-cells = <1>;
+      #size-cells = <1>;
+
+      cpufreq@1040000 {
+        compatible = "qemu,virtual-cpufreq";
+        reg = <0x1040000 0x2000>;
+      };
+    };

Bindings/crypto/fsl,sec-v4.0.yaml

@@ -114,8 +114,9 @@ patternProperties:
           table that specifies the PPID to LIODN mapping. Needed if the PAMU is
           used.  Value is a 12 bit value where value is a LIODN ID for this JR.
           This property is normally set by boot firmware.
-        $ref: /schemas/types.yaml#/definitions/uint32
-        maximum: 0xfff
+        $ref: /schemas/types.yaml#/definitions/uint32-array
+        items:
+          - maximum: 0xfff
 
   '^rtic@[0-9a-f]+$':
     type: object
@@ -186,8 +187,9 @@ patternProperties:
               Needed if the PAMU is used.  Value is a 12 bit value where value
               is a LIODN ID for this JR. This property is normally set by boot
               firmware.
-            $ref: /schemas/types.yaml#/definitions/uint32
-            maximum: 0xfff
+            $ref: /schemas/types.yaml#/definitions/uint32-array
+            items:
+              - maximum: 0xfff
 
           fsl,rtic-region:
             description:

Bindings/crypto/qcom-qce.yaml

@@ -44,6 +44,7 @@ properties:
 
       - items:
           - enum:
+              - qcom,sa8775p-qce
               - qcom,sc7280-qce
               - qcom,sm6350-qce
               - qcom,sm8250-qce

Bindings/display/bridge/adi,adv7533.yaml

@@ -90,7 +90,7 @@ properties:
   adi,dsi-lanes:
     description: Number of DSI data lanes connected to the DSI host.
     $ref: /schemas/types.yaml#/definitions/uint32
-    enum: [ 1, 2, 3, 4 ]
+    enum: [ 2, 3, 4 ]
 
   "#sound-dai-cells":
     const: 0

Bindings/display/bridge/ite,it6263.yaml

@@ -0,0 +1,250 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ITE IT6263 LVDS to HDMI converter
+
+maintainers:
+  - Liu Ying <victor.liu@nxp.com>
+
+description: |
+  The IT6263 is a high-performance single-chip De-SSC(De-Spread Spectrum) LVDS
+  to HDMI converter.  Combined with LVDS receiver and HDMI 1.4a transmitter,
+  the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
+  The built-in LVDS receiver can support single-link and dual-link LVDS inputs,
+  and the built-in HDMI transmitter is fully compliant with HDMI 1.4a/3D, HDCP
+  1.2 and backward compatible with DVI 1.0 specification.
+
+  The IT6263 also encodes and transmits up to 8 channels of I2S digital audio,
+  with sampling rate up to 192KHz and sample size up to 24 bits. In addition,
+  an S/PDIF input port takes in compressed audio of up to 192KHz frame rate.
+
+  The newly supported High-Bit Rate(HBR) audio by HDMI specifications v1.3 is
+  provided by the IT6263 in two interfaces: the four I2S input ports or the
+  S/PDIF input port.  With both interfaces the highest possible HBR frame rate
+  is supported at up to 768KHz.
+
+allOf:
+  - $ref: /schemas/display/lvds-dual-ports.yaml#
+
+properties:
+  compatible:
+    const: ite,it6263
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+    description: audio master clock
+
+  clock-names:
+    const: mclk
+
+  data-mapping:
+    enum:
+      - jeida-18
+      - jeida-24
+      - jeida-30
+      - vesa-24
+      - vesa-30
+
+  reset-gpios:
+    maxItems: 1
+
+  ivdd-supply:
+    description: 1.8V digital logic power
+
+  ovdd-supply:
+    description: 3.3V I/O pin power
+
+  txavcc18-supply:
+    description: 1.8V HDMI analog frontend power
+
+  txavcc33-supply:
+    description: 3.3V HDMI analog frontend power
+
+  pvcc1-supply:
+    description: 1.8V HDMI frontend core PLL power
+
+  pvcc2-supply:
+    description: 1.8V HDMI frontend filter PLL power
+
+  avcc-supply:
+    description: 3.3V LVDS frontend power
+
+  anvdd-supply:
+    description: 1.8V LVDS frontend analog power
+
+  apvdd-supply:
+    description: 1.8V LVDS frontend PLL power
+
+  "#sound-dai-cells":
+    const: 0
+
+  ite,i2s-audio-fifo-sources:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 1
+    maxItems: 4
+    items:
+      enum: [0, 1, 2, 3]
+    description:
+      Each array element indicates the pin number of an I2S serial data input
+      line which is connected to an audio FIFO, from audio FIFO0 to FIFO3.
+
+  ite,rl-channel-swap-audio-sources:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 1
+    maxItems: 4
+    uniqueItems: true
+    items:
+      enum: [0, 1, 2, 3]
+    description:
+      Each array element indicates an audio source whose right channel and left
+      channel are swapped by this converter. For I2S, the element is the pin
+      number of an I2S serial data input line. For S/PDIF, the element is always
+      0.
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0: true
+
+      port@1:
+        oneOf:
+          - required: [dual-lvds-odd-pixels]
+          - required: [dual-lvds-even-pixels]
+
+      port@2:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: video port for the HDMI output
+
+      port@3:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: sound input port
+
+    required:
+      - port@0
+      - port@2
+
+required:
+  - compatible
+  - reg
+  - data-mapping
+  - ivdd-supply
+  - ovdd-supply
+  - txavcc18-supply
+  - txavcc33-supply
+  - pvcc1-supply
+  - pvcc2-supply
+  - avcc-supply
+  - anvdd-supply
+  - apvdd-supply
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    /* single-link LVDS input */
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        hdmi@4c {
+            compatible = "ite,it6263";
+            reg = <0x4c>;
+            data-mapping = "jeida-24";
+            reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+            ivdd-supply = <&reg_buck5>;
+            ovdd-supply = <&reg_vext_3v3>;
+            txavcc18-supply = <&reg_buck5>;
+            txavcc33-supply = <&reg_vext_3v3>;
+            pvcc1-supply = <&reg_buck5>;
+            pvcc2-supply = <&reg_buck5>;
+            avcc-supply = <&reg_vext_3v3>;
+            anvdd-supply = <&reg_buck5>;
+            apvdd-supply = <&reg_buck5>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    reg = <0>;
+
+                    it6263_lvds_link1: endpoint {
+                        remote-endpoint = <&ldb_lvds_ch0>;
+                    };
+                };
+
+                port@2 {
+                    reg = <2>;
+
+                    it6263_out: endpoint {
+                        remote-endpoint = <&hdmi_in>;
+                    };
+                };
+            };
+        };
+    };
+
+  - |
+    /* dual-link LVDS input */
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        hdmi@4c {
+            compatible = "ite,it6263";
+            reg = <0x4c>;
+            data-mapping = "jeida-24";
+            reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+            ivdd-supply = <&reg_buck5>;
+            ovdd-supply = <&reg_vext_3v3>;
+            txavcc18-supply = <&reg_buck5>;
+            txavcc33-supply = <&reg_vext_3v3>;
+            pvcc1-supply = <&reg_buck5>;
+            pvcc2-supply = <&reg_buck5>;
+            avcc-supply = <&reg_vext_3v3>;
+            anvdd-supply = <&reg_buck5>;
+            apvdd-supply = <&reg_buck5>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    reg = <0>;
+                    dual-lvds-odd-pixels;
+
+                    it6263_lvds_link1_dual: endpoint {
+                        remote-endpoint = <&ldb_lvds_ch0>;
+                    };
+                };
+
+                port@1 {
+                    reg = <1>;
+                    dual-lvds-even-pixels;
+
+                    it6263_lvds_link2_dual: endpoint {
+                        remote-endpoint = <&ldb_lvds_ch1>;
+                    };
+                };
+
+                port@2 {
+                    reg = <2>;
+
+                    it6263_out_dual: endpoint {
+                        remote-endpoint = <&hdmi_in>;
+                    };
+                };
+            };
+        };
+    };

Bindings/display/bridge/sil,sii9022.yaml

@@ -81,9 +81,22 @@ properties:
 
     properties:
       port@0:
-        $ref: /schemas/graph.yaml#/properties/port
+        unevaluatedProperties: false
+        $ref: /schemas/graph.yaml#/$defs/port-base
         description: Parallel RGB input port
 
+        properties:
+          endpoint:
+            $ref: /schemas/graph.yaml#/$defs/endpoint-base
+            unevaluatedProperties: false
+
+            properties:
+              bus-width:
+                description:
+                  Endpoint bus width.
+                enum: [ 16, 18, 24 ]
+                default: 24
+
       port@1:
         $ref: /schemas/graph.yaml#/properties/port
         description: HDMI output port

Bindings/display/bridge/ti,tdp158.yaml

@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/ti,tdp158.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI TDP158 HDMI to TMDS Redriver
+
+maintainers:
+  - Arnaud Vrac <avrac@freebox.fr>
+  - Pierre-Hugues Husson <phhusson@freebox.fr>
+
+properties:
+  compatible:
+    const: ti,tdp158
+
+# The reg property is required if and only if the device is connected
+# to an I2C bus. In pin strap mode, reg must not be specified.
+  reg:
+    description: I2C address of the device
+
+# Pin 36 = Operation Enable / Reset Pin
+# OE = L: Power Down Mode
+# OE = H: Normal Operation
+# Internal weak pullup - device resets on H to L transitions
+  enable-gpios:
+    description: GPIO controlling bridge enable
+
+  vcc-supply:
+    description: Power supply 3.3V
+
+  vdd-supply:
+    description: Power supply 1.1V
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Bridge input
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Bridge output
+
+    required:
+      - port@0
+      - port@1
+
+required:
+  - compatible
+  - vcc-supply
+  - vdd-supply
+  - ports
+
+additionalProperties: false

Bindings/display/bridge/toshiba,tc358768.yaml

@@ -60,6 +60,10 @@ properties:
               data-lines:
                 $ref: /schemas/types.yaml#/definitions/uint32
                 enum: [ 16, 18, 24 ]
+                deprecated: true
+
+              bus-width:
+                enum: [ 16, 18, 24 ]
 
       port@1:
         $ref: /schemas/graph.yaml#/properties/port

Bindings/display/imx/fsl-imx-drm.txt

@@ -119,7 +119,6 @@ Optional properties:
 - interface-pix-fmt: How this display is connected to the
   display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
   and "lvds666".
-- edid: verbatim EDID data block describing attached display.
 - ddc: phandle describing the i2c bus handling the display data
   channel
 - port@[0-1]: Port nodes with endpoint definitions as defined in
@@ -131,7 +130,6 @@ example:
 
 disp0 {
 	compatible = "fsl,imx-parallel-display";
-	edid = [edid-data];
 	interface-pix-fmt = "rgb24";
 
 	port@0 {

Bindings/display/imx/ldb.txt

@@ -62,7 +62,6 @@ Required properties:
    display-timings are used instead.
 
 Optional properties (required if display-timings are used):
- - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
  - display-timings : A node that describes the display timings as defined in
    Documentation/devicetree/bindings/display/panel/display-timing.txt.
  - fsl,data-mapping : should be "spwg" or "jeida"

Bindings/display/lvds-data-mapping.yaml

@@ -26,12 +26,17 @@ description: |
   Device compatible with those specifications have been marketed under the
   FPD-Link and FlatLink brands.
 
+  This bindings also supports 30-bit data mapping compatible with JEIDA and
+  VESA.
+
 properties:
   data-mapping:
     enum:
       - jeida-18
       - jeida-24
+      - jeida-30
       - vesa-24
+      - vesa-30
     description: |
       The color signals mapping order.
 
@@ -60,6 +65,19 @@ properties:
       DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
       DATA3     ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
 
+      - "jeida-30" - 30-bit data mapping compatible with JEIDA and VESA. Data
+        are transferred as follows on 5 LVDS lanes.
+
+      Slot          0       1       2       3       4       5       6
+                ________________                         _________________
+      Clock                     \_______________________/
+                  ______  ______  ______  ______  ______  ______  ______
+      DATA0     ><__G4__><__R9__><__R8__><__R7__><__R6__><__R5__><__R4__><
+      DATA1     ><__B5__><__B4__><__G9__><__G8__><__G7__><__G6__><__G5__><
+      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B9__><__B8__><__B7__><__B6__><
+      DATA3     ><_CTL3_><__B3__><__B2__><__G3__><__G2__><__R3__><__R2__><
+      DATA4     ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
+
       - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
         Data are transferred as follows on 4 LVDS lanes.
 
@@ -72,6 +90,19 @@ properties:
       DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
       DATA3     ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
 
+      - "vesa-30" - 30-bit data mapping compatible with VESA. Data are
+        transferred as follows on 5 LVDS lanes.
+
+      Slot          0       1       2       3       4       5       6
+                ________________                         _________________
+      Clock                     \_______________________/
+                  ______  ______  ______  ______  ______  ______  ______
+      DATA0     ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
+      DATA1     ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
+      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
+      DATA3     ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
+      DATA4     ><_CTL3_><__B9__><__B8__><__G9__><__G8__><__R9__><__R8__><
+
       Control signals are mapped as follows.
 
       CTL0: HSync

Bindings/display/lvds-dual-ports.yaml

@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/lvds-dual-ports.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Dual-link LVDS Display Common Properties
+
+maintainers:
+  - Liu Ying <victor.liu@nxp.com>
+
+description: |
+  Common properties for LVDS displays with dual LVDS links. Extend LVDS display
+  common properties defined in lvds.yaml.
+
+  Dual-link LVDS displays receive odd pixels and even pixels separately from
+  the dual LVDS links. One link receives odd pixels and the other receives
+  even pixels. Some of those displays may also use only one LVDS link to
+  receive all pixels, being odd and even agnostic.
+
+allOf:
+  - $ref: lvds.yaml#
+
+properties:
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    patternProperties:
+      '^port@[01]$':
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+        description: |
+          port@0 represents the first LVDS input link.
+          port@1 represents the second LVDS input link.
+
+        properties:
+          dual-lvds-odd-pixels:
+            type: boolean
+            description: LVDS input link for odd pixels
+
+          dual-lvds-even-pixels:
+            type: boolean
+            description: LVDS input link for even pixels
+
+        oneOf:
+          - required: [dual-lvds-odd-pixels]
+          - required: [dual-lvds-even-pixels]
+          - properties:
+              dual-lvds-odd-pixels: false
+              dual-lvds-even-pixels: false
+
+    anyOf:
+      - required:
+          - port@0
+      - required:
+          - port@1
+
+required:
+  - ports
+
+additionalProperties: true
+
+...

Bindings/display/mediatek/mediatek,aal.yaml

@@ -62,6 +62,27 @@ properties:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     maxItems: 1
 
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    description:
+      Input and output ports can have multiple endpoints, each of those
+      connects to either the primary, secondary, etc, display pipeline.
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: AAL input port
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          AAL output to the next component's input, for example could be one
+          of many gamma, overdrive or other blocks.
+
+    required:
+      - port@0
+      - port@1
+
 required:
   - compatible
   - reg
@@ -89,5 +110,24 @@ examples:
            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
            clocks = <&mmsys CLK_MM_DISP_AAL>;
            mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
+
+           ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               port@0 {
+                   reg = <0>;
+                   aal0_in: endpoint {
+                       remote-endpoint = <&ccorr0_out>;
+                   };
+               };
+
+               port@1 {
+                   reg = <1>;
+                   aal0_out: endpoint {
+                       remote-endpoint = <&gamma0_in>;
+                   };
+               };
+           };
        };
     };

Bindings/display/mediatek/mediatek,ccorr.yaml

@@ -57,6 +57,27 @@ properties:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     maxItems: 1
 
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    description:
+      Input and output ports can have multiple endpoints, each of those
+      connects to either the primary, secondary, etc, display pipeline.
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: CCORR input port
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          CCORR output to the input of the next desired component in the
+          display pipeline, usually only one of the available AAL blocks.
+
+    required:
+      - port@0
+      - port@1
+
 required:
   - compatible
   - reg

Bindings/display/mediatek/mediatek,color.yaml

@@ -65,6 +65,28 @@ properties:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     maxItems: 1
 
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    description:
+      Input and output ports can have multiple endpoints, each of those
+      connects to either the primary, secondary, etc, display pipeline.
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: COLOR input port
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          COLOR output to the input of the next desired component in the
+          display pipeline, for example one of the available CCORR or AAL
+          blocks.
+
+    required:
+      - port@0
+      - port@1
+
 required:
   - compatible
   - reg

Bindings/display/mediatek/mediatek,dither.yaml

@@ -56,6 +56,28 @@ properties:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     maxItems: 1
 
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    description:
+      Input and output ports can have multiple endpoints, each of those
+      connects to either the primary, secondary, etc, display pipeline.
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: DITHER input, usually from a POSTMASK or GAMMA block.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          DITHER output to the input of the next desired component in the
+          display pipeline, for example one of the available DSC compressors,
+          DP_INTF, DSI, LVDS or others.
+
+    required:
+      - port@0
+      - port@1
+
 required:
   - compatible
   - reg

Bindings/display/mediatek/mediatek,dp.yaml

@@ -42,6 +42,9 @@ properties:
   interrupts:
     maxItems: 1
 
+  '#sound-dai-cells':
+    const: 0
+
   ports:
     $ref: /schemas/graph.yaml#/properties/ports
     properties:
@@ -85,7 +88,21 @@ required:
   - ports
   - max-linkrate-mhz
 
-additionalProperties: false
+allOf:
+  - $ref: /schemas/sound/dai-common.yaml#
+  - if:
+      not:
+        properties:
+          compatible:
+            contains:
+              enum:
+                - mediatek,mt8188-dp-tx
+                - mediatek,mt8195-dp-tx
+    then:
+      properties:
+        '#sound-dai-cells': false
+
+unevaluatedProperties: false
 
 examples:
   - |

Bindings/display/mediatek/mediatek,dpi.yaml

@@ -81,13 +81,34 @@ properties:
       Output port node. This port should be connected to the input port of an
       attached HDMI, LVDS or DisplayPort encoder chip.
 
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: DPI input port
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: DPI output to an HDMI, LVDS or DisplayPort encoder input
+
+    required:
+      - port@0
+      - port@1
+
 required:
   - compatible
   - reg
   - interrupts
   - clocks
   - clock-names
-  - port
+
+oneOf:
+  - required:
+      - port
+  - required:
+      - ports
 
 additionalProperties: false
 
@@ -96,7 +117,7 @@ examples:
     #include <dt-bindings/interrupt-controller/arm-gic.h>
     #include <dt-bindings/clock/mt8173-clk.h>
 
-    dpi0: dpi@1401d000 {
+    dpi: dpi@1401d000 {
         compatible = "mediatek,mt8173-dpi";
         reg = <0x1401d000 0x1000>;
         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;

Bindings/display/mediatek/mediatek,dsc.yaml

@@ -49,6 +49,30 @@ properties:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     maxItems: 1
 
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    description:
+      Input and output ports can have multiple endpoints, each of those
+      connects to either the primary, secondary, etc, display pipeline.
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Display Stream Compression input, usually from one of the DITHER
+          or MERGE blocks.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Display Stream Compression output to the input of the next desired
+          component in the display pipeline, for example to MERGE, DP_INTF,
+          DPI or DSI.
+
+    required:
+      - port@0
+      - port@1
+
 required:
   - compatible
   - reg

Bindings/display/mediatek/mediatek,dsi.yaml

@@ -77,6 +77,26 @@ properties:
       Output port node. This port should be connected to the input
       port of an attached DSI panel or DSI-to-eDP encoder chip.
 
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    description:
+      Input ports can have multiple endpoints, each of those connects
+      to either the primary, secondary, etc, display pipeline.
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: DSI input port, usually from DITHER, DSC or MERGE
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          DSI output to an attached DSI panel, or a DSI-to-X encoder chip
+
+    required:
+      - port@0
+      - port@1
+
 required:
   - compatible
   - reg
@@ -86,7 +106,12 @@ required:
   - clock-names
   - phys
   - phy-names
-  - port
+
+oneOf:
+  - required:
+      - port
+  - required:
+      - ports
 
 unevaluatedProperties: false
 

Bindings/display/mediatek/mediatek,ethdr.yaml

@@ -110,6 +110,28 @@ properties:
       include/dt-bindings/gce/<chip>-gce.h, mapping to the register of display
       function block.
 
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    description:
+      Input and output ports can have multiple endpoints, each of those
+      connects to either the primary, secondary, etc, display pipeline.
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: ETHDR input, usually from one of the MERGE blocks.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          ETHDR output to the input of the next desired component in the
+          display pipeline, for example one of the available MERGE blocks,
+          or others.
+
+    required:
+      - port@0
+      - port@1
+
 required:
   - compatible
   - reg

Bindings/display/mediatek/mediatek,gamma.yaml

@@ -65,6 +65,25 @@ properties:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     maxItems: 1
 
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: GAMMA input, usually from one of the AAL blocks.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          GAMMA output to the input of the next desired component in the
+          display pipeline, for example one of the available DITHER or
+          POSTMASK blocks.
+
+    required:
+      - port@0
+      - port@1
+
 required:
   - compatible
   - reg

Bindings/display/mediatek/mediatek,merge.yaml

@@ -77,6 +77,29 @@ properties:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     maxItems: 1
 
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    description:
+      Input and output ports can have multiple endpoints, each of those
+      connects to either the primary, secondary, etc, display pipeline.
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          MERGE input port, usually from DITHER, DPI, DSC, DSI, MDP_RDMA,
+          ETHDR or even from a different MERGE block
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          MERGE output to a DSC, DPI, DP_INTF, DSI, ETHDR, Write DMA, or
+          a different MERGE block, or others.
+
+    required:
+      - port@0
+      - port@1
+
   resets:
     description: reset controller
       See Documentation/devicetree/bindings/reset/reset.txt for details.

Bindings/display/mediatek/mediatek,od.yaml

@@ -38,6 +38,28 @@ properties:
     items:
       - description: OD Clock
 
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    description:
+      Input and output ports can have multiple endpoints, each of those
+      connects to either the primary, secondary, etc, display pipeline.
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: OD input port, usually from an AAL block
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          OD output to the input of the next desired component in the
+          display pipeline, for example one of the available RDMA or
+          other blocks.
+
+    required:
+      - port@0
+      - port@1
+
 required:
   - compatible
   - reg

Bindings/display/mediatek/mediatek,ovl-2l.yaml

@@ -57,6 +57,28 @@ properties:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     maxItems: 1
 
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    description:
+      Input and output ports can have multiple endpoints, each of those
+      connects to either the primary, secondary, etc, display pipeline.
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: OVL input port from MMSYS, VDOSYS or other OVLs
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          OVL output to the input of the next desired component in the
+          display pipeline, for example one of the available COLOR, RDMA
+          or WDMA blocks.
+
+    required:
+      - port@0
+      - port@1
+
 required:
   - compatible
   - reg

Bindings/display/mediatek/mediatek,ovl.yaml

@@ -75,6 +75,28 @@ properties:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     maxItems: 1
 
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    description:
+      Input and output ports can have multiple endpoints, each of those
+      connects to either the primary, secondary, etc, display pipeline.
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: OVL input port from MMSYS or one of multiple VDOSYS
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          OVL output to the input of the next desired component in the
+          display pipeline, for example one of the available COLOR, RDMA
+          or WDMA blocks.
+
+    required:
+      - port@0
+      - port@1
+
 required:
   - compatible
   - reg

Bindings/display/mediatek/mediatek,postmask.yaml

@@ -52,6 +52,27 @@ properties:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     maxItems: 1
 
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    description:
+      Input and output ports can have multiple endpoints, each of those
+      connects to either the primary, secondary, etc, display pipeline.
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: POSTMASK input port, usually from GAMMA
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          POSTMASK output to the input of the next desired component in the
+          display pipeline, for example one of the available DITHER blocks.
+
+    required:
+      - port@0
+      - port@1
+
 required:
   - compatible
   - reg

Bindings/display/mediatek/mediatek,rdma.yaml

@@ -87,6 +87,28 @@ properties:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     maxItems: 1
 
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    description:
+      Input and output ports can have multiple endpoints, each of those
+      connects to either the primary, secondary, etc, display pipeline.
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: RDMA input port, usually from MMSYS, OD or OVL
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          RDMA output to the input of the next desired component in the
+          display pipeline, for example one of the available COLOR, DPI,
+          DSI, MERGE or UFOE blocks.
+
+    required:
+      - port@0
+      - port@1
+
 required:
   - compatible
   - reg

Bindings/display/mediatek/mediatek,ufoe.yaml

@@ -43,6 +43,27 @@ properties:
     items:
       - description: UFOe Clock
 
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    description:
+      Input and output ports can have multiple endpoints, each of those
+      connects to either the primary, secondary, etc, display pipeline.
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: UFOE input, usually from one of the RDMA blocks.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          UFOE output to the input of the next desired component in the
+          display pipeline, usually one of the available DSI blocks.
+
+    required:
+      - port@0
+      - port@1
+
 required:
   - compatible
   - reg

Bindings/display/msm/dp-controller.yaml

@@ -17,6 +17,7 @@ properties:
   compatible:
     oneOf:
       - enum:
+          - qcom,sa8775p-dp
           - qcom,sc7180-dp
           - qcom,sc7280-dp
           - qcom,sc7280-edp

Bindings/display/msm/gmu.yaml

@@ -125,6 +125,7 @@ allOf:
             enum:
               - qcom,adreno-gmu-635.0
               - qcom,adreno-gmu-660.1
+              - qcom,adreno-gmu-663.0
     then:
       properties:
         reg:

Bindings/display/msm/qcom,sa8775p-mdss.yaml

@@ -0,0 +1,241 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SA87755P Display MDSS
+
+maintainers:
+  - Mahadevan <quic_mahap@quicinc.com>
+
+description:
+  SA8775P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
+  DPU display controller, DP interfaces and EDP etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+  compatible:
+    const: qcom,sa8775p-mdss
+
+  clocks:
+    items:
+      - description: Display AHB
+      - description: Display hf AXI
+      - description: Display core
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    maxItems: 3
+
+  interconnect-names:
+    maxItems: 3
+
+patternProperties:
+  "^display-controller@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+
+    properties:
+      compatible:
+        const: qcom,sa8775p-dpu
+
+  "^displayport-controller@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+
+    properties:
+      compatible:
+        items:
+          - const: qcom,sa8775p-dp
+
+required:
+  - compatible
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interconnect/qcom,icc.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
+    #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
+
+    display-subsystem@ae00000 {
+        compatible = "qcom,sa8775p-mdss";
+        reg = <0x0ae00000 0x1000>;
+        reg-names = "mdss";
+
+        interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
+                        <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>,
+                        <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>;
+        interconnect-names = "mdp0-mem",
+                             "mdp1-mem",
+                             "cpu-cfg";
+
+
+        resets = <&dispcc_core_bcr>;
+        power-domains = <&dispcc_gdsc>;
+
+        clocks = <&dispcc_ahb_clk>,
+                 <&gcc GCC_DISP_HF_AXI_CLK>,
+                 <&dispcc_mdp_clk>;
+
+        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-controller;
+        #interrupt-cells = <1>;
+
+        iommus = <&apps_smmu 0x1000 0x402>;
+
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+
+        display-controller@ae01000 {
+            compatible = "qcom,sa8775p-dpu";
+            reg = <0x0ae01000 0x8f000>,
+                  <0x0aeb0000 0x2008>;
+            reg-names = "mdp", "vbif";
+
+            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+                     <&dispcc_ahb_clk>,
+                     <&dispcc_mdp_lut_clk>,
+                     <&dispcc_mdp_clk>,
+                     <&dispcc_mdp_vsync_clk>;
+            clock-names = "nrt_bus",
+                          "iface",
+                          "lut",
+                          "core",
+                          "vsync";
+
+            assigned-clocks = <&dispcc_mdp_vsync_clk>;
+            assigned-clock-rates = <19200000>;
+
+            operating-points-v2 = <&mdss0_mdp_opp_table>;
+            power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+            interrupt-parent = <&mdss0>;
+            interrupts = <0>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    reg = <0>;
+                    dpu_intf0_out: endpoint {
+                         remote-endpoint = <&mdss0_dp0_in>;
+                    };
+                };
+            };
+
+            mdss0_mdp_opp_table: opp-table {
+                compatible = "operating-points-v2";
+
+                opp-375000000 {
+                    opp-hz = /bits/ 64 <375000000>;
+                    required-opps = <&rpmhpd_opp_svs_l1>;
+                };
+
+                opp-500000000 {
+                    opp-hz = /bits/ 64 <500000000>;
+                    required-opps = <&rpmhpd_opp_nom>;
+                };
+
+                opp-575000000 {
+                    opp-hz = /bits/ 64 <575000000>;
+                    required-opps = <&rpmhpd_opp_turbo>;
+                };
+
+                opp-650000000 {
+                    opp-hz = /bits/ 64 <650000000>;
+                    required-opps = <&rpmhpd_opp_turbo_l1>;
+                };
+            };
+        };
+
+        displayport-controller@af54000 {
+            compatible = "qcom,sa8775p-dp";
+
+            pinctrl-0 = <&dp_hot_plug_det>;
+            pinctrl-names = "default";
+
+            reg = <0xaf54000 0x104>,
+                  <0xaf54200 0x0c0>,
+                  <0xaf55000 0x770>,
+                  <0xaf56000 0x09c>;
+
+            interrupt-parent = <&mdss0>;
+            interrupts = <12>;
+
+            clocks = <&dispcc_mdss_ahb_clk>,
+                     <&dispcc_dptx0_aux_clk>,
+                     <&dispcc_dptx0_link_clk>,
+                     <&dispcc_dptx0_link_intf_clk>,
+                     <&dispcc_dptx0_pixel0_clk>;
+            clock-names = "core_iface",
+                          "core_aux",
+                          "ctrl_link",
+                          "ctrl_link_iface",
+                          "stream_pixel";
+
+            assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
+                              <&dispcc_mdss_dptx0_pixel0_clk_src>;
+            assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>;
+
+            phys = <&mdss0_edp_phy>;
+            phy-names = "dp";
+
+            operating-points-v2 = <&dp_opp_table>;
+            power-domains = <&rpmhpd SA8775P_MMCX>;
+
+            #sound-dai-cells = <0>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    reg = <0>;
+                    mdss0_dp0_in: endpoint {
+                        remote-endpoint = <&dpu_intf0_out>;
+                    };
+                };
+
+                port@1 {
+                   reg = <1>;
+                   mdss0_dp_out: endpoint { };
+                };
+            };
+
+            dp_opp_table: opp-table {
+                compatible = "operating-points-v2";
+
+                opp-160000000 {
+                    opp-hz = /bits/ 64 <160000000>;
+                    required-opps = <&rpmhpd_opp_low_svs>;
+                };
+
+                opp-270000000 {
+                    opp-hz = /bits/ 64 <270000000>;
+                    required-opps = <&rpmhpd_opp_svs>;
+                };
+
+                opp-540000000 {
+                    opp-hz = /bits/ 64 <540000000>;
+                    required-opps = <&rpmhpd_opp_svs_l1>;
+                };
+
+                opp-810000000 {
+                    opp-hz = /bits/ 64 <810000000>;
+                    required-opps = <&rpmhpd_opp_nom>;
+                };
+            };
+        };
+    };
+...

Bindings/display/msm/qcom,sc7280-dpu.yaml

@@ -7,13 +7,21 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm Display DPU on SC7280
 
 maintainers:
+  - Bjorn Andersson <andersson@kernel.org>
+  - Neil Armstrong <neil.armstrong@linaro.org>
+  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
   - Krishna Manikandan <quic_mkrishn@quicinc.com>
 
 $ref: /schemas/display/msm/dpu-common.yaml#
 
 properties:
   compatible:
-    const: qcom,sc7280-dpu
+    enum:
+      - qcom,sc7280-dpu
+      - qcom,sc8280xp-dpu
+      - qcom,sm8350-dpu
+      - qcom,sm8450-dpu
+      - qcom,sm8550-dpu
 
   reg:
     items:

Bindings/display/msm/qcom,sc8280xp-dpu.yaml

@@ -1,122 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-dpu.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm SC8280XP Display Processing Unit
-
-maintainers:
-  - Bjorn Andersson <andersson@kernel.org>
-
-description:
-  Device tree bindings for SC8280XP Display Processing Unit.
-
-$ref: /schemas/display/msm/dpu-common.yaml#
-
-properties:
-  compatible:
-    const: qcom,sc8280xp-dpu
-
-  reg:
-    items:
-      - description: Address offset and size for mdp register set
-      - description: Address offset and size for vbif register set
-
-  reg-names:
-    items:
-      - const: mdp
-      - const: vbif
-
-  clocks:
-    items:
-      - description: Display hf axi clock
-      - description: Display sf axi clock
-      - description: Display ahb clock
-      - description: Display lut clock
-      - description: Display core clock
-      - description: Display vsync clock
-
-  clock-names:
-    items:
-      - const: bus
-      - const: nrt_bus
-      - const: iface
-      - const: lut
-      - const: core
-      - const: vsync
-
-unevaluatedProperties: false
-
-examples:
-  - |
-    #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
-    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
-    #include <dt-bindings/interrupt-controller/arm-gic.h>
-    #include <dt-bindings/interconnect/qcom,sc8280xp.h>
-    #include <dt-bindings/power/qcom-rpmpd.h>
-
-    display-controller@ae01000 {
-        compatible = "qcom,sc8280xp-dpu";
-        reg = <0x0ae01000 0x8f000>,
-              <0x0aeb0000 0x2008>;
-        reg-names = "mdp", "vbif";
-
-        clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
-                 <&gcc GCC_DISP_SF_AXI_CLK>,
-                 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
-                 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
-                 <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
-                 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
-        clock-names = "bus",
-                      "nrt_bus",
-                      "iface",
-                      "lut",
-                      "core",
-                      "vsync";
-
-        assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
-                          <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
-        assigned-clock-rates = <460000000>,
-                               <19200000>;
-
-        operating-points-v2 = <&mdp_opp_table>;
-        power-domains = <&rpmhpd SC8280XP_MMCX>;
-
-        interrupt-parent = <&mdss0>;
-        interrupts = <0>;
-
-        ports {
-            #address-cells = <1>;
-            #size-cells = <0>;
-
-            port@0 {
-                reg = <0>;
-                endpoint {
-                    remote-endpoint = <&mdss0_dp0_in>;
-                };
-            };
-
-            port@4 {
-                reg = <4>;
-                endpoint {
-                    remote-endpoint = <&mdss0_dp1_in>;
-                };
-            };
-
-            port@5 {
-                reg = <5>;
-                endpoint {
-                    remote-endpoint = <&mdss0_dp3_in>;
-                };
-            };
-
-            port@6 {
-                reg = <6>;
-                endpoint {
-                    remote-endpoint = <&mdss0_dp2_in>;
-                };
-            };
-        };
-    };
-...

Bindings/display/msm/qcom,sm8150-dpu.yaml

@@ -13,7 +13,9 @@ $ref: /schemas/display/msm/dpu-common.yaml#
 
 properties:
   compatible:
-    const: qcom,sm8150-dpu
+    enum:
+      - qcom,sm8150-dpu
+      - qcom,sm8250-dpu
 
   reg:
     items:

Bindings/display/msm/qcom,sm8250-dpu.yaml

@@ -1,99 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-dpu.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm SM8250 Display DPU
-
-maintainers:
-  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-$ref: /schemas/display/msm/dpu-common.yaml#
-
-properties:
-  compatible:
-    const: qcom,sm8250-dpu
-
-  reg:
-    items:
-      - description: Address offset and size for mdp register set
-      - description: Address offset and size for vbif register set
-
-  reg-names:
-    items:
-      - const: mdp
-      - const: vbif
-
-  clocks:
-    items:
-      - description: Display ahb clock
-      - description: Display hf axi clock
-      - description: Display core clock
-      - description: Display vsync clock
-
-  clock-names:
-    items:
-      - const: iface
-      - const: bus
-      - const: core
-      - const: vsync
-
-required:
-  - compatible
-  - reg
-  - reg-names
-  - clocks
-  - clock-names
-
-unevaluatedProperties: false
-
-examples:
-  - |
-    #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
-    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
-    #include <dt-bindings/interrupt-controller/arm-gic.h>
-    #include <dt-bindings/interconnect/qcom,sm8250.h>
-    #include <dt-bindings/power/qcom,rpmhpd.h>
-
-    display-controller@ae01000 {
-        compatible = "qcom,sm8250-dpu";
-        reg = <0x0ae01000 0x8f000>,
-              <0x0aeb0000 0x2008>;
-        reg-names = "mdp", "vbif";
-
-        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
-                 <&gcc GCC_DISP_HF_AXI_CLK>,
-                 <&dispcc DISP_CC_MDSS_MDP_CLK>,
-                 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
-        clock-names = "iface", "bus", "core", "vsync";
-
-        assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
-        assigned-clock-rates = <19200000>;
-
-        operating-points-v2 = <&mdp_opp_table>;
-        power-domains = <&rpmhpd RPMHPD_MMCX>;
-
-        interrupt-parent = <&mdss>;
-        interrupts = <0>;
-
-        ports {
-            #address-cells = <1>;
-            #size-cells = <0>;
-
-            port@0 {
-                reg = <0>;
-                endpoint {
-                    remote-endpoint = <&dsi0_in>;
-                };
-            };
-
-            port@1 {
-                reg = <1>;
-                endpoint {
-                    remote-endpoint = <&dsi1_in>;
-                };
-            };
-        };
-    };
-...

Bindings/display/msm/qcom,sm8350-dpu.yaml

@@ -1,120 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm SM8350 Display DPU
-
-maintainers:
-  - Robert Foss <robert.foss@linaro.org>
-
-$ref: /schemas/display/msm/dpu-common.yaml#
-
-properties:
-  compatible:
-    const: qcom,sm8350-dpu
-
-  reg:
-    items:
-      - description: Address offset and size for mdp register set
-      - description: Address offset and size for vbif register set
-
-  reg-names:
-    items:
-      - const: mdp
-      - const: vbif
-
-  clocks:
-    items:
-      - description: Display hf axi clock
-      - description: Display sf axi clock
-      - description: Display ahb clock
-      - description: Display lut clock
-      - description: Display core clock
-      - description: Display vsync clock
-
-  clock-names:
-    items:
-      - const: bus
-      - const: nrt_bus
-      - const: iface
-      - const: lut
-      - const: core
-      - const: vsync
-
-unevaluatedProperties: false
-
-examples:
-  - |
-    #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
-    #include <dt-bindings/clock/qcom,gcc-sm8350.h>
-    #include <dt-bindings/interrupt-controller/arm-gic.h>
-    #include <dt-bindings/interconnect/qcom,sm8350.h>
-    #include <dt-bindings/power/qcom,rpmhpd.h>
-
-    display-controller@ae01000 {
-        compatible = "qcom,sm8350-dpu";
-        reg = <0x0ae01000 0x8f000>,
-              <0x0aeb0000 0x2008>;
-        reg-names = "mdp", "vbif";
-
-        clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
-                 <&gcc GCC_DISP_SF_AXI_CLK>,
-                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
-                 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
-                 <&dispcc DISP_CC_MDSS_MDP_CLK>,
-                 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
-        clock-names = "bus",
-                      "nrt_bus",
-                      "iface",
-                      "lut",
-                      "core",
-                      "vsync";
-
-        assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
-        assigned-clock-rates = <19200000>;
-
-        operating-points-v2 = <&mdp_opp_table>;
-        power-domains = <&rpmhpd RPMHPD_MMCX>;
-
-        interrupt-parent = <&mdss>;
-        interrupts = <0>;
-
-        ports {
-            #address-cells = <1>;
-            #size-cells = <0>;
-
-            port@0 {
-                reg = <0>;
-                dpu_intf1_out: endpoint {
-                    remote-endpoint = <&dsi0_in>;
-                };
-            };
-        };
-
-        mdp_opp_table: opp-table {
-            compatible = "operating-points-v2";
-
-            opp-200000000 {
-                opp-hz = /bits/ 64 <200000000>;
-                required-opps = <&rpmhpd_opp_low_svs>;
-            };
-
-            opp-300000000 {
-                opp-hz = /bits/ 64 <300000000>;
-                required-opps = <&rpmhpd_opp_svs>;
-            };
-
-            opp-345000000 {
-                opp-hz = /bits/ 64 <345000000>;
-                required-opps = <&rpmhpd_opp_svs_l1>;
-            };
-
-            opp-460000000 {
-                opp-hz = /bits/ 64 <460000000>;
-                required-opps = <&rpmhpd_opp_nom>;
-            };
-        };
-    };
-...

Bindings/display/msm/qcom,sm8450-dpu.yaml

@@ -1,139 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm SM8450 Display DPU
-
-maintainers:
-  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-$ref: /schemas/display/msm/dpu-common.yaml#
-
-properties:
-  compatible:
-    const: qcom,sm8450-dpu
-
-  reg:
-    items:
-      - description: Address offset and size for mdp register set
-      - description: Address offset and size for vbif register set
-
-  reg-names:
-    items:
-      - const: mdp
-      - const: vbif
-
-  clocks:
-    items:
-      - description: Display hf axi
-      - description: Display sf axi
-      - description: Display ahb
-      - description: Display lut
-      - description: Display core
-      - description: Display vsync
-
-  clock-names:
-    items:
-      - const: bus
-      - const: nrt_bus
-      - const: iface
-      - const: lut
-      - const: core
-      - const: vsync
-
-required:
-  - compatible
-  - reg
-  - reg-names
-  - clocks
-  - clock-names
-
-unevaluatedProperties: false
-
-examples:
-  - |
-    #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
-    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
-    #include <dt-bindings/interrupt-controller/arm-gic.h>
-    #include <dt-bindings/interconnect/qcom,sm8450.h>
-    #include <dt-bindings/power/qcom,rpmhpd.h>
-
-    display-controller@ae01000 {
-        compatible = "qcom,sm8450-dpu";
-        reg = <0x0ae01000 0x8f000>,
-              <0x0aeb0000 0x2008>;
-        reg-names = "mdp", "vbif";
-
-        clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
-                <&gcc GCC_DISP_SF_AXI_CLK>,
-                <&dispcc DISP_CC_MDSS_AHB_CLK>,
-                <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
-                <&dispcc DISP_CC_MDSS_MDP_CLK>,
-                <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
-        clock-names = "bus",
-                      "nrt_bus",
-                      "iface",
-                      "lut",
-                      "core",
-                      "vsync";
-
-        assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
-        assigned-clock-rates = <19200000>;
-
-        operating-points-v2 = <&mdp_opp_table>;
-        power-domains = <&rpmhpd RPMHPD_MMCX>;
-
-        interrupt-parent = <&mdss>;
-        interrupts = <0>;
-
-        ports {
-            #address-cells = <1>;
-            #size-cells = <0>;
-
-            port@0 {
-                reg = <0>;
-                dpu_intf1_out: endpoint {
-                    remote-endpoint = <&dsi0_in>;
-                };
-            };
-
-            port@1 {
-                reg = <1>;
-                dpu_intf2_out: endpoint {
-                    remote-endpoint = <&dsi1_in>;
-                };
-            };
-        };
-
-        mdp_opp_table: opp-table {
-            compatible = "operating-points-v2";
-
-            opp-172000000{
-                opp-hz = /bits/ 64 <172000000>;
-                required-opps = <&rpmhpd_opp_low_svs_d1>;
-            };
-
-            opp-200000000 {
-                opp-hz = /bits/ 64 <200000000>;
-                required-opps = <&rpmhpd_opp_low_svs>;
-            };
-
-            opp-325000000 {
-                opp-hz = /bits/ 64 <325000000>;
-                required-opps = <&rpmhpd_opp_svs>;
-            };
-
-            opp-375000000 {
-                opp-hz = /bits/ 64 <375000000>;
-                required-opps = <&rpmhpd_opp_svs_l1>;
-            };
-
-            opp-500000000 {
-                opp-hz = /bits/ 64 <500000000>;
-                required-opps = <&rpmhpd_opp_nom>;
-            };
-        };
-    };
-...