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mmc: dwmmc: only clear handled interrupts

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Unconditionally clearing DTO when RXDR is set leads to spurious timeouts
in FIFO mode transfers if events occur in the following order:

	mask = dwmci_readl(host, DWMCI_RINTSTS);

	// Hardware asserts DWMCI_INTMSK_DTO here

	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_DTO);

	if (mask & DWMCI_INTMSK_DTO) {
		// Unreachable as DTO is cleared without being handled!
		return 0;
	}

Only clear interrupts that we have seen and are handling so that DTO is
not missed.

Signed-off-by: John Keeping <john@metanate.com>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (Rock PI 4B)
Tested-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This commit is contained in:
John Keeping
2022-10-24 18:02:41 +09:00
committed by Jaehoon Chung
parent 359c176de5
commit 7ff2f30b63
1 changed files with 2 additions and 1 deletions
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drivers/mmc/dw_mmc.c
+2 -1
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@@ -168,7 +168,8 @@ static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
if (data->flags == MMC_DATA_READ &&
(mask & (DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO))) {
dwmci_writel(host, DWMCI_RINTSTS,
DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO);
mask & (DWMCI_INTMSK_RXDR |
DWMCI_INTMSK_DTO));
while (size) {
ret = dwmci_fifo_ready(host,
DWMCI_FIFO_EMPTY,