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Merge tag 'u-boot-imx-master-20260421' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Browse Source 
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/29880

- Convert TQMA7 boards to SPL.
- Use second Ethernet MAC also from fuse on i.MX dhelectronics boards.
- Add support for Toradex Verdin iMX95.
- Drop SPL_POWER_LEGACY from imx8m boards.
- Increase the Aquantia Ethernet PHY reset timeout.
This commit is contained in:
Tom Rini
2026-04-22 10:59:44 -06:00
parent 09297182ad 589153f607
commit 7fbed708d9
87 changed files with 5286 additions and 719 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Kconfig
+1 -1
View File
@@ -551,7 +551,7 @@ config BUILD_TARGET
default "u-boot-elf.srec" if RCAR_64
default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 && SPL
default "u-boot-with-spl.imx" if ARCH_MX6 && SPL
default "u-boot-with-spl.imx" if (ARCH_MX6 || ARCH_MX7) && SPL
default "u-boot-with-spl.kwb" if ARMADA_32BIT && SPL
default "u-boot-with-spl.sfp" if ARCH_SOCFPGA_ARRIA10
default "u-boot-with-spl.sfp" if ARCH_SOCFPGA_GEN5
arch/arm/dts/imx7d-mba7-u-boot.dtsi
+10
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@@ -0,0 +1,10 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Device Tree Source for TQ-Systems TQMa7D board on MBa7x carrier board.
*
* Copyright (C) 2024-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
* D-82229 Seefeld, Germany
* Author: Steffen Doster
*/
#include "imx7s-mba7-u-boot.dtsi"
arch/arm/dts/imx7s-mba7-u-boot.dtsi
+48
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@@ -0,0 +1,48 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Device Tree Source for TQ-Systems TQMa7S board on MBa7x carrier board.
*
* Copyright (C) 2025-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
* D-82229 Seefeld, Germany
* Author: Steffen Doster
*/
#include "imx7s-tqma7-u-boot.dtsi"
/ {
config {
u-boot,mmc-env-offset = <0x100000>;
u-boot,mmc-env-offset-redundant = <0x110000>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
};
};
&gpio4 {
/* Deassert BOOT_EN after boot to separate BOOT_CFG circuits from LCD signals */
boot-en-hog {
gpio-hog;
gpios = <3 GPIO_ACTIVE_LOW>;
output-low;
};
};
&wdog1 {
u-boot,noautostart;
timeout-sec = <60>;
};
&iomuxc {
bootph-pre-ram;
};
&pinctrl_uart6 {
bootph-pre-ram;
};
&uart6 {
bootph-pre-ram;
};
arch/arm/dts/imx7s-tqma7-u-boot.dtsi
+22
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@@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Device Tree Source for TQ-Systems TQMa7S module.
*
* Copyright (C) 2024-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
* D-82229 Seefeld, Germany
* Author: Steffen Doster
*/
#include "imx7s-u-boot.dtsi"
&soc {
bootph-pre-ram;
};
&aips1 {
bootph-pre-ram;
};
&aips3 {
bootph-pre-ram;
};
arch/arm/dts/imx8mq-evk-u-boot.dtsi
+87 -1
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@@ -2,19 +2,105 @@
#include "imx8mq-u-boot.dtsi"
&aips1 {
bootph-all;
};
&gpio2 {
bootph-pre-ram;
};
&pinctrl_i2c1 {
bootph-all;
};
&i2c1 {
bootph-all;
};
&soc {
bootph-all;
bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@8} {
bootph-all;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@8/regulators} {
bootph-all;
};
&pinctrl_uart1 {
bootph-pre-ram;
};
&uart1 {
bootph-pre-ram;
};
&usdhc1 {
bootph-pre-ram;
mmc-hs400-1_8v;
/delete-property/ vqmmc-supply;
};
&pinctrl_usdhc1 {
bootph-pre-ram;
};
&pinctrl_usdhc1_100mhz {
bootph-pre-ram;
};
&pinctrl_usdhc1_200mhz {
bootph-pre-ram;
};
&usdhc2 {
bootph-pre-ram;
sd-uhs-sdr104;
sd-uhs-ddr50;
};
&uart1 {
&pinctrl_usdhc2 {
bootph-pre-ram;
};
&pinctrl_usdhc2_100mhz {
bootph-pre-ram;
};
&pinctrl_usdhc2_200mhz {
bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
bootph-pre-ram;
};
&pinctrl_reg_usdhc2 {
bootph-pre-ram;
};
&reg_usdhc2_vmmc {
bootph-pre-ram;
};
#ifdef CONFIG_FSL_CAAM
&crypto {
bootph-pre-ram;
};
&sec_jr0 {
bootph-pre-ram;
};
&sec_jr1 {
bootph-pre-ram;
};
&sec_jr2 {
bootph-pre-ram;
};
#endif
arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi
+64
View File
@@ -2,26 +2,90 @@
#include "imx8mq-u-boot.dtsi"
&aips1 {
bootph-all;
};
&gpio2 {
bootph-pre-ram;
};
&pinctrl_i2c1 {
bootph-all;
};
&i2c1 {
bootph-all;
};
&soc {
bootph-all;
bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@8} {
bootph-all;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@8/regulators} {
bootph-all;
};
&pinctrl_uart1 {
bootph-pre-ram;
};
&uart1 {
bootph-pre-ram;
};
&usdhc1 {
bootph-pre-ram;
mmc-hs400-1_8v;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
};
&pinctrl_usdhc1 {
bootph-pre-ram;
};
&usdhc2 {
bootph-pre-ram;
sd-uhs-sdr104;
sd-uhs-ddr50;
};
&pinctrl_usdhc2 {
bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
bootph-pre-ram;
};
&pinctrl_reg_usdhc2 {
bootph-pre-ram;
};
&reg_usdhc2_vmmc {
bootph-pre-ram;
};
&uart1 {
bootph-pre-ram;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
};
&uart2 {
bootph-pre-ram;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
};
&uart3 {
bootph-pre-ram;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
};
arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
+1 -1
View File
@@ -10,7 +10,7 @@
bootph-pre-ram;
};
&binman_imx_spl {
&binman {
section {
signed-hdmi-imx8m {
filename = "signed_dp_imx8m.bin";
arch/arm/dts/imx8mq-phanbell-u-boot.dtsi
+41
View File
@@ -2,7 +2,12 @@
#include "imx8mq-u-boot.dtsi"
&gpio2 {
bootph-pre-ram;
};
&reg_usdhc2_vmmc {
bootph-pre-ram;
u-boot,off-on-delay-us = <20000>;
};
@@ -13,3 +18,39 @@
&pinctrl_uart1 {
bootph-pre-ram;
};
&usdhc1 {
bootph-pre-ram;
};
&pinctrl_usdhc1 {
bootph-pre-ram;
};
&pinctrl_usdhc1_100mhz {
bootph-pre-ram;
};
&pinctrl_usdhc1_200mhz {
bootph-pre-ram;
};
&usdhc2 {
bootph-pre-ram;
};
&pinctrl_usdhc2 {
bootph-pre-ram;
};
&pinctrl_usdhc2_100mhz {
bootph-pre-ram;
};
&pinctrl_usdhc2_200mhz {
bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
bootph-pre-ram;
};
arch/arm/dts/imx8mq-u-boot.dtsi
+153 -129
View File
@@ -41,6 +41,33 @@
filename = "flash.bin";
section {
pad-byte = <0x00>;
/*
* signed_hdmi_imx8m.bin contains a 1KB zero-filled padding at
* its beginning. This padding has no functional purpose, but
* the firmware is provided and signed by NXP, so the head
* must be preserved and should not be removed.
*
* When the signed HDMI firmware is placed at the beginning of
* flash.bin, the IVT header of u-boot-spl must still reside at
* a 4KB-aligned address. Since flash.bin starts with the HDMI
* firmware (including its 1KB padding), there is already a 1KB
* empty region at the head of flash.bin.
*
* The required 4KB alignment is therefore calculated relative
* to the location after this 1KB padding. To achieve this, we
* explicitly set align and align-size to 0x1000, and add an
* additional 0x400 (1KB) fill to account for the padding.
*/
signed-hdmi-imx8m {
filename = "signed_hdmi_imx8m.bin";
type = "blob-ext";
align = <0x1000>;
align-size = <0x1000>;
};
fill {
size = <0x400>;
};
#ifdef CONFIG_IMX_HAB
nxp-imx8mcst@0 {
@@ -51,145 +78,142 @@
#endif
binman_imx_spl: nxp-imx8mimage {
filename = "u-boot-spl-mkimage.bin";
nxp,boot-from = "sd";
nxp,rom-version = <1>;
nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
args; /* Needed by mkimage etype superclass */
section {
align = <4>;
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
u-boot-spl {
align-end = <4>;
filename = "u-boot-spl.bin";
};
ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem.bin";
align-end = <4>;
type = "blob-ext";
};
signed-hdmi-imx8m {
filename = "signed_hdmi_imx8m.bin";
type = "blob-ext";
};
};
};
#ifdef CONFIG_IMX_HAB
};
nxp-imx8mcst@1 {
filename = "u-boot-fit.signed.bin";
nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>;
offset = <0x58000>;
filename = "u-boot-spl-mkimage.bin";
nxp,boot-from = "sd";
nxp,rom-version = <1>;
nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
args; /* Needed by mkimage etype superclass */
#endif
binman_imx_fit: fit {
description = "Configuration to load ATF before U-Boot";
filename = "u-boot.itb";
#ifndef CONFIG_IMX_HAB
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
#endif
#address-cells = <1>;
section {
align = <4>;
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
offset = <0x57c00>;
images {
uboot {
arch = "arm64";
compression = "none";
description = "U-Boot (64-bit)";
load = <CONFIG_TEXT_BASE>;
type = "standalone";
uboot-blob {
filename = "u-boot-nodtb.bin";
type = "blob-ext";
};
};
#ifndef CONFIG_ARMV8_PSCI
atf {
arch = "arm64";
compression = "none";
description = "ARM Trusted Firmware";
entry = <0x910000>;
load = <0x910000>;
type = "firmware";
atf-blob {
filename = "bl31.bin";
type = "blob-ext";
};
};
#endif
tee: tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <CONFIG_IMX8M_OPTEE_LOAD_ADDR>;
entry = <CONFIG_IMX8M_OPTEE_LOAD_ADDR>;
tee-os {
filename = "tee.bin";
optional;
};
};
fdt {
compression = "none";
description = "NAME";
type = "flat_dt";
uboot-fdt-blob {
filename = "u-boot.dtb";
type = "blob-ext";
};
};
u-boot-spl {
align-end = <4>;
filename = "u-boot-spl.bin";
};
configurations {
default = "conf";
ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem.bin";
align-end = <4>;
type = "blob-ext";
};
conf {
description = "NAME";
fdt = "fdt";
firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
loadables = "atf", "tee";
#endif
};
ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem.bin";
align-end = <4>;
type = "blob-ext";
};
};
};
#ifdef CONFIG_IMX_HAB
};
#endif
};
#ifdef CONFIG_IMX_HAB
nxp-imx8mcst@1 {
filename = "u-boot-fit.signed.bin";
nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>;
offset = <0x58400>;
args; /* Needed by mkimage etype superclass */
#endif
binman_imx_fit: fit {
description = "Configuration to load ATF before U-Boot";
filename = "u-boot.itb";
#ifndef CONFIG_IMX_HAB
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
#endif
#address-cells = <1>;
offset = <0x58000>;
images {
uboot {
arch = "arm64";
compression = "none";
description = "U-Boot (64-bit)";
load = <CONFIG_TEXT_BASE>;
type = "standalone";
uboot-blob {
filename = "u-boot-nodtb.bin";
type = "blob-ext";
};
};
#ifndef CONFIG_ARMV8_PSCI
atf {
arch = "arm64";
compression = "none";
description = "ARM Trusted Firmware";
entry = <0x910000>;
load = <0x910000>;
type = "firmware";
atf-blob {
filename = "bl31.bin";
type = "blob-ext";
};
};
#endif
tee: tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <CONFIG_IMX8M_OPTEE_LOAD_ADDR>;
entry = <CONFIG_IMX8M_OPTEE_LOAD_ADDR>;
tee-os {
filename = "tee.bin";
optional;
};
};
fdt {
compression = "none";
description = "NAME";
type = "flat_dt";
uboot-fdt-blob {
filename = "u-boot.dtb";
type = "blob-ext";
};
};
};
configurations {
default = "conf";
conf {
description = "NAME";
fdt = "fdt";
firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
loadables = "atf", "tee";
#endif
};
};
};
#ifdef CONFIG_IMX_HAB
};
#endif
};
arch/arm/dts/imx95-verdin-dev.dtsi
+239
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@@ -0,0 +1,239 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) Toradex
*
* Common dtsi for Verdin iMX95 SoM on development carrier board
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
* https://www.toradex.com/products/carrier-board/verdin-development-board-kit
*/
/ {
aliases {
eeprom1 = &carrier_eeprom;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "verdin-nau8822";
simple-audio-card,routing =
"Headphones", "LHP",
"Headphones", "RHP",
"Speaker", "LSPK",
"Speaker", "RSPK",
"Line Out", "AUXOUT1",
"Line Out", "AUXOUT2",
"LAUX", "Line In",
"RAUX", "Line In",
"LMICP", "Mic In",
"RMICP", "Mic In";
simple-audio-card,widgets =
"Headphones", "Headphones",
"Line Out", "Line Out",
"Speaker", "Speaker",
"Microphone", "Mic In",
"Line", "Line In";
codec_dai: simple-audio-card,codec {
clocks = <&scmi_clk IMX95_CLK_SAI3>;
sound-dai = <&nau8822_1a>;
};
simple-audio-card,cpu {
sound-dai = <&sai3>;
};
};
};
/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */
&adc1 {
status = "okay";
};
/* Verdin ETH_1 (On-module PHY) */
&enetc_port0 {
status = "okay";
};
/* Verdin ETH_2_RGMII */
&enetc_port1 {
phy-handle = <&ethphy2>;
phy-mode = "rgmii-id";
status = "okay";
};
/* Verdin QSPI_1 */
&flexspi1 {
status = "okay";
};
&gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
&gpio2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1>,
<&pinctrl_gpio2>,
<&pinctrl_gpio3>;
};
&gpio3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio6>;
};
&gpio4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio5>;
};
&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio4>;
};
/* Verdin I2C_3_HDMI */
&i3c2 {
status = "okay";
};
/* Verdin I2C_2_DSI */
&lpi2c3 {
status = "okay";
};
/* Verdin I2C_1 */
&lpi2c4 {
status = "okay";
nau8822_1a: audio-codec@1a {
compatible = "nuvoton,nau8822";
reg = <0x1a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3_mclk>;
#sound-dai-cells = <0>;
};
carrier_gpio_expander: gpio@21 {
compatible = "nxp,pcal6416";
reg = <0x21>;
#gpio-cells = <2>;
gpio-controller;
};
/* Current measurement into module VCC */
hwmon@40 {
compatible = "ti,ina219";
reg = <0x40>;
shunt-resistor = <10000>;
};
temperature-sensor@4f {
compatible = "ti,tmp75c";
reg = <0x4f>;
};
carrier_eeprom: eeprom@57 {
compatible = "st,24c02", "atmel,24c02";
reg = <0x57>;
pagesize = <16>;
};
};
/* Verdin I2C_4_CSI */
&lpi2c5 {
status = "okay";
};
/* Verdin UART_3, used as the Linux console */
&lpuart1 {
status = "okay";
};
/* Verdin UART_4 */
&lpuart2 {
status = "okay";
};
/* Verdin UART_1, connector X50 through RS485 transceiver */
&lpuart7 {
rs485-rts-active-low;
rs485-rx-during-tx;
linux,rs485-enabled-at-boot-time;
status = "okay";
};
/* Verdin UART_2 */
&lpuart8 {
status = "okay";
};
&netc_emdio {
ethphy2: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eth2_rgmii_int>;
interrupt-parent = <&gpio1>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <0>;
};
};
/* Verdin PCIE_1 */
&pcie0 {
status = "okay";
};
/* Verdin I2S_1 */
&sai3 {
status = "okay";
};
/* Verdin PWM_1 */
&tpm4 {
status = "okay";
};
/* Verdin PWM_2 */
&tpm5 {
status = "okay";
};
/* Verdin PWM_3_DSI */
&tpm6 {
status = "okay";
};
/* Verdin USB_1 */
&usb2 {
status = "okay";
};
/* Verdin USB_2 */
&usb3 {
fsl,permanently-attached;
status = "okay";
};
&usb3_phy {
status = "okay";
};
/* Verdin SD_1 */
&usdhc2 {
status = "okay";
};
/* Verdin CTRL_WAKE1_MICO# */
&verdin_gpio_keys {
status = "okay";
};
arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi
+112
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@@ -0,0 +1,112 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) Toradex */
#include "imx95-u-boot.dtsi"
/ {
sysinfo {
compatible = "toradex,sysinfo";
};
};
&{/binman/m33-oei-ddrfw/imx-lpddr/imx-lpddr-imem} {
filename = "lpddr4x_imem_v202409.bin";
};
&{/binman/m33-oei-ddrfw/imx-lpddr/imx-lpddr-dmem} {
filename = "lpddr4x_dmem_v202409.bin";
};
&{/binman/m33-oei-ddrfw/imx-lpddr-qb/imx-lpddr-imem-qb} {
filename = "lpddr4x_imem_qb_v202409.bin";
};
&{/binman/m33-oei-ddrfw/imx-lpddr-qb/imx-lpddr-dmem-qb} {
filename = "lpddr4x_dmem_qb_v202409.bin";
};
&gpio1 {
reg = <0 0x47400000 0 0x1000>, <0 0x47400000 0 0x40>;
bootph-pre-ram;
ctrl-sleep-moci-hog {
bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
gpio-hog;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpios = <14 GPIO_ACTIVE_HIGH>;
line-name = "CTRL_SLEEP_MOCI#";
output-high;
};
};
&som_gpio_expander {
bootph-pre-ram;
};
&lpi2c2 {
bootph-pre-ram;
};
&lpuart1 {
clocks = <&scmi_clk IMX95_CLK_LPUART1>, <&scmi_clk IMX95_CLK_LPUART1>;
clock-names = "ipg", "per";
bootph-pre-ram;
};
&pinctrl_ctrl_sleep_moci {
bootph-pre-ram;
};
&pinctrl_io_exp_int {
bootph-pre-ram;
};
&pinctrl_lpi2c2 {
bootph-pre-ram;
};
&pinctrl_lpi2c2_gpio {
bootph-pre-ram;
};
&pinctrl_uart1 {
bootph-pre-ram;
};
&pinctrl_usdhc1 {
bootph-pre-ram;
};
&pinctrl_usdhc1_200mhz {
bootph-pre-ram;
};
&som_gpio_expander {
bootph-pre-ram;
};
&usb2 {
/delete-property/power-domains;
};
&usb3 {
status = "disabled";
};
&usb3_dwc3 {
status = "disabled";
};
&usb_recov_ctrl {
bootph-pre-ram;
};
&usdhc1 {
bootph-pre-ram;
};
&wdog3 {
status = "disabled";
};
arch/arm/dts/imx95-verdin-wifi-dev.dts
+21
View File
@@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) Toradex
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
* https://www.toradex.com/products/carrier-board/verdin-development-board-kit
*/
/dts-v1/;
#include "imx95-verdin.dtsi"
#include "imx95-verdin-wifi.dtsi"
#include "imx95-verdin-dev.dtsi"
/ {
model = "Toradex Verdin iMX95 WB on Verdin Development Board";
compatible = "toradex,verdin-imx95-wifi-dev",
"toradex,verdin-imx95-wifi",
"toradex,verdin-imx95",
"fsl,imx95";
};
arch/arm/dts/imx95-verdin-wifi.dtsi
+50
View File
@@ -0,0 +1,50 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) Toradex
*
* Common dtsi for Verdin iMX95 SoM WB variant
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
*/
/ {
reg_wifi_en: regulator-wifi-en {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi_pwr_en>;
/* PMIC_EN_WIFI */
gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "PDn_MAYA-W260";
startup-delay-us = <2000>;
};
};
/* On-module Bluetooth */
&lpuart6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bt_uart>;
uart-has-rtscts;
status = "okay";
som_bt: bluetooth {
compatible = "nxp,88w8987-bt";
fw-init-baudrate = <3000000>;
};
};
/* On-module Wi-Fi */
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
keep-power-in-suspend;
non-removable;
vmmc-supply = <&reg_wifi_en>;
status = "okay";
};
arch/arm/dts/imx95-verdin.dtsi
+1172
View File
File diff suppressed because it is too large Load Diff
arch/arm/mach-imx/imx9/Kconfig
+6 -2
View File
@@ -7,6 +7,7 @@ config AHAB_BOOT
config IMX9
bool
select ARCH_MISC_INIT
select BINMAN
select CPU
select CPU_IMX
@@ -22,7 +23,6 @@ config IMX93
config IMX91
bool
select IMX9
select ARCH_MISC_INIT
select ARMV8_SPL_EXCEPTION_VECTORS
config IMX95_A0
@@ -30,7 +30,6 @@ config IMX95_A0
config IMX95
bool
select ARCH_MISC_INIT
select ARMV8_SPL_EXCEPTION_VECTORS
select IMX9
select DM_MAILBOX
@@ -171,6 +170,10 @@ config TARGET_TORADEX_SMARC_IMX95
select IMX95
imply OF_UPSTREAM
config TARGET_VERDIN_IMX95
bool "Support Toradex Verdin iMX95 module"
select IMX95
config TARGET_IMX952_EVK
bool "imx952_evk"
select IMX_SM_CPU
@@ -195,6 +198,7 @@ source "board/variscite/imx93_var_som/Kconfig"
source "board/nxp/imx94_evk/Kconfig"
source "board/nxp/imx95_evk/Kconfig"
source "board/toradex/smarc-imx95/Kconfig"
source "board/toradex/verdin-imx95/Kconfig"
source "board/nxp/imx952_evk/Kconfig"
endif
arch/arm/mach-imx/mx7/Kconfig
+16
View File
@@ -90,6 +90,21 @@ config TARGET_COLIBRI_IMX7
select MX7D
imply CMD_DM
config TARGET_TQMA7
bool "TQ-Systems TQMa7x SoM"
select BOARD_LATE_INIT
select SUPPORT_SPL
select SPL_SEPARATE_BSS if SPL
select DM
select DM_SERIAL
select MX7
imply MX7D
imply CMD_DM
imply DM_THERMAL
help
TQMa7x is a TQ SoM with i.MX7 CPU
The SoM can be used on various baseboards.
endchoice
config SYS_SOC
@@ -102,6 +117,7 @@ source "board/novtech/meerkat96/Kconfig"
source "board/storopack/smegw01/Kconfig"
source "board/technexion/pico-imx7d/Kconfig"
source "board/toradex/colibri_imx7/Kconfig"
source "board/tq/tqma7/Kconfig"
source "board/warp7/Kconfig"
endif
board/dhelectronics/common/dh_imx.c
+2 -2
View File
@@ -10,13 +10,13 @@
#include <net.h>
#include "dh_imx.h"
int dh_imx_get_mac_from_fuse(unsigned char *enetaddr)
int dh_imx_get_mac_from_fuse(unsigned char *enetaddr, int index)
{
/*
* If IIM fuses contain valid MAC address, use it.
* The IIM MAC address fuses are NOT programmed by default.
*/
imx_get_mac_from_fuse(0, enetaddr);
imx_get_mac_from_fuse(index, enetaddr);
if (!is_valid_ethaddr(enetaddr))
return -EINVAL;
board/dhelectronics/common/dh_imx.h
+2 -1
View File
@@ -7,6 +7,7 @@
* dh_imx_get_mac_from_fuse - Get MAC address from fuse and write it to env
*
* @enetaddr: buffer where address is to be stored
* @index: index of MAC address in fuse (starts with 0)
* Return: 0 if OK, other value on error
*/
int dh_imx_get_mac_from_fuse(unsigned char *enetaddr);
int dh_imx_get_mac_from_fuse(unsigned char *enetaddr, int index);
board/dhelectronics/dh_imx6/dh_imx6.c
+1 -1
View File
@@ -94,7 +94,7 @@ int dh_setup_mac_address(struct eeprom_id_page *eip)
if (dh_get_mac_is_enabled("ethernet0"))
return 0;
if (!dh_imx_get_mac_from_fuse(enetaddr))
if (!dh_imx_get_mac_from_fuse(enetaddr, 0))
goto out;
if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
+3 -3
View File
@@ -47,7 +47,7 @@ static int dh_imx8_setup_ethaddr(struct eeprom_id_page *eip)
if (dh_get_mac_is_enabled("ethernet0"))
return 0;
if (!dh_imx_get_mac_from_fuse(enetaddr))
if (!dh_imx_get_mac_from_fuse(enetaddr, 0))
goto out;
if (!dh_get_value_from_eeprom_buffer(DH_MAC0, enetaddr, sizeof(enetaddr), eip))
@@ -72,8 +72,8 @@ static int dh_imx8_setup_eth1addr(struct eeprom_id_page *eip)
if (dh_get_mac_is_enabled("ethernet1"))
return 0;
if (!dh_imx_get_mac_from_fuse(enetaddr))
goto increment_out;
if (!dh_imx_get_mac_from_fuse(enetaddr, 1))
goto out;
if (!dh_get_value_from_eeprom_buffer(DH_MAC1, enetaddr, sizeof(enetaddr), eip))
goto out;
board/google/imx8mq_phanbell/spl.c
+7 -120
View File
@@ -6,134 +6,21 @@
#include <config.h>
#include <hang.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <errno.h>
#include <init.h>
#include <log.h>
#include <asm/io.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/sections.h>
#include <linux/delay.h>
#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
static void spl_dram_init(void)
{
/* ddr init */
ddr_init(&dram_timing);
}
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = 1;
break;
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
return ret;
}
return 1;
}
#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
PAD_CTL_FSEL2)
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
static iomux_v3_cfg_t const usdhc1_pads[] = {
IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
};
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC1_BASE_ADDR},
{USDHC2_BASE_ADDR},
};
int board_mmc_init(struct bd_info *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 USDHC1
* mmc1 USDHC2
*/
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(0);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
usdhc_cfg[0].max_bus_width = 8;
imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
ARRAY_SIZE(usdhc1_pads));
gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
gpio_direction_output(USDHC1_PWR_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC1_PWR_GPIO, 1);
break;
case 1:
init_clk_usdhc(1);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
usdhc_cfg[1].max_bus_width = 4;
imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
ARRAY_SIZE(usdhc2_pads));
gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
gpio_direction_output(USDHC2_PWR_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC2_PWR_GPIO, 1);
break;
default:
printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
}
void spl_board_init(void)
{
puts("Normal Boot\n");
@@ -153,8 +40,8 @@ void board_init_f(ulong dummy)
{
int ret;
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
arch_cpu_init();
@@ -166,12 +53,9 @@ void board_init_f(ulong dummy)
preloader_console_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
ret = spl_init();
ret = spl_early_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
debug("spl_early_init() failed: %d\n", ret);
hang();
}
@@ -180,5 +64,8 @@ void board_init_f(ulong dummy)
/* DDR initialization */
spl_dram_init();
init_clk_usdhc(0);
init_clk_usdhc(1);
board_init_r(NULL, 0);
}
board/kontron/pitx_imx8m/spl.c
+27 -161
View File
@@ -2,22 +2,14 @@
#include <config.h>
#include <errno.h>
#include <fsl_esdhc_imx.h>
#include <hang.h>
#include <init.h>
#include <log.h>
#include <spl.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/sections.h>
#include <linux/delay.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
@@ -26,8 +18,6 @@
extern struct dram_timing_info dram_timing_2gb;
extern struct dram_timing_info dram_timing_4gb;
DECLARE_GLOBAL_DATA_PTR;
static void spl_dram_init(void)
{
struct dram_timing_info *dram_timing;
@@ -53,120 +43,6 @@ static void spl_dram_init(void)
ddr_init(dram_timing);
}
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
.gp = IMX_GPIO_NR(5, 14),
},
.sda = {
.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
.gp = IMX_GPIO_NR(5, 15),
},
};
#if CONFIG_IS_ENABLED(MMC)
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
/* the eMMC does not have a CD pin */
return 1;
case USDHC2_BASE_ADDR:
return !gpio_get_value(USDHC2_CD_GPIO);
}
return 0;
}
#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
PAD_CTL_FSEL2)
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
static iomux_v3_cfg_t const usdhc1_pads[] = {
IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
};
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC1_BASE_ADDR, 0, 8},
{USDHC2_BASE_ADDR, 0, 4},
};
int board_mmc_init(struct bd_info *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 USDHC1
* mmc1 USDHC2
*/
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(0);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
ARRAY_SIZE(usdhc1_pads));
gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
gpio_direction_output(USDHC1_PWR_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC1_PWR_GPIO, 1);
break;
case 1:
init_clk_usdhc(1);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
ARRAY_SIZE(usdhc2_pads));
gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
gpio_direction_output(USDHC2_PWR_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC2_PWR_GPIO, 1);
break;
default:
printf("Warning: you configured more USDHC controllers "
"(%d) than supported by the board\n", i + 1);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
}
const char *spl_board_loader_name(u32 boot_device)
{
switch (boot_device) {
@@ -178,18 +54,14 @@ const char *spl_board_loader_name(u32 boot_device)
return NULL;
}
}
#endif
#if CONFIG_IS_ENABLED(POWER_LEGACY)
#define I2C_PMIC 0
static int pfuze_mode_init(struct pmic *p, u32 mode)
static int pfuze_mode_init(struct udevice *dev, u32 mode)
{
unsigned char offset, i, switch_num;
u32 id;
int ret;
pmic_reg_read(p, PFUZE100_DEVICEID, &id);
id = pmic_reg_read(dev, PFUZE100_DEVICEID);
id = id & 0xf;
if (id == 0) {
@@ -203,14 +75,14 @@ static int pfuze_mode_init(struct pmic *p, u32 mode)
return -EINVAL;
}
ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode);
if (ret < 0) {
printf("Set SW1AB mode error!\n");
return ret;
}
for (i = 0; i < switch_num - 1; i++) {
ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode);
if (ret < 0) {
printf("Set switch 0x%x mode error!\n",
offset + i * SWITCH_SIZE);
@@ -223,46 +95,44 @@ static int pfuze_mode_init(struct pmic *p, u32 mode)
int power_init_board(void)
{
struct pmic *p;
struct udevice *dev;
int reg;
int ret;
unsigned int reg;
ret = power_pfuze100_init(I2C_PMIC);
if (ret)
return -ENODEV;
ret = pmic_get("pmic@8", &dev);
if (ret == -ENODEV) {
puts("No pmic@8\n");
return 0;
}
if (ret < 0)
return ret;
p = pmic_get("PFUZE100");
ret = pmic_probe(p);
if (ret)
return -ENODEV;
pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
reg = pmic_reg_read(dev, PFUZE100_SW3AVOL);
if ((reg & 0x3f) != 0x18) {
reg &= ~0x3f;
reg |= 0x18;
pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
pmic_reg_write(dev, PFUZE100_SW3AVOL, reg);
}
ret = pfuze_mode_init(p, APS_PFM);
ret = pfuze_mode_init(dev, APS_PFM);
if (ret < 0)
return ret;
/* set SW3A standby mode to off */
pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
reg = pmic_reg_read(dev, PFUZE100_SW3AMODE);
reg &= ~0xf;
reg |= APS_OFF;
pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
pmic_reg_write(dev, PFUZE100_SW3AMODE, reg);
return 0;
}
#endif
void board_init_f(ulong dummy)
{
int ret;
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
arch_cpu_init();
@@ -272,26 +142,22 @@ void board_init_f(ulong dummy)
timer_init();
preloader_console_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
ret = spl_init();
ret = spl_early_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
debug("spl_early_init() failed: %d\n", ret);
hang();
}
preloader_console_init();
enable_tzc380();
setup_i2c(0, 100000, 0x7f, &i2c_pad_info1);
#if CONFIG_IS_ENABLED(POWER_LEGACY)
power_init_board();
#endif
spl_dram_init();
init_clk_usdhc(0);
init_clk_usdhc(1);
board_init_r(NULL, 0);
}
board/mntre/imx8mq_reform2/spl.c
-6
View File
@@ -10,7 +10,6 @@
#include <image.h>
#include <init.h>
#include <log.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <errno.h>
#include <asm/io.h>
@@ -28,8 +27,6 @@
#include <power/pmic.h>
#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
extern struct dram_timing_info dram_timing_ch2;
static void spl_dram_init(void)
@@ -226,9 +223,6 @@ void board_init_f(ulong dummy)
{
int ret;
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
arch_cpu_init();
init_uart_clk(0);
board/nxp/common/Makefile
+1 -1
View File
@@ -57,7 +57,7 @@ obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o
ifeq ($(CONFIG_$(PHASE_)POWER_LEGACY),y)
obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
endif
obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o
obj-$(CONFIG_$(PHASE_)DM_PMIC_PFUZE100) += pfuze.o
obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o
ifneq (,$(filter $(SOC), imx8m imx8ulp imx9))
obj-y += mmc.o
board/nxp/common/pfuze.c
+80 -80
View File
@@ -7,7 +7,86 @@
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#ifndef CONFIG_DM_PMIC_PFUZE100
#if CONFIG_IS_ENABLED(DM_PMIC_PFUZE100)
int pfuze_mode_init(struct udevice *dev, u32 mode)
{
unsigned char offset, i, switch_num;
u32 id;
int ret;
id = pmic_reg_read(dev, PFUZE100_DEVICEID);
id = id & 0xf;
if (id == 0) {
switch_num = 6;
offset = PFUZE100_SW1CMODE;
} else if (id == 1) {
switch_num = 4;
offset = PFUZE100_SW2MODE;
} else {
printf("Not supported, id=%d\n", id);
return -EINVAL;
}
ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode);
if (ret < 0) {
printf("Set SW1AB mode error!\n");
return ret;
}
for (i = 0; i < switch_num - 1; i++) {
ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode);
if (ret < 0) {
printf("Set switch 0x%x mode error!\n",
offset + i * SWITCH_SIZE);
return ret;
}
}
return ret;
}
struct udevice *pfuze_common_init(void)
{
struct udevice *dev;
int ret;
unsigned int reg, dev_id, rev_id;
ret = pmic_get("pfuze100@8", &dev);
if (ret == -ENODEV)
return NULL;
dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
rev_id = pmic_reg_read(dev, PFUZE100_REVID);
printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
/* Set SW1AB stanby volage to 0.975V */
reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
reg &= ~SW1x_STBY_MASK;
reg |= SW1x_0_975V;
pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
reg &= ~SW1xCONF_DVSSPEED_MASK;
reg |= SW1xCONF_DVSSPEED_4US;
pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
/* Set SW1C standby voltage to 0.975V */
reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
reg &= ~SW1x_STBY_MASK;
reg |= SW1x_0_975V;
pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
reg &= ~SW1xCONF_DVSSPEED_MASK;
reg |= SW1xCONF_DVSSPEED_4US;
pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
return dev;
}
#else
int pfuze_mode_init(struct pmic *p, u32 mode)
{
unsigned char offset, i, switch_num;
@@ -90,83 +169,4 @@ struct pmic *pfuze_common_init(unsigned char i2cbus)
return p;
}
#elif defined(CONFIG_DM_PMIC)
int pfuze_mode_init(struct udevice *dev, u32 mode)
{
unsigned char offset, i, switch_num;
u32 id;
int ret;
id = pmic_reg_read(dev, PFUZE100_DEVICEID);
id = id & 0xf;
if (id == 0) {
switch_num = 6;
offset = PFUZE100_SW1CMODE;
} else if (id == 1) {
switch_num = 4;
offset = PFUZE100_SW2MODE;
} else {
printf("Not supported, id=%d\n", id);
return -EINVAL;
}
ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode);
if (ret < 0) {
printf("Set SW1AB mode error!\n");
return ret;
}
for (i = 0; i < switch_num - 1; i++) {
ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode);
if (ret < 0) {
printf("Set switch 0x%x mode error!\n",
offset + i * SWITCH_SIZE);
return ret;
}
}
return ret;
}
struct udevice *pfuze_common_init(void)
{
struct udevice *dev;
int ret;
unsigned int reg, dev_id, rev_id;
ret = pmic_get("pfuze100@8", &dev);
if (ret == -ENODEV)
return NULL;
dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
rev_id = pmic_reg_read(dev, PFUZE100_REVID);
printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
/* Set SW1AB stanby volage to 0.975V */
reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
reg &= ~SW1x_STBY_MASK;
reg |= SW1x_0_975V;
pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
reg &= ~SW1xCONF_DVSSPEED_MASK;
reg |= SW1xCONF_DVSSPEED_4US;
pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
/* Set SW1C standby voltage to 0.975V */
reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
reg &= ~SW1x_STBY_MASK;
reg |= SW1x_0_975V;
pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
reg &= ~SW1xCONF_DVSSPEED_MASK;
reg |= SW1xCONF_DVSSPEED_4US;
pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
return dev;
}
#endif
board/nxp/common/pfuze.h
+1 -1
View File
@@ -6,7 +6,7 @@
#ifndef __PFUZE_BOARD_HELPER__
#define __PFUZE_BOARD_HELPER__
#ifdef CONFIG_DM_PMIC_PFUZE100
#if CONFIG_IS_ENABLED(DM_PMIC_PFUZE100)
struct udevice *pfuze_common_init(void);
int pfuze_mode_init(struct udevice *dev, u32 mode);
#else
board/nxp/imx8mq_evk/spl.c
+31 -155
View File
@@ -9,23 +9,16 @@
#include <image.h>
#include <init.h>
#include <log.h>
#include <asm/io.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <fsl_sec.h>
#include <mmc.h>
#include <linux/delay.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <spl.h>
#include "../common/pfuze.h"
@@ -40,166 +33,52 @@ static void spl_dram_init(void)
ddr_init(&dram_timing_b0);
}
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
.gp = IMX_GPIO_NR(5, 14),
},
.sda = {
.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
.gp = IMX_GPIO_NR(5, 15),
},
};
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = 1;
break;
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
return ret;
}
return 1;
}
#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
PAD_CTL_FSEL2)
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
static iomux_v3_cfg_t const usdhc1_pads[] = {
IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
};
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC1_BASE_ADDR, 0, 8},
{USDHC2_BASE_ADDR, 0, 4},
};
int board_mmc_init(struct bd_info *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 USDHC1
* mmc1 USDHC2
*/
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(0);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
ARRAY_SIZE(usdhc1_pads));
gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
gpio_direction_output(USDHC1_PWR_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC1_PWR_GPIO, 1);
break;
case 1:
init_clk_usdhc(1);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
ARRAY_SIZE(usdhc2_pads));
gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
gpio_direction_output(USDHC2_PWR_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC2_PWR_GPIO, 1);
break;
default:
printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
}
#if CONFIG_IS_ENABLED(POWER_LEGACY)
#define I2C_PMIC 0
int power_init_board(void)
{
struct pmic *p;
struct udevice *dev;
int reg;
int ret;
unsigned int reg;
ret = power_pfuze100_init(I2C_PMIC);
if (ret)
return -ENODEV;
ret = pmic_get("pmic@8", &dev);
if (ret == -ENODEV) {
puts("No pmic@8\n");
return 0;
}
if (ret < 0)
return ret;
p = pmic_get("PFUZE100");
ret = pmic_probe(p);
if (ret)
return -ENODEV;
pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
reg = pmic_reg_read(dev, PFUZE100_SW3AVOL);
if ((reg & 0x3f) != 0x18) {
reg &= ~0x3f;
reg |= 0x18;
pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
pmic_reg_write(dev, PFUZE100_SW3AVOL, reg);
}
ret = pfuze_mode_init(p, APS_PFM);
ret = pfuze_mode_init(dev, APS_PFM);
if (ret < 0)
return ret;
/* set SW3A standby mode to off */
pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
reg = pmic_reg_read(dev, PFUZE100_SW3AMODE);
reg &= ~0xf;
reg |= APS_OFF;
pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
pmic_reg_write(dev, PFUZE100_SW3AMODE, reg);
return 0;
}
#endif
void spl_board_init(void)
{
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
if (sec_init())
printf("\nsec_init failed!\n");
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
printf("Failed to initialize caam_jr: %d\n", ret);
}
puts("Normal Boot\n");
}
@@ -218,8 +97,8 @@ void board_init_f(ulong dummy)
{
int ret;
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
arch_cpu_init();
@@ -229,25 +108,22 @@ void board_init_f(ulong dummy)
timer_init();
preloader_console_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
ret = spl_init();
ret = spl_early_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
debug("spl_early_init() failed: %d\n", ret);
hang();
}
preloader_console_init();
enable_tzc380();
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
power_init_board();
/* DDR initialization */
spl_dram_init();
init_clk_usdhc(0);
init_clk_usdhc(1);
board_init_r(NULL, 0);
}
board/nxp/mx6sabreauto/mx6sabreauto.c
+2
View File
@@ -465,6 +465,7 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
}
#endif
#ifndef CONFIG_XPL_BUILD
int power_init_board(void)
{
struct udevice *dev;
@@ -488,6 +489,7 @@ int power_init_board(void)
return pfuze_mode_init(dev, APS_PFM);
}
#endif
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
board/nxp/mx6sabresd/mx6sabresd.c
+2
View File
@@ -437,6 +437,7 @@ int board_init(void)
return 0;
}
#ifndef CONFIG_XPL_BUILD
int power_init_board(void)
{
struct udevice *dev;
@@ -468,6 +469,7 @@ int power_init_board(void)
return 0;
}
#endif
#ifdef CONFIG_MXC_SPI
int board_spi_cs_gpio(unsigned bus, unsigned cs)
board/ronetix/imx8mq-cm/spl.c
-5
View File
@@ -18,8 +18,6 @@
#include <linux/delay.h>
#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
static void spl_dram_init(void)
{
/* ddr init */
@@ -135,9 +133,6 @@ void board_init_f(ulong dummy)
{
int ret;
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
arch_cpu_init();
init_uart_clk(0);
board/technexion/pico-imx8mq/spl.c
-6
View File
@@ -10,7 +10,6 @@
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
@@ -24,8 +23,6 @@
#include "lpddr4_timing.h"
DECLARE_GLOBAL_DATA_PTR;
#define DDR_DET_1 IMX_GPIO_NR(3, 11)
#define DDR_DET_2 IMX_GPIO_NR(3, 12)
#define DDR_DET_3 IMX_GPIO_NR(3, 13)
@@ -196,9 +193,6 @@ void board_init_f(ulong dummy)
{
int ret;
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
arch_cpu_init();
init_uart_clk(0);
board/toradex/common/tdx-cfg-block.c
+3
View File
@@ -187,6 +187,9 @@ const struct toradex_som toradex_modules[] = {
{ OSM_IMX91S_2GB_IT, "OSM iMX91 Solo 2GB IT", TARGET_IS_ENABLED(TORADEX_OSM_IMX91) },
{ VERDIN_AM62D_1G_ET_GPU_NODSI, "Verdin AM62 Dual 1GB ET", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
{ AQUILA_TDA4O_16GB_IT, "Aquila TDA4 Octa 16GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) },
{ VERDIN_IMX95H_4G_WB_IT, "Verdin iMX95 Hexa 4GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX95) },
{ VERDIN_IMX95H_4G_ET, "Verdin iMX95 Hexa 4GB ET", TARGET_IS_ENABLED(VERDIN_IMX95) },
{ VERDIN_IMX95H_16G_IT, "Verdin iMX95 Hexa 16GB IT", TARGET_IS_ENABLED(VERDIN_IMX95) },
};
struct pid4list {
board/toradex/common/tdx-cfg-block.h
+3
View File
@@ -150,6 +150,9 @@ enum {
OSM_IMX91S_2GB_IT, /* 220 */
VERDIN_AM62D_1G_ET_GPU_NODSI,
AQUILA_TDA4O_16GB_IT = 223,
VERDIN_IMX95H_4G_WB_IT = 226,
VERDIN_IMX95H_4G_ET,
VERDIN_IMX95H_16G_IT,
};
enum {
board/toradex/verdin-imx95/Kconfig
+36
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@@ -0,0 +1,36 @@
if TARGET_VERDIN_IMX95
config SYS_BOARD
default "verdin-imx95"
config SYS_VENDOR
default "toradex"
config SYS_CONFIG_NAME
default "verdin-imx95"
config TDX_CFG_BLOCK
default y
config TDX_CFG_BLOCK_2ND_ETHADDR
default y
config TDX_CFG_BLOCK_DEV
default "0"
# Toradex config block in eMMC, at the end of 1st "boot sector"
config TDX_CFG_BLOCK_OFFSET
default "-512"
config TDX_CFG_BLOCK_PART
default "1"
config TDX_HAVE_EEPROM_EXTRA
default y
config TDX_HAVE_MMC
default y
source "board/toradex/common/Kconfig"
endif
board/toradex/verdin-imx95/MAINTAINERS
+13
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@@ -0,0 +1,13 @@
Verdin iMX95
F: arch/arm/dts/imx95-verdin.dtsi
F: arch/arm/dts/imx95-verdin-dev.dtsi
F: arch/arm/dts/imx95-verdin-wifi.dtsi
F: arch/arm/dts/imx95-verdin-wifi-dev.dts
F: arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi
F: board/toradex/verdin-imx95/
F: configs/verdin-imx95_defconfig
F: doc/board/toradex/verdin-imx95.rst
F: include/configs/verdin-imx95.h
M: Francesco Dolcini <francesco.dolcini@toradex.com>
S: Maintained
W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
board/toradex/verdin-imx95/Makefile
+8
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@@ -0,0 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# Copyright (c) Toradex
obj-y += verdin-imx95.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
endif
board/toradex/verdin-imx95/spl.c
+75
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@@ -0,0 +1,75 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* Copyright (c) Toradex */
#include <asm/arch/clock.h>
#include <asm/arch/mu.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/ele_api.h>
#include <asm/sections.h>
#include <asm/global_data.h>
#include <clk.h>
#include <dm/uclass.h>
#include <hang.h>
#include <i2c.h>
#include <init.h>
#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
switch (boot_dev_spl) {
case SD1_BOOT:
case MMC1_BOOT:
return BOOT_DEVICE_MMC1;
case SD2_BOOT:
case MMC2_BOOT:
return BOOT_DEVICE_MMC2;
case USB_BOOT:
return BOOT_DEVICE_BOARD;
default:
return BOOT_DEVICE_NONE;
}
}
void spl_board_init(void)
{
int ret;
ret = ele_start_rng();
if (ret)
printf("Fail to start RNG: %d\n", ret);
}
void board_init_f(ulong dummy)
{
int ret;
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
if (IS_ENABLED(CONFIG_SPL_RECOVER_DATA_SECTION))
spl_save_restore_data();
timer_init();
/* Need dm_init() to run before any SCMI calls */
spl_early_init();
/* Need to enable SCMI drivers and ELE driver before console */
ret = imx9_probe_mu();
if (ret)
hang(); /* MU not probed, nothing can be outputed, hang */
arch_cpu_init();
preloader_console_init();
debug("SOC: 0x%x\n", gd->arch.soc_rev);
debug("LC: 0x%x\n", gd->arch.lifecycle);
get_reset_reason(true, false);
board_init_r(NULL, 0);
}
board/toradex/verdin-imx95/verdin-imx95.c
+80
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@@ -0,0 +1,80 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* Copyright (c) Toradex */
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <env.h>
#include <errno.h>
#include <fdt_support.h>
#include <init.h>
#include <stdio.h>
#include <string.h>
#include "../common/tdx-cfg-block.h"
#include "../common/tdx-common.h"
DECLARE_GLOBAL_DATA_PTR;
static void select_dt_from_module_version(void)
{
char variant[32];
char *env_variant = env_get("variant");
bool is_wifi = false;
if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) {
/*
* If we have a valid config block and it says we are a
* module with Wi-Fi/Bluetooth make sure we use the -wifi
* device tree.
*/
is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX95H_8G_WIFI_BT_IT) ||
(tdx_hw_tag.prodid == VERDIN_IMX95H_4G_WB_IT);
}
if (is_wifi)
strlcpy(&variant[0], "wifi", sizeof(variant));
else
strlcpy(&variant[0], "nonwifi", sizeof(variant));
if (!env_variant || strcmp(variant, env_variant)) {
printf("Setting variant to %s\n", variant);
env_set("variant", variant);
}
}
int board_late_init(void)
{
select_dt_from_module_version();
return 0;
}
static const struct ram_alias_check ram_alias_checks[] = {
{ (void *)(PHYS_SDRAM + SZ_8G), (void *)(PHYS_SDRAM), SZ_16G },
{ (void *)(PHYS_SDRAM + SZ_4G), (void *)(PHYS_SDRAM), SZ_8G },
{ (void *)(PHYS_SDRAM + SZ_2G), (void *)(PHYS_SDRAM), SZ_4G },
{ (void *)(PHYS_SDRAM + SZ_1G), (void *)(PHYS_SDRAM), SZ_2G },
{ NULL }
};
int board_phys_sdram_size(phys_size_t *size)
{
phys_size_t sz;
sz = probe_ram_size_by_alias(ram_alias_checks);
if (!sz) {
puts("## WARNING: Less than 2GB RAM detected\n");
return -EINVAL;
}
*size = sz - PHYS_SDRAM_FW_RSVD;
return 0;
}
#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
return ft_common_board_setup(blob, bd);
}
#endif
board/toradex/verdin-imx95/verdin-imx95.env
+20
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@@ -0,0 +1,20 @@
boot_scripts=boot.scr
boot_script_dhcp=boot.scr
boot_targets=mmc1 mmc0 dhcp
console=ttyLP2
fdt_board=dev
fdt_addr=0x9c400000
fdt_addr_r=0x9c400000
kernel_addr_r=CONFIG_SYS_LOAD_ADDR
kernel_comp_addr_r=0x94400000
kernel_comp_size=0x8000000
ramdisk_addr_r=0x9c800000
scriptaddr=0x9c600000
update_uboot=
askenv confirm Did you load flash.bin (y/N)?;
if test "$confirm" = y; then
setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt
${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0
${blkcnt};
fi
board/tq/MAINTAINERS
+9
View File
@@ -6,3 +6,12 @@ W: https://www.tq-group.com/en/products/tq-embedded/
F: arch/arm/dts/*mba6*.dts*
F: arch/arm/dts/*tqma6*.dts*
F: configs/tqma6*config
TQMA7
M: Alexander Feilke <Alexander.Feilke@ew.tq-group.com>
L: u-boot@ew.tq-group.com
S: Maintained
W: https://www.tq-group.com/en/products/tq-embedded/
F: arch/arm/dts/*mba7*.dts*
F: arch/arm/dts/*tqma7*.dts*
F: configs/tqma7*config
board/tq/common/Kconfig
+3
View File
@@ -11,3 +11,6 @@ config TQ_COMMON_BB
config TQ_COMMON_SDMMC
bool
config TQ_COMMON_SOM
bool
board/tq/common/Makefile
+1
View File
@@ -6,4 +6,5 @@
#
obj-$(CONFIG_TQ_COMMON_BB) += tq_bb.o
obj-$(CONFIG_TQ_COMMON_SOM) += tq_som.o
obj-$(CONFIG_TQ_COMMON_SDMMC) += tq_sdmmc.o
board/tq/common/tq_som.c
+32
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@@ -0,0 +1,32 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2025-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Feilke, Max Merchel
*/
#include <init.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include "tq_som.h"
void __weak tq_som_ram_init(void)
{
;
}
/*
* checks if the accessible range equals the requested RAM size.
* returns true if successful, false otherwise
*/
bool tq_som_ram_check_size(long ram_size)
{
long size;
size = get_ram_size((void *)PHYS_SDRAM, ram_size);
debug("SPL: requested RAM size %lu MiB. accessible %lu MiB\n",
ram_size / (SZ_1M), size / (SZ_1M));
return (size == ram_size);
}
board/tq/common/tq_som.h
+35
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@@ -0,0 +1,35 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2025-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Feilke, Max Merchel
*/
#ifndef __TQ_SOM_H
#define __TQ_SOM_H
#include <init.h>
#include <asm/io.h>
#include <linux/iopoll.h>
void tq_som_ram_init(void);
/* used as a wrapper to write to specific register addresses */
static inline void tq_som_init_write_reg(u32 address, u32 value)
{
writel_relaxed(value, address);
}
/*
* checks if the accessible range equals the requested ram size.
* returns true if successful, false otherwise
*/
bool tq_som_ram_check_size(long ram_size);
static inline void tq_som_check_bits_set(u32 address, u32 mask)
{
u32 val;
readl_poll_timeout(address, val, (val & mask) == mask, 1000);
}
#endif /* __TQ_SOM_H */
board/tq/tqma7/Kconfig
+103
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@@ -0,0 +1,103 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
# D-82229 Seefeld, Germany.
# Author: Markus Niebel, Steffen Doster
#
if TARGET_TQMA7
config SYS_BOARD
default "tqma7"
config SYS_VENDOR
default "tq"
config SYS_CONFIG_NAME
default "tqma7"
choice
prompt "TQMa7x RAM configuration"
default TQMA7_RAM_MULTI
help
Select RAM configuration. Normally use default here but for
specific setup it is possible to use a single RAM size.
config TQMA7_RAM_MULTI
bool "TQMa7x with 512/1024/2048 MB RAM - Single image"
select TQMA7_RAM_2G
select TQMA7_RAM_1G
select TQMA7_RAM_512M
help
Build a single U-Boot solely for variants
with 512/1024/2048 MB RAM.
config TQMA7_RAM_SINGLE_2G
bool "TQMa7x with 2 GB RAM"
select TQMA7_RAM_2G
help
Build U-Boot solely for variants
with 2 GB RAM.
config TQMA7_RAM_SINGLE_1G
bool "TQMa7x with 1 GB RAM"
select TQMA7_RAM_1G
help
Build U-Boot solely for variants
with 1 GB RAM.
config TQMA7_RAM_SINGLE_512M
bool "TQMa7x with 512 MB RAM"
select TQMA7_RAM_512M
help
Build U-Boot solely for variants
with 512 MB RAM.
endchoice
config TQMA7_RAM_2G
bool
config TQMA7_RAM_1G
bool
config TQMA7_RAM_512M
bool
choice
prompt "TQMa7x base board variant"
default MBA7
help
Select base board
for TQMa7x
config MBA7
bool "TQMa7x on MBa7x Starterkit"
select TQ_COMMON_BB
select TQ_COMMON_SOM
select TQ_COMMON_SYSINFO
select I2C_EEPROM
select MISC
imply USB
imply CMD_USB
imply USB_STORAGE
imply PHYLIB
imply CONFIG_PHY_TI_DP83867
select MXC_UART
select DM_MMC
select DM_SPI
select DM_I2C
select DM_GPIO
imply DM_ETH
help
Select the MBa7x
starterkit.
endchoice
config IMX_CONFIG
default "board/tq/tqma7/tqma7.cfg"
source "board/tq/common/Kconfig"
endif
board/tq/tqma7/Makefile
+14
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@@ -0,0 +1,14 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
# D-82229 Seefeld, Germany.
obj-y += tqma7.o
obj-$(CONFIG_MBA7) += tqma7_mba7.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-y += spl_tqma7_ram.o
obj-$(CONFIG_MBA7) += spl_mba7.o
endif
board/tq/tqma7/spl.c
+123
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@@ -0,0 +1,123 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2014-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Feilke
*/
#include <fsl_esdhc_imx.h>
#include <hang.h>
#include <spl.h>
#include <asm/arch/clock.h>
#include <asm/arch-mx7/mx7d_pins.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include "../common/tq_bb.h"
#include "../common/tq_som.h"
DECLARE_GLOBAL_DATA_PTR;
#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
#define USDHC_CMD_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
#define USDHC_CLK_PAD_CTRL (PAD_CTL_DSE_3P3V_98OHM | \
PAD_CTL_SRE_SLOW | PAD_CTL_PUS_PU47KOHM)
#define USDHC_STROBE_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PD100KOHM)
/* eMMC on USDHCI3 always present */
static const iomux_v3_cfg_t tqma7_usdhc3_pads[] = {
NEW_PAD_CTRL(MX7D_PAD_SD3_CLK__SD3_CLK, USDHC_CLK_PAD_CTRL),
NEW_PAD_CTRL(MX7D_PAD_SD3_CMD__SD3_CMD, USDHC_CMD_PAD_CTRL),
NEW_PAD_CTRL(MX7D_PAD_SD3_DATA0__SD3_DATA0, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX7D_PAD_SD3_DATA1__SD3_DATA1, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX7D_PAD_SD3_DATA2__SD3_DATA2, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX7D_PAD_SD3_DATA3__SD3_DATA3, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX7D_PAD_SD3_DATA4__SD3_DATA4, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX7D_PAD_SD3_DATA5__SD3_DATA5, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX7D_PAD_SD3_DATA6__SD3_DATA6, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX7D_PAD_SD3_DATA7__SD3_DATA7, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX7D_PAD_SD3_STROBE__SD3_STROBE, USDHC_STROBE_PAD_CTRL),
};
static struct fsl_esdhc_cfg tqma7_usdhc3_cfg = {
.esdhc_base = USDHC3_BASE_ADDR,
.max_bus_width = 8,
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
if (cfg->esdhc_base == USDHC3_BASE_ADDR)
/* eMMC/uSDHC3 is always present */
ret = 1;
else
ret = tq_bb_board_mmc_getcd(mmc);
return ret;
}
int board_mmc_getwp(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
if (cfg->esdhc_base == USDHC3_BASE_ADDR)
/* eMMC/uSDHC3 is not WP */
ret = 0;
else
ret = tq_bb_board_mmc_getwp(mmc);
return ret;
}
int board_mmc_init(struct bd_info *bis)
{
imx_iomux_v3_setup_multiple_pads(tqma7_usdhc3_pads,
ARRAY_SIZE(tqma7_usdhc3_pads));
tqma7_usdhc3_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
if (fsl_esdhc_initialize(bis, &tqma7_usdhc3_cfg))
puts("Warning: failed to initialize eMMC dev\n");
tq_bb_board_mmc_init(bis);
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
return tq_bb_board_init();
}
/*
* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM
* - no variable global data is available
*/
void board_init_f(ulong dummy)
{
/* setup AIPS and disable watchdog */
arch_cpu_init();
timer_init();
tq_bb_board_early_init_f();
preloader_console_init();
/* DDR initialization */
tq_som_ram_init();
}
board/tq/tqma7/spl_mba7.c
+182
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@@ -0,0 +1,182 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2014-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Feilke
*/
#include <fsl_esdhc_imx.h>
#include <spl.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/arch-mx7/mx7d_pins.h>
#include "../common/tq_bb.h"
#define UART_RX_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
PAD_CTL_PUE | PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
#define UART_TX_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
PAD_CTL_PUE | PAD_CTL_SRE_SLOW)
#define USDHC_DATA_PAD_CTRL (PAD_CTL_DSE_3P3V_98OHM | PAD_CTL_SRE_FAST | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
#define USDHC_CMD_PAD_CTRL (PAD_CTL_DSE_3P3V_98OHM | PAD_CTL_SRE_FAST | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
#define USDHC_CLK_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | \
PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
#define USDHC_STROBE_PAD_CTRL (PAD_CTL_DSE_3P3V_98OHM | PAD_CTL_SRE_FAST | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PD100KOHM)
#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | \
PAD_CTL_DSE_3P3V_196OHM | PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | \
PAD_CTL_DSE_3P3V_98OHM | PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
static const iomux_v3_cfg_t mba7_uart6_pads[] = {
NEW_PAD_CTRL(MX7D_PAD_EPDC_DATA08__UART6_DCE_RX, UART_RX_PAD_CTRL),
NEW_PAD_CTRL(MX7D_PAD_EPDC_DATA09__UART6_DCE_TX, UART_TX_PAD_CTRL),
};
static void mba7_setup_iomuxc_uart(void)
{
imx_iomux_v3_setup_multiple_pads(mba7_uart6_pads, ARRAY_SIZE(mba7_uart6_pads));
}
static const iomux_v3_cfg_t mba7_usdhc1_pads[] = {
NEW_PAD_CTRL(MX7D_PAD_SD1_CLK__SD1_CLK, USDHC_CLK_PAD_CTRL),
NEW_PAD_CTRL(MX7D_PAD_SD1_CMD__SD1_CMD, USDHC_CMD_PAD_CTRL),
NEW_PAD_CTRL(MX7D_PAD_SD1_DATA0__SD1_DATA0, USDHC_DATA_PAD_CTRL),
NEW_PAD_CTRL(MX7D_PAD_SD1_DATA1__SD1_DATA1, USDHC_DATA_PAD_CTRL),
NEW_PAD_CTRL(MX7D_PAD_SD1_DATA2__SD1_DATA2, USDHC_DATA_PAD_CTRL),
NEW_PAD_CTRL(MX7D_PAD_SD1_DATA3__SD1_DATA3, USDHC_DATA_PAD_CTRL),
/* CD */
NEW_PAD_CTRL(MX7D_PAD_SD1_CD_B__GPIO5_IO0, GPIO_IN_PAD_CTRL),
/* WP */
NEW_PAD_CTRL(MX7D_PAD_SD1_WP__GPIO5_IO1, GPIO_IN_PAD_CTRL),
};
#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
#define USDHC1_WP_GPIO IMX_GPIO_NR(5, 1)
int tq_bb_board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
if (cfg->esdhc_base == USDHC1_BASE_ADDR)
ret = !gpio_get_value(USDHC1_CD_GPIO);
return ret;
}
int tq_bb_board_mmc_getwp(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
if (cfg->esdhc_base == USDHC1_BASE_ADDR)
ret = gpio_get_value(USDHC1_WP_GPIO);
return ret;
}
static struct fsl_esdhc_cfg mba7_usdhc_cfg = {
.esdhc_base = USDHC1_BASE_ADDR,
.max_bus_width = 4,
};
int tq_bb_board_mmc_init(struct bd_info *bis)
{
imx_iomux_v3_setup_multiple_pads(mba7_usdhc1_pads,
ARRAY_SIZE(mba7_usdhc1_pads));
gpio_request(USDHC1_CD_GPIO, "usdhc1-cd");
gpio_request(USDHC1_WP_GPIO, "usdhc1-wp");
gpio_direction_input(USDHC1_CD_GPIO);
gpio_direction_input(USDHC1_WP_GPIO);
mba7_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
if (fsl_esdhc_initialize(bis, &mba7_usdhc_cfg))
puts("Warning: failed to initialize SD\n");
return 0;
}
int tq_bb_board_early_init_f(void)
{
/* iomux and setup of uart */
mba7_setup_iomuxc_uart();
return 0;
}
/*
* This is done per baseboard to allow different implementations
*/
void board_boot_order(u32 *spl_boot_list)
{
enum boot_device bd;
/*
* try to get sd card slots in order:
* eMMC: on Module
* -> therefore index 0 for bootloader
* index n in kernel (controller instance 3) -> patches needed for
* alias indexing
* SD1: on Mainboard
* index n in kernel (controller instance 1) -> patches needed for
* alias indexing
* we assume to have a kernel patch that will present mmcblk dev
* indexed like controller devs
*/
puts("Boot: ");
bd = get_boot_device();
switch (bd) {
case MMC3_BOOT:
puts("USDHC3(eMMC)\n");
spl_boot_list[0] = BOOT_DEVICE_MMC1;
break;
case SD1_BOOT:
puts("USDHC1(SD)\n");
spl_boot_list[0] = BOOT_DEVICE_MMC2;
break;
case QSPI_BOOT:
puts("QSPI\n");
spl_boot_list[0] = BOOT_DEVICE_NOR;
break;
case USB_BOOT:
puts("USB\n");
spl_boot_list[0] = BOOT_DEVICE_BOARD;
break;
default:
/* Default - BOOT_DEVICE_MMC1 */
puts("WARN: unknown boot device, fallback to eMMC\n");
spl_boot_list[0] = BOOT_DEVICE_MMC1;
break;
}
}
int board_fit_config_name_match(const char *name)
{
char *config = NULL;
if (is_cpu_type(MXC_CPU_MX7S))
config = "imx7s-mba7";
else if (is_cpu_type(MXC_CPU_MX7D))
config = "imx7d-mba7";
if (strcmp(config, name))
return -EINVAL;
printf("Device tree: %s\n", name);
return 0;
}
board/tq/tqma7/spl_tqma7_ram.c
+171
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@@ -0,0 +1,171 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Feilke
*/
#include <config.h>
#include <hang.h>
#include <asm/arch/imx-regs.h>
#include <asm/mach-imx/iomux-v3.h>
#include <linux/sizes.h>
#include "../common/tq_som.h"
#define DDRC_RFSHTMG_512M 0x0020002B
#define DDRC_RFSHTMG_1G 0x00200045
#define DDRC_RFSHTMG_2G 0x0020005D
#define DDRC_ADDRMAP1_512M 0x00161616
#define DDRC_ADDRMAP1_1G 0x00171717
#define DDRC_ADDRMAP1_2G 0x00181818
#define DDRC_ADDRMAP6_512M 0x0F0F0404
#define DDRC_ADDRMAP6_1G 0x0F040404
#define DDRC_ADDRMAP6_2G 0x04040404
#define DDR_PHY_OFFSET_RD_CON0_512M 0x0B0B0B0B
#define DDR_PHY_OFFSET_RD_CON0_1G 0x0B0B0B0B
#define DDR_PHY_OFFSET_RD_CON0_2G 0x0A0A0A0A
#define DDR_PHY_OFFSET_WR_CON0_512M 0x06060606
#define DDR_PHY_OFFSET_WR_CON0_1G 0x06060606
#define DDR_PHY_OFFSET_WR_CON0_2G 0x04040404
static void tqma7_ddr_exit_retention(void)
{
/* Clear then set bit30 to ensure exit from DDR retention */
tq_som_init_write_reg(0x30360388, 0x40000000);
tq_som_init_write_reg(0x30360384, 0x40000000);
}
static void gpr_init(void)
{
/* reset default and enable GPR OCRAM EPDC */
tq_som_init_write_reg(0x30340004, 0x4F400005);
}
static void tqma7_ccgr_init(void)
{
tq_som_init_write_reg(0x30384130, 0x00000000); /* CCM_CCGR19 */
tq_som_init_write_reg(0x30340020, 0x00000178); /* IOMUXC_GPR_GPR8 */
tq_som_init_write_reg(0x30384130, 0x00000002); /* CCM_CCGR19 */
tq_som_init_write_reg(0x30790018, 0x0000000f); /* DDR_PHY_LP_CON0 */
/* wait for auto-ZQ calibration to complete */
tq_som_check_bits_set(0x307a0004, 0x1); /* DDRC_STAT */
}
static void ddr_init_error(const char *msg)
{
pr_err("%s", msg);
hang();
}
#define TQMA7_SELECT_DDR_VALUE(SIZE, NAME) \
((SIZE) == SZ_512M ? NAME ## _512M : \
((SIZE) == SZ_1G ? NAME ## _1G : \
((SIZE) == SZ_2G ? NAME ## _2G : \
(ddr_init_error("Invalid DDR RAM size detected"), 0))))
static void tqma7_init_ddr_controller(u32 size)
{
gpr_init();
/* TQMa7 DDR config */
/* TQMa7x DRAM Timing REV0201A */
/* DCD Code i.MX7D/S 528 MHz 512 MByte Samsung K4B2G1646F */
tq_som_init_write_reg(0x30360070, 0x0070302C); /*CCM_ANALOG_PLL_DDRx*/
tq_som_init_write_reg(0x30360090, 0x00000000); /*CCM_ANALOG_PLL_NUM*/
tq_som_init_write_reg(0x30360070, 0x0060302C); /*CCM_ANALOG_PLL_DDRx*/
tq_som_check_bits_set(0x30360070, 0x80000000);
tq_som_init_write_reg(0x30391000, 0x00000002); /*SRC_DDRC_RCR*/
tq_som_init_write_reg(0x307a0000, 0x01040001); /*DDRC_MSTR*/
tq_som_init_write_reg(0x307a01a0, 0x80400003); /*DDRC_DFIUPD0*/
tq_som_init_write_reg(0x307a01a4, 0x00100020); /*DDRC_DFIUPD1*/
tq_som_init_write_reg(0x307a01a8, 0x80100004); /*DDRC_DFIUPD2*/
tq_som_init_write_reg(0x307a0064, TQMA7_SELECT_DDR_VALUE(size, DDRC_RFSHTMG));
tq_som_init_write_reg(0x307a0490, 0x00000001); /*DDRC_MP_PCTRL_0*/
tq_som_init_write_reg(0x307a00d0, 0x00020081); /*DDRC_INIT0*/
tq_som_init_write_reg(0x307a00d4, 0x00680000); /*DDRC_INIT1*/
tq_som_init_write_reg(0x307a00dc, 0x09300004); /*DDRC_INIT3*/
tq_som_init_write_reg(0x307a00e0, 0x00480000); /*DDRC_INIT4*/
tq_som_init_write_reg(0x307a00e4, 0x00100004); /*DDRC_INIT5*/
tq_som_init_write_reg(0x307a00f4, 0x0000033F); /*DDRC_RANKCTL*/
tq_som_init_write_reg(0x307a0100, 0x090E0809); /*DDRC_DRAMTMG0*/
tq_som_init_write_reg(0x307a0104, 0x0007020E); /*DDRC_DRAMTMG1*/
tq_som_init_write_reg(0x307a0108, 0x03040407); /*DDRC_DRAMTMG2*/
tq_som_init_write_reg(0x307a010c, 0x00002006); /*DDRC_DRAMTMG3*/
tq_som_init_write_reg(0x307a0110, 0x04020304); /*DDRC_DRAMTMG4*/
tq_som_init_write_reg(0x307a0114, 0x03030202); /*DDRC_DRAMTMG5*/
tq_som_init_write_reg(0x307a0120, 0x00000803); /*DDRC_DRAMTMG8*/
tq_som_init_write_reg(0x307a0180, 0x00800020); /*DDRC_ZQCTL0*/
tq_som_init_write_reg(0x307a0190, 0x02098204); /*DDRC_DFITMG0*/
tq_som_init_write_reg(0x307a0194, 0x00030303); /*DDRC_DFITMG1*/
tq_som_init_write_reg(0x307a0200, 0x0000001F); /*DDRC_ADDRMAP0*/
tq_som_init_write_reg(0x307a0204, TQMA7_SELECT_DDR_VALUE(size, DDRC_ADDRMAP1));
tq_som_init_write_reg(0x307a020C, 0x00000000); /*DDRC_ADDRMAP3*/
tq_som_init_write_reg(0x307a0210, 0x00000F0F); /*DDRC_ADDRMAP4*/
tq_som_init_write_reg(0x307a0214, 0x04040404); /*DDRC_ADDRMAP5*/
tq_som_init_write_reg(0x307a0218, TQMA7_SELECT_DDR_VALUE(size, DDRC_ADDRMAP6));
tq_som_init_write_reg(0x307a0240, 0x06000604); /*DDRC_ODTCFG*/
tq_som_init_write_reg(0x307a0244, 0x00000001); /*DDRC_ODTMAP*/
tq_som_init_write_reg(0x30391000, 0x00000000); /*SRC_DDRC_RCR*/
tq_som_init_write_reg(0x30790000, 0x17420F40); /*DDR_PHY_PHY_CON0*/
tq_som_init_write_reg(0x30790004, 0x10210100); /*DDR_PHY_PHY_CON1*/
tq_som_init_write_reg(0x30790010, 0x00060807); /*DDR_PHY_PHY_CON4*/
tq_som_init_write_reg(0x307900b0, 0x1010007E); /*DDR_PHY_MDLL_CON0*/
tq_som_init_write_reg(0x3079009c, 0x00000924); /*DDR_PHY_DRVDS_CON0*/
tq_som_init_write_reg(0x30790020, TQMA7_SELECT_DDR_VALUE(size, DDR_PHY_OFFSET_RD_CON0));
tq_som_init_write_reg(0x30790030, TQMA7_SELECT_DDR_VALUE(size, DDR_PHY_OFFSET_WR_CON0));
tq_som_init_write_reg(0x30790050, 0x01000010); /*DDR_PHY_CMD_SDLL_CON0*/
tq_som_init_write_reg(0x30790050, 0x00000010); /*DDR_PHY_CMD_SDLL_CON0*/
tq_som_init_write_reg(0x307900c0, 0x0C407304); /*DDR_PHY_ZQ_CON0*/
tq_som_init_write_reg(0x307900c0, 0x0C447304); /*DDR_PHY_ZQ_CON0*/
tq_som_init_write_reg(0x307900c0, 0x0C447306); /*DDR_PHY_ZQ_CON0*/
tq_som_check_bits_set(0x307900c4, 0x1); /*ZQ Calibration is finished*/
tq_som_init_write_reg(0x307900c0, 0x0C447304); /*DDR_PHY_ZQ_CON0*/
tq_som_init_write_reg(0x307900c0, 0x0C407304); /*DDR_PHY_ZQ_CON0*/
tqma7_ccgr_init();
}
void tq_som_ram_init(void)
{
/* RAM sizes need to be in descending order */
static const u32 ram_sizes[] = {
#if IS_ENABLED(CONFIG_TQMA7_RAM_2G)
SZ_2G,
#endif
#if IS_ENABLED(CONFIG_TQMA7_RAM_1G)
SZ_1G,
#endif
#if IS_ENABLED(CONFIG_TQMA7_RAM_512M)
SZ_512M,
#endif
};
int i;
debug("SPL: tqma7 iomux ....\n");
tqma7_ddr_exit_retention();
for (i = 0; i < ARRAY_SIZE(ram_sizes); i++) {
tqma7_init_ddr_controller(ram_sizes[i]);
if (tq_som_ram_check_size(ram_sizes[i]))
break;
}
if (i < ARRAY_SIZE(ram_sizes)) {
debug("SPL: tqma7 ddr init done ...\n");
} else {
pr_err("Error: Invalid DDR RAM size\n");
hang();
}
}
board/tq/tqma7/tqma7.c
+96
View File
@@ -0,0 +1,96 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Markus Niebel, Steffen Doster
*/
#include <env.h>
#include <fdt_support.h>
#include <mtd_node.h>
#include <spi_flash.h>
#include <asm/bootm.h>
#include <asm/setup.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include "../common/tq_bb.h"
#include "../common/tq_som.h"
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
}
#if (!IS_ENABLED(CONFIG_SPL_BUILD))
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
if (IS_ENABLED(CONFIG_FSL_QSPI))
set_clk_qspi();
return tq_bb_board_init();
}
static const char *tqma7_get_boardname(void)
{
switch (get_cpu_type()) {
case MXC_CPU_MX7S:
return "TQMa7S";
case MXC_CPU_MX7D:
return "TQMa7D";
default:
return "??";
};
}
int board_late_init(void)
{
const char *bname = tqma7_get_boardname();
if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
struct tag_serialnr serialnr;
get_board_serial(&serialnr);
printf("UID: %08x%08x\n", serialnr.high, serialnr.low);
}
env_set_runtime("board_name", bname);
return tq_bb_board_late_init();
}
static u32 tqma7_get_board_rev(void)
{
/* REV.0100 is unsupported */
return 200;
}
int checkboard(void)
{
printf("Board: %s REV.%04u\n", tq_bb_get_boardname(), tqma7_get_board_rev());
return 0;
}
/*
* Device Tree Support
*/
#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT)
int ft_board_setup(void *blob, struct bd_info *bd)
{
tq_bb_ft_board_setup(blob, bd);
return 0;
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
#endif /* !IS_ENABLED(CONFIG_SPL_BUILD) */
board/tq/tqma7/tqma7.cfg
+26
View File
@@ -0,0 +1,26 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Markus Niebel, Steffen Doster
*
* Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
#include <config.h>
/*
* Set to sd even for QSPI boot on i.MX7, as i.MX7 uses offset 0x400 rather
* than 0x1000 for QSPI
*/
BOOT_FROM sd
#if IS_ENABLED(CONFIG_IMX_HAB)
CSF CONFIG_CSF_SIZE
#endif
board/tq/tqma7/tqma7.env
+35
View File
@@ -0,0 +1,35 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2024-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Feilke
*
* TQMa7x environment
*/
#include <env/tq/tq-imx-shared.env>
board=tqma7
boot_os=bootz "${kernel_addr_r}" - "${fdt_addr_r}"
emmc_bootp_start=TQMA7_MMC_UBOOT_SECTOR_START
emmc_dev=0
fdt_addr_r=TQMA7_FDT_ADDRESS
fdtoverlay_addr_r=FDT_OVERLAY_ADDR
image=zImage
kernel_addr_r=CONFIG_SYS_LOAD_ADDR
netdev=eth0
pxefile_addr_r=CONFIG_SYS_LOAD_ADDR
ramdisk_addr_r=TQMA7_INITRD_ADDRESS
sd_dev=1
uboot=u-boot-with-spl.imx
uboot_mmc_start=TQMA7_MMC_UBOOT_SECTOR_START
uboot_mmc_size=TQMA7_MMC_UBOOT_SECTOR_COUNT
uboot_spi_sector_size=TQMA7_SPI_FLASH_SECTOR_SIZE
uboot_spi_start=TQMA7_SPI_UBOOT_START
uboot_spi_size=TQMA7_SPI_UBOOT_SIZE
#ifdef CONFIG_FASTBOOT_UUU_SUPPORT
fastboot_partition_alias_all=CONFIG_FASTBOOT_FLASH_MMC_DEV:0
fastboot_raw_partition_bootloader=TQMA7_MMC_UBOOT_SECTOR_START TQMA7_MMC_UBOOT_SECTOR_COUNT mmcpart 1
fastbootcmd=fastboot usb 0
#endif
board/tq/tqma7/tqma7_mba7.c
+148
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@@ -0,0 +1,148 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Markus Niebel, Steffen Doster
*/
#include <env.h>
#include <errno.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch-mx7/imx-regs.h>
#include <asm/mach-imx/boot_mode.h>
#include "../common/tq_bb.h"
const char *tq_bb_get_boardname(void)
{
return "MBa7x";
}
#if !IS_ENABLED(CONFIG_SPL_BUILD)
static int mba7_setup_fec(int fec_id)
{
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
int ret;
switch (fec_id) {
case 0:
/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK, 0);
break;
case 1:
/* Use 125M anatop REF_CLK2 for ENET2, clear gpr1[14], gpr1[18]*/
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK |
IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK, 0);
break;
default:
printf("FEC%d: unsupported\n", fec_id);
return -EINVAL;
}
ret = set_clk_enet(ENET_125MHZ);
if (ret)
return ret;
return 0;
}
int tq_bb_board_init(void)
{
mba7_setup_fec(0);
if (!is_cpu_type(MXC_CPU_MX7S))
mba7_setup_fec(1);
return 0;
}
int tq_bb_board_late_init(void)
{
puts("Boot: ");
if (is_boot_from_usb()) {
puts("USB\n");
env_set_runtime("boot_dev", "mmc");
env_set_runtime("mmcdev", "0");
env_set_runtime("mmcblkdev", "0");
} else {
/*
* try to get sd card slots in order:
* eMMC: on Module
* -> therefore index 0 for bootloader
* index n in kernel (controller instance 3) -> patches needed for
* alias indexing
* SD1: on Mainboard
* index n in kernel (controller instance 1) -> patches needed for
* alias indexing
* we assume to have a kernel patch that will present mmcblk dev
* indexed like controller devs
*/
enum boot_device bd = get_boot_device();
switch (bd) {
case MMC3_BOOT:
puts("USDHC3(eMMC)\n");
env_set_runtime("boot_dev", "mmc");
env_set_runtime("mmcdev", "0");
env_set_runtime("mmcblkdev", "0");
break;
case SD1_BOOT:
puts("USDHC1(SD)\n");
env_set_runtime("boot_dev", "mmc");
env_set_runtime("mmcdev", "1");
env_set_runtime("mmcblkdev", "1");
break;
case QSPI_BOOT:
puts("QSPI\n");
env_set_runtime("boot_dev", "qspi");
env_set_runtime("mmcdev", "0");
env_set_runtime("mmcblkdev", "0");
break;
default:
printf("unhandled boot device %d\n", (int)bd);
env_set_runtime("mmcdev", "0");
env_set_runtime("mmcblkdev", "0");
}
}
if (!env_get("fdtfile")) {
/* provide default setting for fdtfile if nothing in env is set */
switch (get_cpu_type()) {
case MXC_CPU_MX7S:
env_set_runtime("fdtfile", "imx7s-mba7.dtb");
break;
case MXC_CPU_MX7D:
env_set_runtime("fdtfile", "imx7d-mba7.dtb");
break;
default:
debug("unknown CPU");
}
}
return 0;
}
int board_mmc_get_env_dev(int devno)
{
switch (devno) {
case 2:
/* eMMC */
return 0;
case 0:
/* SD card */
return 1;
default:
/* Unknown */
return 0;
}
}
#endif /* !IS_ENABLED(CONFIG_SPL_BUILD) */
common/memsize.c
+59
View File
@@ -127,6 +127,65 @@ long get_ram_size(long *base, long maxsize)
return (maxsize);
}
/**
* probe_ram_size_by_alias() - Detect RAM size using known alias addresses
* @checks: Array of RAM alias probe descriptors, terminated by a NULL
* @probe_addr entry
*
* Probe RAM size by writing a test pattern to each @probe_addr and checking
* whether the same pattern does not appear at the corresponding @alias_addr.
* This is useful on systems where address wrap-around does not alias to the
* base of memory in a linear way, so get_ram_size() cannot be used directly.
* It is also useful on systems where the base of the physical memory cannot
* be safely accessed, so get_ram_size() cannot be used at all.
*
* Return: The size associated with the first matching entry, or 0 if no match
* is found.
*/
long probe_ram_size_by_alias(const struct ram_alias_check *checks)
{
long save[2];
int dcache_en = 0;
long ret = 0;
if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
dcache_en = dcache_status();
while (checks->probe_addr && !ret) {
volatile long *d = checks->probe_addr;
volatile long *s = checks->alias_addr;
save[0] = *s;
save[1] = *d;
/* Ensure s is written and not cached */
if (dcache_en)
dcache_flush_invalidate(s);
*d = ~save[0];
sync();
if (dcache_en)
dcache_flush_invalidate(d);
if (*s != ~save[0])
ret = checks->size;
/* Restore content */
*d = save[1];
sync();
if (dcache_en)
dcache_flush_invalidate(d);
*s = save[0];
sync();
if (dcache_en)
dcache_flush_invalidate(s);
checks++;
}
return ret;
}
phys_size_t __weak get_effective_memsize(void)
{
phys_size_t ram_size = gd->ram_size;
configs/imx8mq_evk_defconfig
+10 -11
View File
@@ -4,12 +4,8 @@ CONFIG_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x600000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x200000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mq-evk"
CONFIG_TARGET_IMX8MQ_EVK=y
@@ -18,7 +14,7 @@ CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x187ff0
CONFIG_SPL_STACK=0x920000
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x180000
@@ -73,6 +69,7 @@ CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_REDUNDANT=y
@@ -80,31 +77,33 @@ CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_MMC_DEVICE_INDEX=1
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FEC"
CONFIG_SPL_DM=y
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
CONFIG_DFU_MMC=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY=y
CONFIG_PHY_IMX8MQ_USB=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_SPL_POWER_LEGACY=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_POWER_PFUZE100=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=n
CONFIG_SPL_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_POWER_I2C=y
CONFIG_SPL_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_TEE=y
configs/imx8mq_phanbell_defconfig
+7 -7
View File
@@ -7,9 +7,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-phanbell"
CONFIG_TARGET_IMX8MQ_PHANBELL=y
@@ -18,7 +15,7 @@ CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x187ff0
CONFIG_SPL_STACK=0x920000
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x180000
@@ -67,16 +64,17 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_MMC_DEVICE_INDEX=1
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FEC"
CONFIG_SPL_DM=y
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
@@ -84,14 +82,16 @@ CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_SPL_POWER_LEGACY=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_POWER_I2C=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
configs/imx8mq_reform2_defconfig
-1
View File
@@ -87,7 +87,6 @@ CONFIG_PHY=y
CONFIG_PHY_IMX8MQ_USB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_SPL_POWER_LEGACY=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
configs/imx943_evk_defconfig
+1
View File
@@ -109,6 +109,7 @@ CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
CONFIG_SPI_FLASH_STMICRO=y
configs/imx95_evk.config
+1
View File
@@ -120,6 +120,7 @@ CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MT35XU=y
CONFIG_PHYLIB=y
configs/kontron_pitx_imx8m_defconfig
+8 -8
View File
@@ -7,9 +7,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x300000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-kontron-pitx-imx8m"
CONFIG_TARGET_KONTRON_PITX_IMX8M=y
@@ -18,7 +15,7 @@ CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x187ff0
CONFIG_SPL_STACK=0x920000
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x180000
@@ -73,16 +70,17 @@ CONFIG_CMD_REGULATOR=y
CONFIG_CMD_HASH=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FEC"
CONFIG_SPL_DM=y
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
CONFIG_DFU_MMC=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
@@ -94,15 +92,17 @@ CONFIG_MII=y
CONFIG_PHY=y
CONFIG_PHY_IMX8MQ_USB=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_SPL_POWER_LEGACY=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_POWER_PFUZE100=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_SPL_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_POWER_I2C=y
CONFIG_SPL_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
CONFIG_RTC_RV8803=y
CONFIG_DM_SERIAL=y
configs/pico-imx8mq_defconfig
-1
View File
@@ -85,7 +85,6 @@ CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_SPL_POWER_LEGACY=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
configs/tqma7_common.config
+119
View File
@@ -0,0 +1,119 @@
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_ENV_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx7d-mba7"
CONFIG_TARGET_TQMA7=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_MAX_SIZE=0x100000
CONFIG_SF_DEFAULT_BUS=4
CONFIG_SPL=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_IMX_RDC=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x98000000
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
# CONFIG_EFI_LOADER is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_OF_BOARD_SETUP=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_SPL_MAX_SIZE=0xf000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_LICENSE=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_MD5SUM=y
CONFIG_MD5SUM_VERIFY=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
# CONFIG_SYS_ALT_MEMTEST_BITFLIP is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_MMC_SPEED_MODE_SET=y
CONFIG_CMD_MTD=y
CONFIG_CMD_SPI=y
CONFIG_CMD_TEMPERATURE=y
CONFIG_CMD_WDT=y
CONFIG_CMD_NFS=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=30bb0000.qspi"
CONFIG_MTDPARTS_DEFAULT="mtdparts=30bb0000.qspi:4m@0k(bootstream),64k@4096k(env0),64k@4160k(env1),-@6m(ubi)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_OF_UPSTREAM=y
CONFIG_OF_LIST="nxp/imx/imx7d-mba7 nxp/imx/imx7s-mba7"
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_USE_ROOTPATH=y
CONFIG_ROOTPATH="/srv/nfs"
CONFIG_BUTTON=y
CONFIG_BUTTON_GPIO=y
CONFIG_GPIO_HOG=y
CONFIG_DM_PCA953X=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0x3
CONFIG_SYS_I2C_MXC=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_BOOTDEV_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_MDIO=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS1307=y
CONFIG_CONS_INDEX=5
CONFIG_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_IMX_THERMAL=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
# CONFIG_WATCHDOG_AUTOSTART is not set
CONFIG_IMX_WATCHDOG=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
configs/tqma7_mba7_mmc_defconfig
+2
View File
@@ -0,0 +1,2 @@
#include <configs/tqma7_common.config>
#include <configs/tqma7_mmc.config>
configs/tqma7_mba7_qspi_defconfig
+2
View File
@@ -0,0 +1,2 @@
#include <configs/tqma7_common.config>
#include <configs/tqma7_qspi.config>
configs/tqma7_mba7_uuu_defconfig
+2
View File
@@ -0,0 +1,2 @@
#include <configs/tqma7_common.config>
#include <configs/tqma7_uuu.config>
configs/tqma7_mmc.config
+4
View File
@@ -0,0 +1,4 @@
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_ENV_OFFSET=0x100000
CONFIG_BOOTCOMMAND="run mmcboot; run nfsboot; run panicboot"
CONFIG_ENV_MMC_USE_DT=y
configs/tqma7_qspi.config
+7
View File
@@ -0,0 +1,7 @@
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_QSPI_BOOT=y
CONFIG_BOOTCOMMAND="run ubiboot; run nfsboot; run panicboot"
# CONFIG_ENV_IS_IN_MMC is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
configs/tqma7_uuu.config
+22
View File
@@ -0,0 +1,22 @@
CONFIG_SYS_MALLOC_LEN=0x2000000
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run fastbootcmd"
# CONFIG_ENV_IS_IN_MMC is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x84000000
CONFIG_FASTBOOT_BUF_SIZE=0x8000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_UUU_SUPPORT=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_SPL_USB_HOST=y
CONFIG_USB_MAX_CONTROLLER_COUNT=2
CONFIG_USB_GADGET=y
CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_SDP_LOADADDR=0x80800000
CONFIG_SPL_USB_SDP_SUPPORT=y
configs/verdin-imx95_defconfig
+183
View File
@@ -0,0 +1,183 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX9=y
CONFIG_TEXT_BASE=0x90200000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx95-verdin-wifi-dev"
CONFIG_TARGET_VERDIN_IMX95=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x204d6000
CONFIG_SPL_TEXT_BASE=0x20480000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x204d6000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SYS_LOAD_ADDR=0x90400000
CONFIG_WATCHDOG_TIMEOUT_MSECS=30000
CONFIG_SPL=y
CONFIG_SPL_RECOVER_DATA_SECTION=y
CONFIG_PCI=y
CONFIG_SYS_MEMTEST_START=0x90000000
CONFIG_SYS_MEMTEST_END=0xA0000000
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTSTD_FULL=y
CONFIG_BOOTDELAY=1
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="bootflow scan -b"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="test -n \"${fdtfile}\" || setenv fdtfile imx95-verdin-${variant}-${fdt_board}.dtb"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_BOARD_INIT is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x30000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/scmi/container.cfg"
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_HAVE_INIT_STACK=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x93200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_THERMAL=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="Verdin iMX95 # "
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MD5SUM=y
CONFIG_MD5SUM_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_READ=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_SYSBOOT=y
CONFIG_CMD_UUID=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_HASH=y
CONFIG_CMD_SCMI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_MMC_EMMC_HW_PARTITION=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eth0"
CONFIG_VERSION_VARIABLE=y
CONFIG_PROT_UDP=y
CONFIG_IP_DEFRAG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TFTP_BLOCKSIZE=4096
CONFIG_SYS_RX_ETH_BUFFER=8
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_SPL_CLK_CCF=y
CONFIG_CLK_CCF=y
CONFIG_CLK_SCMI=y
CONFIG_SPL_CLK_SCMI=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x90400000
CONFIG_FASTBOOT_BUF_SIZE=0x20000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_UUU_SUPPORT=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_SPL_FIRMWARE=y
# CONFIG_SCMI_AGENT_SMCCC is not set
CONFIG_IMX_SM_CPU=y
CONFIG_IMX_SM_LMM=y
CONFIG_GPIO_HOG=y
CONFIG_SPL_GPIO_HOG=y
CONFIG_IMX_RGPIO2P=y
CONFIG_DM_PCA953X=y
CONFIG_SPL_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_IMX_MU_MBOX=y
CONFIG_I2C_EEPROM=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_DM_MDIO=y
CONFIG_MII=y
CONFIG_FSL_ENETC=y
CONFIG_PHYLIB=y
CONFIG_PHY_TI_DP83867=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PHY_IMX8MQ_USB=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX_SCMI=y
CONFIG_POWER_DOMAIN=y
CONFIG_SCMI_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REMOTEPROC_IMX=y
CONFIG_DM_RNG=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_SPI=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Toradex"
CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
CONFIG_USB_GADGET_OS_DESCRIPTORS=y
CONFIG_SDP_LOADADDR=0x90400000
CONFIG_ULP_WATCHDOG=y
# CONFIG_SPL_SHA1 is not set
CONFIG_LZO=y
CONFIG_HEXDUMP=y
doc/board/index.rst
+1
View File
@@ -71,6 +71,7 @@ Board-specific doc
theobroma-systems/index
ti/index
toradex/index
tq/index
variscite/index
wexler/index
xen/index
doc/board/nxp/imx8mq_evk.rst
+2 -2
View File
@@ -45,11 +45,11 @@ Build U-Boot
$ make imx8mq_evk_defconfig
$ make
Burn the flash.bin to MicroSD card offset 33KB:
Burn the flash.bin to MicroSD card offset 32KB:
.. code-block:: bash
$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 conv=notrunc
$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc
Boot
----
doc/board/toradex/index.rst
+1
View File
@@ -16,3 +16,4 @@ Toradex
verdin-am62p
verdin-imx8mm
verdin-imx8mp
verdin-imx95
doc/board/toradex/verdin-imx95.rst
+171
View File
@@ -0,0 +1,171 @@
.. SPDX-License-Identifier: GPL-2.0-or-later
Verdin iMX95 Module
==========================
- SoM: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
- Carrier board: https://www.toradex.com/products/carrier-board/verdin-development-board-kit
Quick Start
-----------
- Setup environment
- Get ahab-container.img
- Get DDR PHY Firmware Images
- Get and Build OEI Images
- Get and Build System Manager Image
- Get and Build the ARM Trusted Firmware
- Build the Bootloader Image
- Boot
Setup environment
-----------------
Suggested current toolchains are ARM 14.3 (https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads):
- https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/binrel/arm-gnu-toolchain-14.3.rel1-x86_64-arm-none-linux-gnueabihf.tar.xz
- https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/binrel/arm-gnu-toolchain-14.3.rel1-x86_64-aarch64-none-linux-gnu.tar.xz
.. code-block:: console
$ export TOOLS=<path/to/directory/with/toolchains>
$ export CROSS_COMPILE_32=<path/to/arm/toolchain/bin/>arm-none-linux-gnueabihf-
$ export CROSS_COMPILE_64=<path/to/arm64/toolchain/bin/>aarch64-none-linux-gnu-
Get ahab-container.img
----------------------
Note: `$srctree` is the U-Boot source directory
.. code-block:: console
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-2.0.2-89161a8.bin
$ sh firmware-ele-imx-2.0.2-89161a8.bin --auto-accept
$ cp firmware-ele-imx-2.0.2-89161a8/mx95b0-ahab-container.img $(srctree)
Get DDR PHY Firmware Images
---------------------------
Note: `$srctree` is the U-Boot source directory
.. code-block:: console
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin
$ sh firmware-imx-8.28-994fa14.bin --auto-accept
$ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr4x*v202409.bin $(srctree)
Get and Build OEI Images
------------------------
Note: `$srctree` is the U-Boot source directory
Get OEI from: https://git.toradex.com/cgit/imx-oei-toradex.git/
branch: main
.. code-block:: console
$ git clone -b main https://git.toradex.com/cgit/imx-oei-toradex.git/
$ cd imx-oei-toradex
$ make board=toradex-verdin-imx95 oei=ddr DEBUG=1 r=B0 all
$ cp build/toradex-verdin-imx95/ddr/oei-m33-ddr.bin $(srctree)
The Makefile will set `DDR_CONFIG` automatically based on the selected silicon
revision.
Get and Build the System Manager Image
--------------------------------------
Note: `$srctree` is the U-Boot source directory
Get System Manager from: https://git.toradex.com/cgit/imx-sm-toradex.git/
branch: main
.. code-block:: console
$ git clone -b main https://git.toradex.com/cgit/imx-sm-toradex.git/
$ cd imx-sm-toradex
$ make config=verdin-imx95 all
$ cp build/verdin-imx95/m33_image.bin $(srctree)
Get and Build the ARM Trusted Firmware
--------------------------------------
Note: `$srctree` is the U-Boot source directory
Get ATF from: https://github.com/nxp-imx/imx-atf/
branch: lf_v2.12
.. code-block:: console
$ export CROSS_COMPILE=$CROSS_COMPILE_64
$ unset LDFLAGS
$ unset AS
$ git clone -b lf_v2.12 https://github.com/nxp-imx/imx-atf.git
$ cd imx-atf
$ make PLAT=imx95 bl31
$ cp build/imx95/release/bl31.bin $(srctree)
Build the Bootloader Image
--------------------------
.. code-block:: console
$ export CROSS_COMPILE=$CROSS_COMPILE_64
$ make verdin-imx95_defconfig
$ make
Flash to eMMC
-------------
.. code-block:: console
> tftpboot ${loadaddr} flash.bin
> setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
> mmc dev 0 1 && mmc write ${loadaddr} 0x0 ${blkcnt}
As a convenience, instead of the last two commands, one may also use the update
U-Boot wrapper:
.. code-block:: console
> run update_uboot
Boot
----
Boot sequence is:
* SPL ---> ATF (TF-A) ---> U-Boot proper
Output:
.. code-block:: console
U-Boot SPL 2026.04-00756-ge7053d7cab88 (Apr 15 2026 - 12:27:34 +0200)
SYS Boot reason: pmic, origin: -1, errid: -1
SYS shutdown reason: pmic, origin: -1, errid: -1
Trying to boot from MMC1
Primary set selected
Load image from MMC/SD 0xca000
NOTICE: BL31: v2.12.0(release):lf-6.12.20-2.0.0
NOTICE: BL31: Built : 17:34:12, Oct 21 2025
U-Boot 2026.04-00756-ge7053d7cab88 (Apr 15 2026 - 12:27:34 +0200)
CPU: NXP i.MX95 Rev2.0 A55 at 1800 MHz - invalid sensor data
DRAM: 7.8 GiB
Core: 323 devices, 28 uclasses, devicetree: separate
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... Reading from MMC(0)... OK
In: serial@44380000
Out: serial@44380000
Err: serial@44380000
Model: Toradex 0089 Verdin iMX95 Hexa 8GB WB IT V1.0B
Serial#: 12594936
BuildInfo:
- ELE firmware version 2.0.2-2a118457
Setting variant to wifi
Net: No ethernet found.
Hit any key to stop autoboot: 0
Verdin iMX95 #
doc/board/tq/index.rst
+12
View File
@@ -0,0 +1,12 @@
.. SPDX-License-Identifier: GPL-2.0-or-later or CC-BY-4.0
.. Copyright (c) 2024-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
.. D-82229 Seefeld, Germany.
TQ-Systems
==========
.. toctree::
:maxdepth: 2
tqma7
doc/board/tq/tqma7.rst
+77
View File
@@ -0,0 +1,77 @@
.. SPDX-License-Identifier: CC-BY-4.0
.. Copyright (c) 2020-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
.. D-82229 Seefeld, Germany.
########################################
U-Boot for the TQ-Systems TQMa7x modules
########################################
This file contains information for the port of
U-Boot to the TQ-Systems TQMa7x modules.
***********
Boot source
***********
The following boot sources are supported:
- SD/eMMC
- USB (SDP)
QSPI boot is functional but requires an additional prepended NXP header
image. This currently unsupported in u-boot.
********
Building
********
To build U-Boot for the TQ-Systems TQMa7x modules:
.. code-block:: bash
make tqma7_mba7_<boot>_defconfig
make
**boot** is a placeholder for the boot device:
+------+-----------+
| mmc | SD/eMMC |
+------+-----------+
| uuu | USB (SDP) |
+------+-----------+
The default build artifact is named ``u-boot-with-spl.imx``.
*****************************************
Serial Download Protocol (SDP) / USB boot
*****************************************
The complete system image can be programmed with ``uuu``
(https://github.com/nxp-imx/mfgtools) to eMMC.
Serial Download Protocol is supported on the Micro-B USB port (X5) of MBa7x.
The command ``fastboot usb 0`` is used to enable the fastboot gadget.
Build SDP enabled U-Boot image
==============================
.. code-block:: bash
make <som>_mba7_uuu_defconfig
make
Booting
=======
With UUU
.. code-block:: bash
uuu -b spl <UUU U-Boot image>
************
Support Wiki
************
See `TQ Embedded Wiki for TQMa7x <https://support.tq-group.com/en/arm/tqma7x>`_.
drivers/ddr/imx/imx9/Kconfig
+1 -1
View File
@@ -24,9 +24,9 @@ config IMX9_DRAM_INLINE_ECC
config SAVED_DRAM_TIMING_BASE
hex "Define the base address for saved dram timing"
default 0x2051C000
help
after DRAM is trained, need to save the dram related timming
info into memory for low power use.
default 0x2051C000
endmenu
drivers/ddr/imx/phy/helper.c
+13
View File
@@ -38,6 +38,8 @@ binman_sym_declare(ulong, ddr_2d_dmem_fw, image_pos);
binman_sym_declare(ulong, ddr_2d_dmem_fw, size);
#endif
binman_sym_declare(ulong, u_boot_spl, image_pos);
/* We need PHY iMEM PHY is 32KB padded */
void ddr_load_train_firmware(enum fw_type type)
{
@@ -49,6 +51,7 @@ void ddr_load_train_firmware(enum fw_type type)
unsigned long dmem_start;
unsigned long imem_len = IMEM_LEN, dmem_len = DMEM_LEN;
static enum fw_type last_type = -1;
unsigned long spl_start = 0;
/* If FW doesn't change, we can save the loading. */
if (last_type == type)
@@ -67,6 +70,9 @@ void ddr_load_train_firmware(enum fw_type type)
dmem_start = imem_start + imem_len;
if (BINMAN_SYMS_OK) {
if (IS_ENABLED(CONFIG_IMX8MQ))
spl_start = binman_sym(ulong, u_boot_spl, image_pos);
switch (type) {
case FW_1D_IMAGE:
imem_start = binman_sym(ulong, ddr_1d_imem_fw, image_pos);
@@ -83,6 +89,13 @@ void ddr_load_train_firmware(enum fw_type type)
#endif
break;
}
if (IS_ENABLED(CONFIG_IMX8MQ)) {
imem_start -= spl_start;
imem_start += CONFIG_SPL_TEXT_BASE;
dmem_start -= spl_start;
dmem_start += CONFIG_SPL_TEXT_BASE;
}
}
pr_from32 = imem_start;
drivers/net/fsl_enetc.c
+46 -11
View File
@@ -8,6 +8,7 @@
#include <clk.h>
#include <cpu_func.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <errno.h>
#include <fdt_support.h>
#include <malloc.h>
@@ -20,14 +21,21 @@
#include <linux/bug.h>
#include <linux/delay.h>
#include <linux/build_bug.h>
#include <linux/bitfield.h>
#include <power/regulator.h>
#include "fsl_enetc.h"
#ifdef CONFIG_ARCH_IMX9
#include <asm/mach-imx/sys_proto.h>
#include <cpu_func.h>
#include "fsl_enetc_xpcs_phy.c"
#else
static inline int xpcs_phy_usxgmii_pma_config(struct udevice *dev)
{
return 0;
}
#endif
#include "fsl_enetc.h"
#define ENETC_DRIVER_NAME "enetc_eth"
/*
@@ -454,19 +462,23 @@ static void enetc_setup_mac_iface(struct udevice *dev,
/* set up serdes for SXGMII */
static int enetc_init_sxgmii(struct udevice *dev)
{
struct enetc_priv *priv = dev_get_priv(dev);
if (!enetc_has_imdio(dev))
return 0;
/* Dev ability - SXGMII */
enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII);
if (enetc_is_imx95(dev)) {
xpcs_phy_usxgmii_pma_config(dev);
} else {
struct enetc_priv *priv = dev_get_priv(dev);
/* Restart PCS AN */
enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
ENETC_PCS_CR,
ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN);
/* Dev ability - SXGMII */
enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII);
/* Restart PCS AN */
enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
ENETC_PCS_CR,
ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN);
}
return 0;
}
@@ -523,6 +535,10 @@ static int enetc_config_phy(struct udevice *dev)
return -ENODEV;
supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full;
if (enetc_is_imx95(dev))
supported |= PHY_10G_FEATURES;
priv->phy->supported &= supported;
priv->phy->advertising &= supported;
@@ -537,12 +553,31 @@ static int enetc_probe(struct udevice *dev)
{
struct enetc_priv *priv = dev_get_priv(dev);
int res;
struct udevice *supply = NULL;
if (ofnode_valid(dev_ofnode(dev)) && !ofnode_is_enabled(dev_ofnode(dev))) {
enetc_dbg(dev, "interface disabled\n");
return -ENODEV;
}
if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
res = device_get_supply_regulator(dev, "serdes-supply",
&supply);
if (res && res != -ENOENT) {
printf("%s: device_get_supply_regulator failed: %d\n",
__func__, res);
return res;
}
if (supply) {
res = regulator_set_enable_if_allowed(supply, true);
if (res) {
printf("%s: Error enabling phy supply\n", dev->name);
return res;
}
}
}
priv->enetc_txbd = memalign(ENETC_BD_ALIGN,
sizeof(struct enetc_tx_bd) * ENETC_BD_CNT);
priv->enetc_rxbd = memalign(ENETC_BD_ALIGN,
drivers/net/fsl_enetc.h
+1
View File
@@ -205,6 +205,7 @@ struct enetc_data {
/* PCS / internal SoC PHY ID, it defaults to 0 on all interfaces */
#define ENETC_PCS_PHY_ADDR 0
#define ENETC_NON_PCS_PHY_ADDR 16
/* PCS registers */
#define ENETC_PCS_CR 0x00
drivers/net/fsl_enetc_xpcs_phy.c
+970
View File
@@ -0,0 +1,970 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2024 NXP
*/
#define XPCS_PHY_GLOBAL 0x0
#define XPCS_PHY_MPLLA 0x1
#define XPCS_PHY_MPLLB 0x2
#define XPCS_PHY_LANE 0x3
#define XPCS_PHY_MAC_ADAPTER 0x1f
#define XPCS_PHY_REG(x) (((x) & 0x1fffe) >> 1)
/* MAC ADAPTER */
#define MAC_ADAPTER_LOCK_PHY 0x200
#define MAC_ADAPTER_LOCK_MPLLA 0x204
#define MAC_ADAPTER_LOCK_MPLLB 0x208
#define MAC_ADAPTER_LOCK_ROM 0x20c
#define MAC_ADAPTER_LOCK_RAM 0x210
#define MAC_ADAPTER_LOCK_EVENT 0x214
#define MAC_ADAPTER_LOCK_LOCK BIT(7)
/* PMA */
#define PMA_RX_LSTS 0x10040
#define PMA_RX_LSTS_RX_VALID_0 BIT(12)
#define PMA_MP_12G_16G_25G_TX_GENCTRL0 0x10060
#define PMA_TX_GENCTRL0_TX_RST_0 BIT(8)
#define PMA_TX_GENCTRL0_TX_DT_EN_0 BIT(12)
#define PMA_MP_12G_16G_25G_TX_GENCTRL1 0x10062
#define PMA_TX_GENCTRL1_VBOOST_EN_0 BIT(4)
#define PMA_TX_GENCTRL1_VBOOST_LVL_MASK GENMASK(10, 8)
#define PMA_TX_GENCTRL1_VBOOST_LVL(x) (((x) << 8) & GENMASK(10, 8))
#define PMA_TX_GENCTRL1_TX_CLK_RDY_0 BIT(12)
#define PMA_MP_12G_16G_TX_GENCTRL2 0x10064
#define PMA_TX_GENCTRL2_TX_REQ_0 BIT(0)
#define PMA_TX_GENCTRL2_TX0_WIDTH_MASK GENMASK(9, 8)
#define PMA_TX_GENCTRL2_TX0_WIDTH(x) (((x) << 8) & GENMASK(9, 8))
#define PMA_MP_12G_16G_25G_TX_BOOST_CTRL 0x10066
#define PMA_TX_BOOST_CTRL_TX0_IBOOST_MASK GENMASK(3, 0)
#define PMA_TX_BOOST_CTRL_TX0_IBOOST(x) ((x) & GENMASK(3, 0))
#define PMA_MP_12G_16G_25G_TX_RATE_CTRL 0x10068
#define PMA_TX_RATE_CTRL_TX0_RATE_MASK GENMASK(2, 0)
#define PMA_TX_RATE_CTRL_TX0_RATE(x) ((x) & GENMASK(2, 0))
#define PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL 0x1006A
#define PMA_POWER_STATE_CTRL_TX0_PSTATE_MASK GENMASK(1, 0)
#define PMA_POWER_STATE_CTRL_TX0_PSTATE(x) ((x) & GENMASK(1, 0))
#define PMA_POWER_STATE_CTRL_TX_DISABLE_0 BIT(8)
#define PMA_MP_12G_16G_25G_TX_EQ_CTRL0 0x1006C
#define PMA_TX_EQ_CTRL0_TX_EQ_PRE_MASK GENMASK(5, 0)
#define PMA_TX_EQ_CTRL0_TX_EQ_PRE(x) ((x) & GENMASK(5, 0))
#define PMA_TX_EQ_CTRL0_TX_EQ_MAIN_MASK GENMASK(13, 8)
#define PMA_TX_EQ_CTRL0_TX_EQ_MAIN(x) (((x) << 8) & GENMASK(13, 8))
#define PMA_MP_12G_16G_25G_TX_EQ_CTRL1 0x1006E
#define PMA_TX_EQ_CTRL1_TX_EQ_POST_MASK GENMASK(5, 0)
#define PMA_TX_EQ_CTRL1_TX_EQ_POST(x) ((x) & GENMASK(5, 0))
#define PMA_MP_16G_25G_TX_MISC_CTRL0 0x1007C
#define PMA_TX_MISC_CTRL0_TX0_MISC_MASK GENMASK(7, 0)
#define PMA_TX_MISC_CTRL0_TX0_MISC(x) ((x) & GENMASK(7, 0))
#define PMA_MP_12G_16G_25G_RX_GENCTRL0 0x100A0
#define PMA_RX_GENCTRL0_RX_DT_EN_0 BIT(8)
#define PMA_MP_12G_16G_25G_RX_GENCTRL1 0x100A2
#define PMA_RX_GENCTRL1_RX_RST_0 BIT(4)
#define PMA_RX_GENCTRL1_RX_TERM_ACDC_0 BIT(8)
#define PMA_RX_GENCTRL1_RX_DIV16P5_CLK_EN_0 BIT(12)
#define PMA_MP_12G_16G_RX_GENCTRL2 0x100A4
#define PMA_RX_GENCTRL2_RX_REQ_0 BIT(0)
#define PMA_RX_GENCTRL2_RX0_WIDTH_MASK GENMASK(9, 8)
#define PMA_RX_GENCTRL2_RX0_WIDTH(x) (((x) << 8) & GENMASK(9, 8))
#define PMA_MP_12G_16G_RX_GENCTRL3 0x100A6
#define PMA_RX_GENCTRL3_LOS_TRSHLD_0_MASK GENMASK(2, 0)
#define PMA_RX_GENCTRL3_LOS_TRSHLD_0(x) ((x) & GENMASK(2, 0))
#define PMA_RX_GENCTRL3_LOS_LFPS_EN_0 BIT(12)
#define PMA_MP_12G_16G_25G_RX_RATE_CTRL 0x100A8
#define PMA_RX_RATE_CTRL_RX0_RATE_MASK GENMASK(1, 0)
#define PMA_RX_RATE_CTRL_RX0_RATE(x) ((x) & GENMASK(1, 0))
#define PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL 0x100AA
#define PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK GENMASK(1, 0)
#define PMA_RX_POWER_STATE_CTRL_RX0_PSTATE(x) ((x) & GENMASK(1, 0))
#define PMA_RX_POWER_STATE_CTRL_RX_DISABLE_0 BIT(8)
#define PMA_MP_12G_16G_25G_RX_CDR_CTRL 0x100AC
#define PMA_RX_CDR_CTRL_CDR_SSC_EN_0 BIT(4)
#define PMA_MP_12G_16G_25G_RX_ATTN_CTRL 0x100AE
#define PMA_RX_ATTN_CTRL_RX0_EQ_ATT_LVL_MASK GENMASK(2, 0)
#define PMA_RX_ATTN_CTRL_RX0_EQ_ATT_LVL(x) ((x) & GENMASK(2, 0))
#define PMA_MP_16G_25G_RX_EQ_CTRL0 0x100B0
#define PMA_RX_EQ_CTRL0_CTLE_BOOST_0_MASK GENMASK(4, 0)
#define PMA_RX_EQ_CTRL0_CTLE_BOOST_0(x) ((x) & GENMASK(4, 0))
#define PMA_RX_EQ_CTRL0_CTLE_POLE_0_MASK GENMASK(6, 5)
#define PMA_RX_EQ_CTRL0_CTLE_POLE_0(x) (((x) << 5) & GENMASK(6, 5))
#define PMA_RX_EQ_CTRL0_VGA2_GAIN_0_MASK GENMASK(10, 8)
#define PMA_RX_EQ_CTRL0_VGA2_GAIN_0(x) (((x) << 8) & GENMASK(10, 8))
#define PMA_RX_EQ_CTRL0_VGA1_GAIN_0_MASK GENMASK(14, 12)
#define PMA_RX_EQ_CTRL0_VGA1_GAIN_0(x) (((x) << 12) & GENMASK(14, 12))
#define PMA_MP_12G_16G_25G_RX_EQ_CTRL4 0x100B8
#define PMA_RX_EQ_CTRL4_CONT_ADAPT_0 BIT(0)
#define PMA_RX_EQ_CTRL4_RX_AD_REQ BIT(12)
#define PMA_MP_16G_25G_RX_EQ_CTRL5 0x100BA
#define PMA_RX_EQ_CTRL5_RX_ADPT_SEL_0 BIT(0)
#define PMA_RX_EQ_CTRL5_RX0_ADPT_MODE_MASK GENMASK(5, 4)
#define PMA_RX_EQ_CTRL5_RX0_ADPT_MODE(x) (((x) << 4) & GENMASK(5, 4))
#define PMA_MP_12G_16G_25G_DFE_TAP_CTRL0 0x100BC
#define PMA_DFE_TAP_CTRL0_DFE_TAP1_0_MASK GENMASK(7, 0)
#define PMA_DFE_TAP_CTRL0_DFE_TAP1_0(x) ((x) & GENMASK(7, 0))
#define PMA_MP_16G_RX_CDR_CTRL1 0x100C8
#define PMA_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0 BIT(0)
#define PMA_RX_CDR_CTRL1_VCO_STEP_CTRL_0 BIT(4)
#define PMA_RX_CDR_CTRL1_VCO_FRQBAND_0_MASK GENMASK(9, 8)
#define PMA_RX_CDR_CTRL1_VCO_FRQBAND_0(x) (((x) << 8) & GENMASK(9, 8))
#define PMA_MP_16G_25G_RX_PPM_CTRL0 0x100CA
#define PMA_RX_PPM_CTRL0_RX0_CDR_PPM_MAX_MASK GENMASK(4, 0)
#define PMA_RX_PPM_CTRL0_RX0_CDR_PPM_MAX(x) ((x) & GENMASK(4, 0))
#define PMA_MP_16G_25G_RX_GENCTRL4 0x100D0
#define PMA_RX_GENCTRL4_RX_DFE_BYP_0 BIT(8)
#define PMA_MP_16G_25G_RX_MISC_CTRL0 0x100D2
#define PMA_RX_MISC_CTRL0_RX0_MISC_MASK GENMASK(7, 0)
#define PMA_RX_MISC_CTRL0_RX0_MISC(x) ((x) & GENMASK(7, 0))
#define PMA_MP_16G_25G_RX_IQ_CTRL0 0x100D6
#define PMA_RX_IQ_CTRL0_RX0_MARGIN_IQ_MASK GENMASK(6, 0)
#define PMA_RX_IQ_CTRL0_RX0_MARGIN_IQ(x) ((x) & GENMASK(6, 0))
#define PMA_RX_IQ_CTRL0_RX0_DELTA_IQ_MASK GENMASK(11, 8)
#define PMA_RX_IQ_CTRL0_RX0_DELTA_IQ(x) (((x) << 8) & GENMASK(11, 8))
#define PMA_MP_12G_16G_25G_MPLL_CMN_CTRL 0x100E0
#define PMA_MPLL_CMN_CTRL_MPLL_EN_0 BIT(0)
#define PMA_MPLL_CMN_CTRL_MPLLB_SEL_0 BIT(4)
#define PMA_MP_12G_16G_MPLLA_CTRL0 0x100E2
#define PMA_MPLLA_CTRL0_MPLLA_MULTIPLIER_MASK GENMASK(7, 0)
#define PMA_MPLLA_CTRL0_MPLLA_MULTIPLIER(x) ((x) & GENMASK(7, 0))
#define PMA_MP_16G_MPLLA_CTRL1 0x100E4
#define PMA_MPLLA_CTRL1_MPLLA_SSC_EN BIT(0)
#define PMA_MPLLA_CTRL1_MPLLA_SSC_CLK_SEL BIT(4)
#define PMA_MPLLA_CTRL1_MPLLA_FRACN_CTRL_MASK GENMASK(15, 5)
#define PMA_MPLLA_CTRL1_MPLLA_FRACN_CTRL(x) (((x) << 5) & GENMASK(15, 5))
#define PMA_MP_12G_16G_MPLLA_CTRL2 0x100E6
#define PMA_MPLLA_CTRL2_MPLLA_DIV_MULT_MASK GENMASK(6, 0)
#define PMA_MPLLA_CTRL2_MPLLA_DIV_MULT(x) ((x) & GENMASK(6, 0))
#define PMA_MPLLA_CTRL2_MPLLA_DIV_CLK_EN BIT(7)
#define PMA_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN BIT(8)
#define PMA_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN BIT(9)
#define PMA_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN BIT(10)
#define PMA_MPLLA_CTRL2_MPLLA_TX_CLK_DIV_MASK GENMASK(12, 11)
#define PMA_MPLLA_CTRL2_MPLLA_TX_CLK_DIV(x) (((x) << 11) & GENMASK(12, 11))
#define PMA_MP_16G_MPLLA_CTRL3 0x100EE
#define PMA_MPLLA_CTRL3_MPLLA_BANDWIDTH_MASK GENMASK(15, 0)
#define PMA_MPLLA_CTRL3_MPLLA_BANDWIDTH(x) ((x) & GENMASK(15, 0))
#define PMA_MP_16G_MPLLA_CTRL4 0x100F2
#define PMA_MPLLA_CTRL4_MPLLA_SSC_FRQ_CNT_INT_MASK GENMASK(11, 0)
#define PMA_MPLLA_CTRL4_MPLLA_SSC_FRQ_CNT_INT(x) ((x) & GENMASK(11, 0))
#define PMA_MP_16G_MPLLA_CTRL5 0x100F4
#define PMA_MPLLA_CTRL5_MPLLA_SSC_FRQ_CNT_PK_MASK GENMASK(7, 0)
#define PMA_MPLLA_CTRL5_MPLLA_SSC_FRQ_CNT_PK(x) ((x) & GENMASK(7, 0))
#define PMA_MPLLA_CTRL5_MPLLA_SSC_SPD_EN BIT(8)
#define PMA_MP_12G_16G_25G_MISC_CTRL0 0x10120
#define PMA_MISC_CTRL0_RX_VREF_CTRL_MASK GENMASK(12, 8)
#define PMA_MISC_CTRL0_RX_VREF_CTRL(x) (((x) << 8) & GENMASK(12, 8))
#define PMA_MP_12G_16G_25G_REF_CLK_CTRL 0x10122
#define PMA_REF_CLK_CTRL_REF_CLK_DIV2 BIT(2)
#define PMA_REF_CLK_CTRL_REF_RANGE_MASK GENMASK(5, 3)
#define PMA_REF_CLK_CTRL_REF_RANGE(x) (((x) << 3) & GENMASK(5, 3))
#define PMA_REF_CLK_CTRL_REF_MPLLA_DIV2 BIT(6)
#define PMA_MP_12G_16G_25G_VCO_CAL_LD0 0x10124
#define PMA_VCO_CAL_LD0_VCO_LD_VAL_0_MASK GENMASK(12, 0)
#define PMA_VCO_CAL_LD0_VCO_LD_VAL_0(x) ((x) & GENMASK(12, 0))
#define PMA_MP_16G_25G_VCO_CAL_REF0 0x1012C
#define PMA_VCO_CAL_REF0_VCO_REF_LD_0_MASK GENMASK(6, 0)
#define PMA_VCO_CAL_REF0_VCO_REF_LD_0(x) ((x) & GENMASK(6, 0))
#define PMA_MP_12G_16G_25G_MISC_STS 0x10130
#define PMA_MISC_STS_RX_ADPT_ACK BIT(12)
#define PMA_MP_12G_16G_25G_SRAM 0x10136
#define PMA_SRAM_INIT_DN BIT(0)
#define PMA_SRAM_EXT_LD_DN BIT(1)
#define PMA_MP_16G_25G_MISC_CTRL2 0x10138
#define PMA_MISC_CTRL2_SUP_MISC_MASK GENMASK(7, 0)
#define PMA_MISC_CTRL2_SUP_MISC(x) ((x) & GENMASK(7, 0))
/* PCS */
#define PCS_CTRL1 0x0
#define PCS_CTRL1_RESET BIT(15)
#define PCS_CTRL2 0xE
#define PCS_CTRL2_PCS_TYPE_SEL_MASK GENMASK(3, 0)
#define PCS_CTRL2_PCS_TYPE_SEL(x) ((x) & GENMASK(3, 0))
#define PCS_DIG_CTRL1 0x10000
#define PCS_DIG_CTRL1_USXG_EN BIT(9)
#define PCS_DIG_CTRL1_USRA_RST BIT(10)
#define PCS_DIG_CTRL1_VR_RST BIT(15)
#define PCS_DEBUG_CTRL 0x1000A
#define PCS_DEBUG_CTRL_SUPRESS_LOS_DET BIT(4)
#define PCS_DEBUG_CTRL_RX_DT_EN_CTL BIT(6)
#define PCS_DEBUG_CTRL_TX_PMBL_CTL BIT(8)
#define PCS_KR_CTRL1 0x1000E
#define PCS_KR_CTRL1_USXG_MODE_MASK GENMASK(12, 10)
#define PCS_KR_CTRL1_USXG_MODE(x) (((x) << 10) & GENMASK(12, 10))
/* VS MII MMD */
#define MII_CTRL 0x0
#define MII_CTRL_SS5 BIT(5)
#define MII_CTRL_SS6 BIT(6)
#define MII_CTRL_AN_ENABLE BIT(12)
#define MII_CTRL_SS13 BIT(13)
#define MII_DIG_CTRL1 0x10000
#define MII_DIG_CTRL1_CL37_TMR_OVR_RIDE BIT(3)
#define MII_AN_CTRL 0x10002
#define MII_AN_CTRL_MII_AN_INTR_EN BIT(0)
#define MII_AN_CTRL_TX_CONFIG BIT(3)
#define MII_AN_INTR_STS 0x10004
#define MII_AN_INTR_STS_CL37_ANCMPLT_INTR BIT(0)
#define MII_LINK_TIMER_CTRL 0x10014
#define MII_LINK_TIMER_CTRL_CL37_LINK_TIME_MASK GENMASK(15, 0)
#define MII_LINK_TIMER_CTRL_CL37_LINK_TIME(x) ((x) & GENMASK(15, 0))
/* E16 MEM MAP */
#define IDCODE_LO 0x0
#define IDCODE_HI 0x4
#define GLOBAL_CTRL_EX_0 0x114
#define GLOBAL_CTRL_EX_0_PHY_SRAM_BYPASS BIT(0)
#define L0_RX_VCO_OVRD_OUT_0 0x20c
#define L0_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_FREQ_TUNE_MASK GENMASK(12, 3)
#define L0_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_FREQ_TUNE(x) (((x) << 3) & GENMASK(12, 3))
#define L0_RX_VCO_OVRD_OUT_0_RX_CDR_FREQ_TUNE_OVRD_EN BIT(15)
#define L0_RX_VCO_OVRD_OUT_2 0x214
#define L0_RX_VCO_OVRD_OUT_2_RX_ANA_CDR_FREQ_TUNE_CLK BIT(0)
static int enetc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg);
static int enetc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, u16 val);
int xpcs_read(struct udevice *dev, int devaddr, u32 reg)
{
struct enetc_priv *priv = dev_get_priv(dev);
return enetc_mdio_read(&priv->imdio, ENETC_PCS_PHY_ADDR, devaddr, reg);
}
int xpcs_write(struct udevice *dev, int devaddr, u32 reg, u16 val)
{
struct enetc_priv *priv = dev_get_priv(dev);
return enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, devaddr, reg, val);
}
int xpcs_phy_read(struct udevice *dev, int devaddr, u32 reg)
{
struct enetc_priv *priv = dev_get_priv(dev);
return enetc_mdio_read(&priv->imdio, ENETC_NON_PCS_PHY_ADDR, devaddr, reg);
}
int xpcs_phy_write(struct udevice *dev, int devaddr, u32 reg, u16 val)
{
struct enetc_priv *priv = dev_get_priv(dev);
return enetc_mdio_write(&priv->imdio, ENETC_NON_PCS_PHY_ADDR, devaddr, reg, val);
}
int xpcs_phy_read_pma(struct udevice *dev, u32 reg)
{
return xpcs_read(dev, MDIO_MMD_PMAPMD, XPCS_PHY_REG(reg));
}
int xpcs_phy_write_pma(struct udevice *dev, int reg, u16 val)
{
return xpcs_write(dev, MDIO_MMD_PMAPMD, XPCS_PHY_REG(reg), val);
}
int xpcs_phy_usxgmii_init_seq_2(struct udevice *dev)
{
ulong begin;
u16 val;
/* Seq 2.1 Keep preamble data */
val = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DEBUG_CTRL));
val |= PCS_DEBUG_CTRL_TX_PMBL_CTL;
xpcs_write(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DEBUG_CTRL), val);
/* Seq 2.2 Power up MPLLA to P1 state */
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL);
val = u16_replace_bits(val, 2, PMA_POWER_STATE_CTRL_TX0_PSTATE_MASK);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL);
val |= PMA_MPLL_CMN_CTRL_MPLL_EN_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, val);
/* Seq 2.3 Assert request of transmitand receive */
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2);
val |= PMA_TX_GENCTRL2_TX_REQ_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);
val |= PMA_RX_GENCTRL2_RX_REQ_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2, val);
/* Seq 2.4 Poll for acknowledge */
begin = get_timer(0);
do {
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2);
if (get_timer(begin) > 500) {
dev_err(dev, "Polling timeout, line: %d\n", __LINE__);
goto timeout;
}
mdelay(10);
} while (val & PMA_TX_GENCTRL2_TX_REQ_0);
begin = get_timer(0);
do {
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);
if (get_timer(begin) > 500) {
dev_err(dev, "Polling timeout, line: %d\n", __LINE__);
goto timeout;
}
mdelay(10);
} while (val & PMA_RX_GENCTRL2_RX_REQ_0);
/* Seq 2.5 Turn transmit to P0 state */
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL);
val = u16_replace_bits(val, 0, PMA_POWER_STATE_CTRL_TX0_PSTATE_MASK);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0);
val &= ~PMA_TX_GENCTRL0_TX_RST_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL);
val &= ~PMA_POWER_STATE_CTRL_TX_DISABLE_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL);
val |= PMA_MPLL_CMN_CTRL_MPLL_EN_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, val);
/* Seq 2.6 Turn receive to P0 state */
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1);
val &= ~PMA_RX_GENCTRL1_RX_RST_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL);
val &= ~PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK;
val &= ~PMA_RX_POWER_STATE_CTRL_RX_DISABLE_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL);
val &= ~PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK;
val &= ~PMA_RX_POWER_STATE_CTRL_RX_DISABLE_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val);
/* Seq 2.7 Enable transmitter output driver in the PHY */
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0);
val |= PMA_TX_GENCTRL0_TX_DT_EN_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0, val);
/* Seq 2.8 Enable receiver data output from PHY */
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0);
val |= PMA_RX_GENCTRL0_RX_DT_EN_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0, val);
/* Seq 2.9 Assert request of transmit and receive */
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2);
val |= PMA_TX_GENCTRL2_TX_REQ_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);
val |= PMA_RX_GENCTRL2_RX_REQ_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2, val);
/* Seq 2.10 Poll for acknowledge */
begin = get_timer(0);
do {
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2);
if (get_timer(begin) > 500) {
dev_err(dev, "Polling timeout, line: %d\n", __LINE__);
goto timeout;
}
mdelay(10);
schedule();
} while (val & PMA_TX_GENCTRL2_TX_REQ_0);
begin = get_timer(0);
do {
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);
if (get_timer(begin) > 500) {
dev_err(dev, "Polling timeout, line: %d\n", __LINE__);
goto timeout;
}
mdelay(10);
schedule();
} while (val & PMA_RX_GENCTRL2_RX_REQ_0);
return 0;
timeout:
return -ETIMEDOUT;
}
void xpcs_phy_reg_lock(struct udevice *dev)
{
u16 val;
ulong begin;
if (xpcs_phy_read(dev, XPCS_PHY_MAC_ADAPTER, XPCS_PHY_REG(MAC_ADAPTER_LOCK_PHY)) & MAC_ADAPTER_LOCK_LOCK)
return;
xpcs_phy_write(dev, XPCS_PHY_MAC_ADAPTER, XPCS_PHY_REG(MAC_ADAPTER_LOCK_PHY), MAC_ADAPTER_LOCK_LOCK);
xpcs_phy_write(dev, XPCS_PHY_MAC_ADAPTER, XPCS_PHY_REG(MAC_ADAPTER_LOCK_MPLLA), MAC_ADAPTER_LOCK_LOCK);
xpcs_phy_write(dev, XPCS_PHY_MAC_ADAPTER, XPCS_PHY_REG(MAC_ADAPTER_LOCK_MPLLB), MAC_ADAPTER_LOCK_LOCK);
xpcs_phy_write(dev, XPCS_PHY_MAC_ADAPTER, XPCS_PHY_REG(MAC_ADAPTER_LOCK_ROM), MAC_ADAPTER_LOCK_LOCK);
xpcs_phy_write(dev, XPCS_PHY_MAC_ADAPTER, XPCS_PHY_REG(MAC_ADAPTER_LOCK_RAM), MAC_ADAPTER_LOCK_LOCK);
begin = get_timer(0);
do {
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_SRAM);
if (get_timer(begin) > 500) {
dev_err(dev, "Polling timeout, line: %d\n", __LINE__);
goto timeout;
}
mdelay(10);
} while (!(val & PMA_SRAM_INIT_DN));
/* Work around */
// xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_SRAM, PMA_SRAM_EXT_LD_DN);
xpcs_phy_write(dev, XPCS_PHY_GLOBAL, XPCS_PHY_REG(GLOBAL_CTRL_EX_0), GLOBAL_CTRL_EX_0_PHY_SRAM_BYPASS);
begin = get_timer(0);
do {
val = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_CTRL1));
if (get_timer(begin) > 500) {
dev_err(dev, "Polling timeout, line: %d\n", __LINE__);
goto timeout;
}
mdelay(10);
} while (val & PCS_CTRL1_RESET);
mdelay(1);
timeout:
return;
}
int xpcs_phy_usxgmii_pma_config(struct udevice *dev)
{
ulong begin;
u16 val;
xpcs_phy_reg_lock(dev);
/* 1.6 Turn off C37 auto-negotiation */
val = xpcs_read(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_CTRL));
val &= ~MII_CTRL_AN_ENABLE;
xpcs_write(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_CTRL), val);
/* 1.7 Assert tx_reset and rx_reset*/
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0);
val |= PMA_TX_GENCTRL0_TX_RST_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1);
val |= PMA_RX_GENCTRL1_RX_RST_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val);
/* 1.8 Wait for more than 1us */
udelay(5);
/* 1.9 Deassert tx_reset and rx_reset*/
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0);
val &= ~PMA_TX_GENCTRL0_TX_RST_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1);
val &= ~PMA_RX_GENCTRL1_RX_RST_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val);
/* 1.10 Power down MPLLA */
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL);
val = u16_replace_bits(val, 3, PMA_POWER_STATE_CTRL_TX0_PSTATE_MASK);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL);
val &= ~PMA_MPLL_CMN_CTRL_MPLL_EN_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0);
val &= ~PMA_TX_GENCTRL0_TX_DT_EN_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0, val);
/* 1.11 Change RX0 power state to P2 */
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0);
val &= ~PMA_RX_GENCTRL0_RX_DT_EN_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0, val);
/* TODO: check if it is needed */
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL);
val = u16_replace_bits(val, 1, PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL);
val = u16_replace_bits(val, 3, PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val);
/* 1.12 Assert request of transmit and receive */
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2);
val |= PMA_TX_GENCTRL2_TX_REQ_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);
val |= PMA_RX_GENCTRL2_RX_REQ_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2, val);
/* 1.13 Poll for acknlowledge */
begin = get_timer(0);
do {
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2);
if (get_timer(begin) > 500) {
dev_err(dev, "Polling timeout, line: %d\n", __LINE__);
goto timeout;
}
mdelay(10);
} while (val & PMA_TX_GENCTRL2_TX_REQ_0);
begin = get_timer(0);
do {
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);
if (get_timer(begin) > 500) {
dev_err(dev, "Polling timeout, line: %d\n", __LINE__);
goto timeout;
}
mdelay(10);
} while (val & PMA_RX_GENCTRL2_RX_REQ_0);
/* 2 Config MPLL for 10G XGMII */
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_REF_CLK_CTRL);
val = u16_replace_bits(val, 6, PMA_REF_CLK_CTRL_REF_RANGE_MASK);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_REF_CLK_CTRL, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_REF_CLK_CTRL);
val &= ~PMA_REF_CLK_CTRL_REF_CLK_DIV2;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_REF_CLK_CTRL, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_REF_CLK_CTRL);
val |= PMA_REF_CLK_CTRL_REF_MPLLA_DIV2;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_REF_CLK_CTRL, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2);
val &= ~PMA_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2);
val |= PMA_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2);
val |= PMA_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2);
val &= ~PMA_MPLLA_CTRL2_MPLLA_TX_CLK_DIV_MASK;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2);
val |= PMA_MPLLA_CTRL2_MPLLA_DIV_CLK_EN;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2);
val = u16_replace_bits(val, 5, PMA_MPLLA_CTRL2_MPLLA_DIV_MULT_MASK);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_MPLLA_CTRL1);
val &= ~PMA_MPLLA_CTRL1_MPLLA_SSC_EN;
xpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL1, val);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_MPLLA_CTRL1);
val &= ~PMA_MPLLA_CTRL1_MPLLA_SSC_CLK_SEL;
xpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL1, val);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_MPLLA_CTRL5);
val &= ~PMA_MPLLA_CTRL5_MPLLA_SSC_FRQ_CNT_PK_MASK;
xpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL5, val);
xpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL4, 0);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_MPLLA_CTRL5);
val &= ~PMA_MPLLA_CTRL5_MPLLA_SSC_SPD_EN;
xpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL5, val);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_MPLLA_CTRL1);
val &= ~PMA_MPLLA_CTRL1_MPLLA_FRACN_CTRL_MASK;
xpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL1, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL0);
val = u16_replace_bits(val, 33, PMA_MPLLA_CTRL0_MPLLA_MULTIPLIER_MASK);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL0, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1);
val = u16_replace_bits(val, 5, PMA_TX_GENCTRL1_VBOOST_LVL_MASK);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1, val);
val = PMA_MPLLA_CTRL3_MPLLA_BANDWIDTH(0xA016);
xpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL3, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_MISC_CTRL0);
val = u16_replace_bits(val, 0x11, PMA_MISC_CTRL0_RX_VREF_CTRL_MASK);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_MISC_CTRL0, val);
val = PMA_MISC_CTRL2_SUP_MISC(1);
xpcs_phy_write_pma(dev, PMA_MP_16G_25G_MISC_CTRL2, val);
val = PMA_VCO_CAL_REF0_VCO_REF_LD_0(0x29);
xpcs_phy_write_pma(dev, PMA_MP_16G_25G_VCO_CAL_REF0, val);
val = PMA_VCO_CAL_LD0_VCO_LD_VAL_0(0x549);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_VCO_CAL_LD0, val);
val = PMA_RX_PPM_CTRL0_RX0_CDR_PPM_MAX(0x12);
xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_PPM_CTRL0, val);
/* 3 Configure LANE0 for 10G XGMII */
xpcs_phy_write_pma(dev, PMA_MP_16G_25G_TX_MISC_CTRL0, 0x0);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_RATE_CTRL, 0x0);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL);
val &= ~PMA_MPLL_CMN_CTRL_MPLLB_SEL_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2);
val = u16_replace_bits(val, 3, PMA_TX_GENCTRL2_TX0_WIDTH_MASK);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1);
val |= PMA_TX_GENCTRL1_VBOOST_EN_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1, val);
val = PMA_TX_BOOST_CTRL_TX0_IBOOST(0xf);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_BOOST_CTRL, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_EQ_CTRL0);
val = u16_replace_bits(val, 0, PMA_TX_EQ_CTRL0_TX_EQ_PRE_MASK);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_EQ_CTRL0, val);
val = PMA_TX_EQ_CTRL1_TX_EQ_POST(0x20);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_EQ_CTRL1, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_EQ_CTRL0);
val = u16_replace_bits(val, 0x20, PMA_TX_EQ_CTRL0_TX_EQ_MAIN_MASK);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_EQ_CTRL0, val);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_RATE_CTRL, 0x0);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0);
val = u16_replace_bits(val, 0x2, PMA_RX_EQ_CTRL0_CTLE_POLE_0_MASK);
xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0, val);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0);
val = u16_replace_bits(val, 0x10, PMA_RX_EQ_CTRL0_CTLE_BOOST_0_MASK);
xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL3);
val = u16_replace_bits(val, 0x7, PMA_RX_GENCTRL3_LOS_TRSHLD_0_MASK);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL3, val);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_RX_CDR_CTRL1);
val |= PMA_RX_CDR_CTRL1_VCO_STEP_CTRL_0;
xpcs_phy_write_pma(dev, PMA_MP_16G_RX_CDR_CTRL1, val);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_RX_CDR_CTRL1);
val |= PMA_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0;
xpcs_phy_write_pma(dev, PMA_MP_16G_RX_CDR_CTRL1, val);
val = PMA_RX_MISC_CTRL0_RX0_MISC(0x12);
xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_MISC_CTRL0, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);
val = u16_replace_bits(val, 0x3, PMA_RX_GENCTRL2_RX0_WIDTH_MASK);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1);
val |= PMA_RX_GENCTRL1_RX_DIV16P5_CLK_EN_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_CDR_CTRL, 0x0);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL3);
val &= ~PMA_RX_GENCTRL3_LOS_LFPS_EN_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL3, val);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_GENCTRL4);
val &= ~PMA_RX_GENCTRL4_RX_DFE_BYP_0;
xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_GENCTRL4, val);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_ATTN_CTRL, 0x0);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0);
val = u16_replace_bits(val, 0x5, PMA_RX_EQ_CTRL0_VGA1_GAIN_0_MASK);
xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0, val);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0);
val = u16_replace_bits(val, 0x5, PMA_RX_EQ_CTRL0_VGA2_GAIN_0_MASK);
xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0, val);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_DFE_TAP_CTRL0, 0x0);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_RX_CDR_CTRL1);
val = u16_replace_bits(val, 0x1, PMA_RX_CDR_CTRL1_VCO_FRQBAND_0_MASK);
xpcs_phy_write_pma(dev, PMA_MP_16G_RX_CDR_CTRL1, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1);
val |= PMA_RX_GENCTRL1_RX_TERM_ACDC_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_IQ_CTRL0);
val = u16_replace_bits(val, 0x0, PMA_RX_IQ_CTRL0_RX0_DELTA_IQ_MASK);
xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_IQ_CTRL0, val);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL5);
val &= ~PMA_RX_EQ_CTRL5_RX_ADPT_SEL_0;
xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL5, val);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL5);
val = u16_replace_bits(val, 0x3, PMA_RX_EQ_CTRL5_RX0_ADPT_MODE_MASK);
xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL5, val);
/* 4 Configure XPCS for 10G XGMII */
xpcs_write(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_CTRL2), 0x0);
val = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DIG_CTRL1));
val |= PCS_DIG_CTRL1_USXG_EN;
xpcs_write(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DIG_CTRL1), val);
val = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_KR_CTRL1));
val = u16_replace_bits(val, 0x0, PCS_KR_CTRL1_USXG_MODE_MASK);
xpcs_write(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_KR_CTRL1), val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL0);
val = u16_replace_bits(val, 0x21, PMA_MPLLA_CTRL0_MPLLA_MULTIPLIER_MASK);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL0, val);
val = PMA_MPLLA_CTRL3_MPLLA_BANDWIDTH(0xA016);
xpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL3, val);
val = PMA_VCO_CAL_LD0_VCO_LD_VAL_0(0x549);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_VCO_CAL_LD0, val);
val = PMA_VCO_CAL_REF0_VCO_REF_LD_0(0x29);
xpcs_phy_write_pma(dev, PMA_MP_16G_25G_VCO_CAL_REF0, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_EQ_CTRL4);
val |= PMA_RX_EQ_CTRL4_CONT_ADAPT_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_EQ_CTRL4, val);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_RATE_CTRL, 0x0);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_RATE_CTRL, 0x0);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2);
val = u16_replace_bits(val, 0x3, PMA_TX_GENCTRL2_TX0_WIDTH_MASK);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);
val = u16_replace_bits(val, 0x3, PMA_RX_GENCTRL2_RX0_WIDTH_MASK);
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2);
val |= PMA_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2);
val |= PMA_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2);
val &= ~PMA_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1);
val |= PMA_TX_GENCTRL1_VBOOST_EN_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1, val);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0);
val = u16_replace_bits(val, 0x10, PMA_RX_EQ_CTRL0_CTLE_BOOST_0_MASK);
xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0, val);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_RX_CDR_CTRL1);
val |= PMA_RX_CDR_CTRL1_VCO_STEP_CTRL_0;
xpcs_phy_write_pma(dev, PMA_MP_16G_RX_CDR_CTRL1, val);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_RX_CDR_CTRL1);
val |= PMA_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0;
xpcs_phy_write_pma(dev, PMA_MP_16G_RX_CDR_CTRL1, val);
val = PMA_RX_MISC_CTRL0_RX0_MISC(0x12);
xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_MISC_CTRL0, val);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_GENCTRL4);
val &= ~PMA_RX_GENCTRL4_RX_DFE_BYP_0;
xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_GENCTRL4, val);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_RX_CDR_CTRL1);
val = u16_replace_bits(val, 0x1, PMA_RX_CDR_CTRL1_VCO_FRQBAND_0_MASK);
xpcs_phy_write_pma(dev, PMA_MP_16G_RX_CDR_CTRL1, val);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_IQ_CTRL0);
val = u16_replace_bits(val, 0x0, PMA_RX_IQ_CTRL0_RX0_DELTA_IQ_MASK);
xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_IQ_CTRL0, val);
val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL5);
val = u16_replace_bits(val, 0x3, PMA_RX_EQ_CTRL5_RX0_ADPT_MODE_MASK);
xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL5, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1);
val &= ~PMA_TX_GENCTRL1_TX_CLK_RDY_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1, val);
/* 5 Assert soft reset */
val = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DIG_CTRL1));
val |= PCS_DIG_CTRL1_VR_RST;
xpcs_write(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DIG_CTRL1), val);
/* 6 Poll for SRAM initialization done */
begin = get_timer(0);
do {
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_SRAM);
if (get_timer(begin) > 500) {
dev_err(dev, "Polling timeout, line: %d\n", __LINE__);
goto timeout;
}
mdelay(10);
} while (!(val & PMA_SRAM_INIT_DN));
/* 7 Assert SRAM external loading done */
/* Workaround */
// xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_SRAM, PMA_SRAM_EXT_LD_DN);
xpcs_phy_write(dev, XPCS_PHY_GLOBAL, XPCS_PHY_REG(GLOBAL_CTRL_EX_0), GLOBAL_CTRL_EX_0_PHY_SRAM_BYPASS);
/* 8 Poll for vendor-specific soft reset */
begin = get_timer(0);
do {
val = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DIG_CTRL1));
if (get_timer(begin) > 500) {
dev_err(dev, "Polling timeout, line: %d\n", __LINE__);
goto timeout;
}
mdelay(10);
} while (val & PCS_DIG_CTRL1_VR_RST);
/* 9 Turn receive to P0 state */
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1);
val &= ~PMA_RX_GENCTRL1_RX_RST_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL);
val &= ~PMA_RX_POWER_STATE_CTRL_RX_DISABLE_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val);
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL);
val &= ~PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val);
/* 10 Enable receiver data output from PHY */
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0);
val |= PMA_RX_GENCTRL0_RX_DT_EN_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0, val);
/* 11 Assert request of receive */
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);
val |= PMA_RX_GENCTRL2_RX_REQ_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2, val);
/* 11.1 Poll for acknowledge */
begin = get_timer(0);
do {
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);
if (get_timer(begin) > 500) {
dev_err(dev, "Polling timeout, line: %d\n", __LINE__);
goto timeout;
}
mdelay(10);
} while (val & PMA_RX_GENCTRL2_RX_REQ_0);
/* 12 Assert TX0 clock is active and stable */
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1);
val |= PMA_TX_GENCTRL1_TX_CLK_RDY_0;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1, val);
/*
* 13.1 Configure XPCS to consider Loss-of-Signal indicated by the
* PHY while evaluating the receive link status
*/
val = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DEBUG_CTRL));
val |= PCS_DEBUG_CTRL_SUPRESS_LOS_DET;
xpcs_write(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DEBUG_CTRL), val);
/*
* 13.2 Configure XPCS to deassert "receiver data enable" on
* detecting of Loss-of-Signal
*/
val = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DEBUG_CTRL));
val |= PCS_DEBUG_CTRL_RX_DT_EN_CTL;
xpcs_write(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DEBUG_CTRL), val);
/* 14 Poll for DPLL lock status for Lane 0 */
begin = get_timer(0);
do {
val = xpcs_phy_read_pma(dev, PMA_RX_LSTS);
if (get_timer(begin) > 500) {
dev_err(dev, "Polling timeout, line: %d\n", __LINE__);
goto timeout;
}
mdelay(10);
} while (!(val & PMA_RX_LSTS_RX_VALID_0));
/* 15 Assert request of receive adaptation */
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_EQ_CTRL4);
val |= PMA_RX_EQ_CTRL4_RX_AD_REQ;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_EQ_CTRL4, val);
/* 16 Poll for acknowledge */
begin = get_timer(0);
do {
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_MISC_STS);
if (get_timer(begin) > 500) {
dev_err(dev, "Polling timeout, line: %d\n", __LINE__);
goto timeout;
}
mdelay(10);
} while (!(val & PMA_MISC_STS_RX_ADPT_ACK));
/* 17 Deassert request of receive adaptation */
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_EQ_CTRL4);
val &= ~PMA_RX_EQ_CTRL4_RX_AD_REQ;
xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_EQ_CTRL4, val);
/* 18 Set the value of Config_Reg to 0 for Clause 37 autonegotiation. */
val = xpcs_read(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_AN_CTRL));
val &= ~MII_AN_CTRL_TX_CONFIG;
xpcs_write(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_AN_CTRL), val);
/* 19 Select XGMII speed */
val = xpcs_read(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_CTRL));
val &= ~MII_CTRL_SS5;
val |= MII_CTRL_SS6 | MII_CTRL_SS13;
xpcs_write(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_CTRL), val);
val = xpcs_phy_usxgmii_init_seq_2(dev);
if (val)
return val;
return 0;
timeout:
return -ETIMEDOUT;
}
u32 xpcs_phy_get_id(struct udevice *dev)
{
int ret;
u32 id;
/* First, search C73 PCS using PCS MMD */
ret = xpcs_phy_read(dev, XPCS_PHY_GLOBAL, XPCS_PHY_REG(IDCODE_HI));
if (ret < 0)
return 0xffffffff;
id = ret << 16;
ret = xpcs_phy_read(dev, XPCS_PHY_GLOBAL, XPCS_PHY_REG(IDCODE_LO));
if (ret < 0)
return 0xffffffff;
/* If Device IDs are not all zeros or all ones,
* we found C73 AN-type device
*/
if ((id | ret) && (id | ret) != 0xffffffff)
return id | ret;
return 0xffffffff;
}
drivers/net/phy/aquantia.c
+1 -1
View File
@@ -400,7 +400,7 @@ int aquantia_config(struct phy_device *phydev)
int interface = phydev->interface;
u32 val, id, rstatus, fault;
u32 reg_val1 = 0;
int num_retries = 5;
int num_retries = 200;
int usx_an = 0;
/*
include/configs/tqma7.h
+71
View File
@@ -0,0 +1,71 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Markus Niebel, Steffen Doster
*
* Configuration settings for the TQ-Systems TQMa7x SOM
*/
#ifndef __TQMA7_CONFIG_H
#define __TQMA7_CONFIG_H
#include "mx7_common.h"
#include <linux/build_bug.h>
/* MMC Configs */
#define CFG_SYS_FSL_ESDHC_ADDR 0
/*
* 128 MiB offset as recommended in Linux' `Documentation/arch/arm/booting.rst`
* TQMA7_FDT_ADDRESS = MMDC0_ARB_BASE_ADDR + 0x8000000
*/
#define TQMA7_FDT_ADDRESS 0x88000000
/* FDT_OVERLAY_ADDR = (TQMA7_FDT_ADDRESS + SZ_256K) */
#define FDT_OVERLAY_ADDR 0x88040000
/*
* DTB is loaded at 128 MiB, so use just 16 MiB more
* TQMA7_INITRD_ADDRESS = (TQMA7_FDT_ADDRESS + SZ_16M)
*/
#define TQMA7_INITRD_ADDRESS 0x89000000
#ifndef __ASSEMBLY__
static_assert(TQMA7_FDT_ADDRESS == (MMDC0_ARB_BASE_ADDR + 0x8000000));
static_assert(FDT_OVERLAY_ADDR == (TQMA7_FDT_ADDRESS + SZ_256K));
static_assert(TQMA7_INITRD_ADDRESS == (TQMA7_FDT_ADDRESS + SZ_16M));
#endif
#define TQMA7_UBOOT_OFFSET SZ_1K
#define TQMA7_MMC_UBOOT_SECTOR_START 0x2
#define TQMA7_MMC_UBOOT_SECTOR_COUNT 0x7fe
#define TQMA7_SPI_FLASH_SECTOR_SIZE SZ_64K
#define TQMA7_SPI_UBOOT_START 0x1000
#define TQMA7_SPI_UBOOT_SIZE 0xf0000
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* u-boot.img base address for SPI-NOR boot */
#define CFG_SYS_UBOOT_BASE (QSPI0_ARB_BASE_ADDR + TQMA7_UBOOT_OFFSET + CONFIG_SPL_PAD_TO)
/*
* All the defines above are for the TQMa7x SoM
*
* Now include the baseboard specific configuration
*/
#if IS_ENABLED(CONFIG_MBA7)
#include "tqma7_mba7.h"
#else
#error "No baseboard for the TQMa7x SOM defined!"
#endif
#endif /* __TQMA7_CONFIG_H */
include/configs/tqma7_mba7.h
+16
View File
@@ -0,0 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Markus Niebel, Steffen Doster
*
* Configuration settings for the TQ-Systems MBa7x carrier board for
* TQMa7x module.
*/
#ifndef __CONFIG_TQMA7_MBA7_H
#define __CONFIG_TQMA7_MBA7_H
#define CFG_MXC_UART_BASE UART6_IPS_BASE_ADDR
#endif /* __CONFIG_TQMA7_MBA7_H */
include/configs/verdin-imx95.h
+27
View File
@@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* Copyright (c) Toradex */
#ifndef __VERDIN_IMX95_H
#define __VERDIN_IMX95_H
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
/* For 32GB modules: 2GB from 0x80000000..0xffffffff, 30GB above.
* Actual size is determined at runtime.
*/
#define SZ_30G _AC(0x780000000, ULL)
/* The first 256MB of SDRAM is reserved for firmware (Cortex M7) */
#define PHYS_SDRAM_FW_RSVD SZ_256M
#define CFG_SYS_INIT_RAM_ADDR PHYS_SDRAM
#define CFG_SYS_INIT_RAM_SIZE SZ_2M
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define PHYS_SDRAM (0x80000000 + PHYS_SDRAM_FW_RSVD)
#define PHYS_SDRAM_SIZE (SZ_2G - PHYS_SDRAM_FW_RSVD)
#define PHYS_SDRAM_2_SIZE SZ_30G
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
#endif
include/env.h
+20
View File
@@ -9,6 +9,7 @@
#ifndef __ENV_H
#define __ENV_H
#include <config.h>
#include <compiler.h>
#include <stdbool.h>
#include <linux/types.h>
@@ -160,6 +161,25 @@ bool env_get_autostart(void);
*/
int env_set(const char *varname, const char *value);
/**
* env_set_runtime() - set an environment variable if
* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is set.
*
* This is equivalent to env_set(), but does nothing if
* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is unset.
*
* @varname: Variable to adjust
* @value: Value to set for the variable, or NULL or "" to delete the variable
* @return 0 if OK or !CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG, 1 on error
*/
static inline int env_set_runtime(const char *varname, const char *value)
{
if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
return env_set(varname, value);
return 0;
}
/**
* env_get_ulong() - Return an environment variable as an integer value
*
include/env/tq/spi.env
Vendored
+4
View File
@@ -20,4 +20,8 @@ update_uboot_spi=
fi;
fi;
#ifdef CONFIG_CMD_QSPIHDR
write_uboot_spi=qspihdr init ${loadaddr} ${filesize} safe;
#else
write_uboot_spi=sf update "${loadaddr}" "${uboot_spi_start}" "${filesize}"
#endif
include/init.h
+7
View File
@@ -14,6 +14,12 @@
#include <linux/types.h>
struct ram_alias_check {
void *probe_addr;
void *alias_addr;
long size;
};
/*
* In case of the EFI app the UEFI firmware provides the low-level
* initialisation.
@@ -88,6 +94,7 @@ int dram_init(void);
int dram_init_banksize(void);
long get_ram_size(long *base, long size);
long probe_ram_size_by_alias(const struct ram_alias_check *checks);
phys_size_t get_effective_memsize(void);
int testdram(void);